CN102938416A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102938416A CN102938416A CN2011102345031A CN201110234503A CN102938416A CN 102938416 A CN102938416 A CN 102938416A CN 2011102345031 A CN2011102345031 A CN 2011102345031A CN 201110234503 A CN201110234503 A CN 201110234503A CN 102938416 A CN102938416 A CN 102938416A
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Abstract
The invention relates to a semiconductor device which comprises a substrate, a channel region, drain/source regions, a gate piling structure, side walls and raised drains/sources. The channel region is located in the substrate, the drain/source regions are located in the substrate, the gate piling structure is located on the channel region, the side walls are located on two sides of the gate piling structure, the raised drains/sources are located on the drain/source regions on two sides of the side walls, and drain/source contact metal silicide is located on the raised drains/sources. The semiconductor device is characterized in that epitaxial growth ultrathin metal silicide is arranged between the drain/source regions and the raised drains/sources. According to the semiconductor device and a manufacturing method thereof, the epitaxial growth ultrathin metal silicide is arranged below the raised drains/sources so that the raised drains/sources can be directly contacted with the channel region, high resistance regions between the side walls and the raised drains/sources are prevented, drain/source parasitic resistance and contact resistance are further reduced, and the device performances are further improved.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, relate to especially a kind of novel metal oxide semiconductor field effect transistor (MOSFET) device architecture and manufacture method thereof with lifting source on the Ultra Thin Epitaxial silicide/leakage (RSD).
Background technology
Along with technology node continues to advance, reduce as the integrated circuit characteristic size of representative is lasting take MOS transistor grid width or channel length, so that channel resistance decreases, improved to a certain extent device performance.Yet brought such as series of problems such as short-channel effects after the channel shortening, suppressed the further lifting of device performance.In order to overcome short-channel effect, the degree of depth is leaked in transistorized source must be correspondingly or with more vast scale reduction so that the source leaking joint becomes more and more shallow, for example only for long channel device source-and-drain junction dark 70%, so the source is omitted living resistance and is sharply increased.
When physical gate length entered inferior 30nm zone, the source was omitted living resistance and is increased obstruction impact on device performance and surpassed channel resistance and reduce the benefit of bringing.Therefore, how effectively to reduce the leakage of parasitic source and become huge challenge with the boost device performance.
In traditional solution, high concentration ground mixes to reduce dead resistance to propose to leak as far as possible to the source.But because solid solubility limit and short-channel effect control require the sudden change doped interface, the source is leaked to mix and is become more and more limited.
In order to address this problem, some schemes have been proposed.Except proposed by the present patent application people for example for the new device structure of metal silicide source drain MOSFET, industry is also used by selective epitaxial (SEG) thereby the lifting source of making is leaked by thickening junction depth and leaked film resistor and reduce parasitic source-drain resistances to reduce the source.Referring to accompanying drawing 1, be the structural representation of this lifting source drain MOSFET.Wherein, deposition forms gate dielectric 3, grid 4 on the substrate 1 that is surrounded by STI2, the source is leaked low concentration and is injected formation source drain extension region 5A, then gate dielectric 2 and grid 3 both sides form side wall 6, the source is leaked high concentration and is injected formation source leakage heavily doped region 5B, carry out SEG take side wall 6 as mask, form lifting source leakage (RSD) district 5C so that heavily doped region 5B part extension is leaked in the source of side wall 6 both sides.In order further to reduce resistance, can after SEG, form metal silicide 7 at RSD district 5C, consist of the source drain contact.
Although the leakage upper metal suicide source drain contact that forms in this lifting source can reduce to a certain extent the source and omit living resistance, this structure still has the leeway of sizable further improvement structure, improving performance.Particularly in zone shown in Fig. 1 ellipse, because SEG leaks the impact in material crystal orientation in the source that is subjected to, epitaxial growth speed is inconsistent on the different directions, so that have the space between RSD district 5C and the side wall 6, and then this space can't be filled fully by metal silicide 7, therefore zone shown in Figure 1 consists of high resistance area, be present in channel region to the RSD 5C between the metal silicide 7, so that living resistance is omitted in the source is still larger.Therefore, simple super shallow silicon source leakage can't further reduce the source ohmic leakage effectively with the simple superposition of silicon RSD.
Generally speaking, current lifting source drain MOSFET can't further effectively reduce the source ohmic leakage, needs a kind of improved new device structure and manufacture method thereof badly.
Summary of the invention
The invention provides a kind of semiconductor device, comprise substrate, be arranged in substrate channel region, be arranged in substrate source-drain area, be positioned at gate stack structure on the channel region, be positioned at the side wall of gate stack structure both sides, the source drain contact metal silicide that leak in the lifting source is leaked, is positioned in the lifting source that is positioned on the source-drain area of side wall both sides, it is characterized in that: also have epitaxially grown super thin metal silicide between source-drain area and the leakage of lifting source.
Wherein, source-drain area comprises source drain extension region and heavy-doped source drain region.
Wherein, epitaxially grown super thin metal silicide contacts with the channel region of side wall below.
Wherein, epitaxially grown super thin metal silicide comprises NiSi
2-y(0≤y＜1), Ni
1-xPt
ySi
2-y(0＜x＜1,0≤y＜1), CoSi
2-y(0≤y＜1) or Ni
1-xCo
ySi
2-y(0＜x＜1,0≤y＜1).
Wherein, substrate is Si, SOI, SiGe or SiC.
Wherein, drain contact metal silicide in source comprises CoSi
2, NiSi, NiPtSi, NiCoSi
2
Wherein, gate stack structure comprises gate dielectric and grid.Wherein, gate dielectric comprises silica, silicon oxynitride or high k material, and grid comprises doped polycrystalline silicon, metal, metal alloy or metal nitride.
Wherein, promote the source bottom pour ladle and draw together Si, Si
1-xGe
xOr Si
1-xC
x(0＜x＜1).
When wherein, leak in the lifting source it is carried out N-shaped or p-type in-situ doped.
The present invention also provides a kind of method, semi-conductor device manufacturing method, comprising: form gate stack structure and side wall at substrate; In substrate, form source-drain area, constituting channel district between the source-drain area; In source-drain area, form epitaxially grown super thin metal silicide; Epitaxially grown super thin metal silicide in the side wall both sides forms the lifting source and leaks; Leak formation source drain contact metal silicide in the lifting source.
Wherein, successively take gate stack structure and side wall as mask, twice injection forms the source-drain area that source drain extension region and heavy-doped source drain region consist of.
Wherein, deposit the first metal layer on source-drain area, annealing is so that the pasc reaction in the first metal layer and the source-drain area and divest unreacted the first metal layer, forms epitaxially grown super thin metal silicide and contacts with channel region below the side wall.Wherein, the first metal layer comprises Ni, Co, Pt and alloy thereof, and thickness is 1 to 5nm, and formed epitaxially grown super thin metal silicide comprises NiSi
2-y(0≤y＜1), Ni
1-xPt
ySi
2-y(0＜x＜1,0≤y＜1), CoSi
2-y(0≤y＜1) or Ni
1-xCO
ySi
2-y(0＜x＜1,0≤y＜1).
Wherein, adopting MBE, CVD or ALD to form the lifting source at epitaxially grown super thin metal silicide leaks.
Wherein, promote the source bottom pour ladle and draw together Si, Si
1-xGe
xOr Si
1-xC
xWhen leak (0＜x＜1), lifting source it is carried out N-shaped or p-type in-situ doped.
Wherein, leak deposit the second metal level in the source that promotes, annealing so that the second metal level in leaking with the lifting source pasc reaction and divest unreacted the second metal level, formation source drain contact metal silicide.Wherein, the second metal level comprises Ni, Co, Pt and alloy thereof, and thickness is 1 to 30nm, and formed source drain contact metal silicide comprises CoSi
2, NiSi, NiPtSi, NiCoSi
2
Wherein, 500 to 850 ℃ of lower annealing.
Wherein, substrate is Si, SOI or SiGe.
According to Novel MOS FET device of the present invention and manufacture method thereof, owing in the side of leaking down, lifting source epitaxially grown super thin metal silicide being arranged, it is directly contacted with channel region, avoid occurring side wall and the source high resistance area between leaking, omit living resistance and contact resistance thereby further reduced the source, significantly improved device performance.
Purpose of the present invention, and in these other unlisted purposes, in the scope of the application's independent claims, satisfied.Embodiments of the invention are limited in the independent claims, and specific features is limited in its dependent claims.
Description of drawings
What Fig. 1 had shown prior art is formed with the MOSFET generalized section of Metal-silicides Contact at RSD; And
Fig. 2 to Fig. 8 has shown generalized section corresponding to each step according to Novel MOS FET device making method of the present invention.
Embodiment
Also describe feature and the technique effect thereof of technical solution of the present invention referring to accompanying drawing in conjunction with schematic embodiment in detail, disclose Novel MOS FET structure and the manufacture method thereof that can further effectively reduce the source ohmic leakage.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score etc. can be used for modifying various device architectures.These are modified is not space, order or the hierarchical relationship of hint institute modification device architecture unless stated otherwise.
At first, with reference to Fig. 2, form basic structure.Substrate 10 is provided, in substrate 10, form insulation isolated area 11, then adopt the conventional process such as CVD to use shallow trench isolation that the filling insulating material shallow trenchs such as oxide, nitrogen oxide form from (STI) 11 such as form shallow trench by traditional photoetching/etching technics etching in substrate 10, wherein substrate 10 can be body silicon, silicon-on-insulator (SOI), SiGe, SiC and other any (siliceous) semi-conducting materials that needs according to the device electric property.The STI11 degree of depth forms annular ditch groove less than substrate 10 thickness in substrate 10, the substrate 10 that is surrounded by STI11 is equivalent to the active area of device.Deposit successively gate dielectric 12, grid 13 by methods such as CVD, and etching forms gate stack structure.Gate dielectric 12 can be the low k dielectrics such as silica, silicon oxynitride, also can be hafnium oxide, tantalum oxide, the contour k medium of barium titanate.Grid 13 can be doped polycrystalline silicon or metal gates, and metal comprises the common metal materials such as Al, Ti, Cu, W, Au, Ag, and grid also can comprise the alloy of these metals and the nitride of these metals.Take gate stack structure as mask, Implantation is leaked in the source of substrate 10 being carried out low concentration, forms low-doped source drain extension region 14 (also being the LDD district), and these extension area 14 junction depths are more shallow, and doping type and concentration need according to the device conductive characteristic and sets.Substrate 10 in the gate stack structure both sides forms side walls 15, and for example first uniform deposition nitride layer anisotropic etching then only stays nitride layer in the gate stack structure both sides, forms sidewall structure.Take side wall 15 as mask, carry out the high concentration source and leak Implantation, form heavy-doped source drain region 16, wherein heavy-doped source drain region 16 is thicker than source drain extension region 14.
Secondly, with reference to Fig. 3, form metal level in basic structure.At mode deposit one thin metal layer 17 of whole basic structure by for example sputter or evaporation, as the primer of metal silicide, its material is Ni, Co, Pt or its alloy, and its thickness is about 1 to 5nm.Particularly, metal level 17 can be thickness less than the Co layer of 5nm, thickness less than or equal to the Ni layer of 4nm, thickness less than the Ni-Pt alloy-layer (wherein Pt content is less than or equal to 8% weight) of 4nm, the thickness Ni-Co alloy-layer (wherein Co content is less than or equal to 10% weight) less than or equal to 4nm.As shown in Figure 3, metal level 17 cover gate 13, side wall 15, heavy-doped source drain region 16 and STI11 have especially covered the zone that side wall 15 and heavy-doped source drain region 16 join, so that the metal silicide that forms after a while near-earth contact channel region as far as possible.
Again, with reference to Fig. 4, form metal silicide.Total is annealed under 500 to 850 ℃ and divested unreacted metal level 17, so that the silicon of the surface part in the metal in the metal level 17 and heavy-doped source drain region 16 reacts, epitaxial growth forms ultra-thin metal silicide 18, and its crystal orientation is consistent with heavy-doped source drain region 16 or substrate 10.Extension super thin metal silicide 18 is positioned at the surface in heavy-doped source drain region 16, the interface along channel direction of itself and source drain extension region 14 (also being extension super thin metal silicide 18 and the interface of channel region) is parallel to the side of side wall 15 and preferably coplanar, in fact is equivalent to extension super thin metal silicide 18 and directly contacts with the channel region of side wall 15 belows.The interface along the vertical-channel direction of extension super thin metal silicide 18 and source drain extension region is parallel to substrate 10 and is positioned at the inside in heavy-doped source drain region 16, also is that the unreacted silicon of part is still contained in heavy-doped source drain region 16.Material according to metal level 17 is different, and formed extension super thin metal silicide 18 materials can comprise NiSi
2-y(0＜=y＜1), Ni
1-xPt
ySi
2-y(0＜x＜1,0＜=y＜1), CoSi
2-y(0＜=y＜1) or Ni
1-xCo
ySi
2-y(0＜x＜1,0＜=y＜1), its thickness can be 15nm.Because material, thickness and the treatment temperature of selected metal level 17, that formed extension super thin metal silicide 18 has is 10 close with silicon-containing substrate, substantially equate or identical lattice constant, therefore is easy on substrate 10 epitaxial growth metal silicide 18 and the source of epitaxial growth lifting thereon and leaks.Because extension super thin metal silicide 18 is pressed close to side wall 15, greatly reduce the contact resistance between source leakage and the channel region.
Then, with reference to Fig. 5, form the lifting source at extension super thin metal silicide and leak (raised drain/source).Use molecular beam epitaxy (MBE), CVD, ald (ALD) etc. technique forms the lifting sources at extension super thin metal silicide 18 and leaks 19, and it can be Si that 19 materials are leaked in the source that wherein promotes, or needs and employing Si according to type of device and stress
1-xGe
xOr Si
1-xC
x(0＜x＜1).It can be N-shaped or p-type by original position (in-situ) doping or later stage dopant implant that the lifting source leaks 19, consists of NMOS or PMOS.It should be noted that since extension super thin metal silicide 18 crystal orientation according to heavy-doped source drain region 16 or substrate 10 and difference, the speed of growth is inconsistent in different directions in epitaxially grown lifting source leakage 19, makes between itself and the side wall 15 to have the gap.In traditional handicraft owing to there not being the existence of extension super thin metal silicide 18, the source is omitted living resistance and can't be effectively reduced, and the extension super thin metal silicide 18 that leaks between 16 by the leakage 19 of lifting source and heavy-doped source among the present invention effectively reduces dead resistance, has significantly improved device performance.In addition, selective epitaxial growth (SEG) Si, SiGe or SiC on epitaxially grown super thin metal silicide 18 not only can be used for the formation of the lifting source leakage of MOSFET, also can be used for other semiconductor device, for example photoelectric device.
Then, with reference to Fig. 6, another metal level of deposit on total.Mode by for example sputter or evaporation on whole basic structure deposits another thin metal layer 20, and as the primer of source drain contact metal silicide, its material is Ni, Co, Pt or its alloy, and its thickness is about 1 to 30nm.Particularly, metal level 20 can be the Ni-Co alloy-layer (wherein Co content is less than or equal to 10% weight) of the Ni layer of thickness 1-30nm, the Ni-Pt alloy-layer of thickness 1-30nm (wherein Pt content is less than or equal to 8% weight), thickness 1-30nm.As shown in Figure 6, metal level 20 cover gate 13, side wall 15, the leakage 19 of lifting source and STI11 have especially filled the space between the leakage 19 of lifting source and the side wall 15.
Subsequently, with reference to Fig. 7, form source drain contact metal silicide.Total is annealed under 500 to 850 ℃ and divested unreacted metal level 20, so that the silicon of the surface part of the metal in the metal level 20 and lifting source leakage 19 reacts, carry out self-alignment silicide technology (SALICIDE) and form source drain contact metal silicide 21.Source drain contact metal silicide 21 is positioned at the surface of lifting source leakage 19, itself and lifting source leak that 19 the interface along channel direction is parallel to the side of side wall 15 and at a certain distance away from side wall 15, itself and lifting source are leaked 19 the interface along the vertical-channel direction and are parallel to substrate 10 and are positioned at the lifting source and leak 19 inside, and also namely the lifting source is leaked 19 and still contained the unreacted silicon of part.Material according to metal level 20 is different, and formed source drain contact metal silicide 21 materials can comprise CoSi
2, NiSi, NiPtSi, NiCoSi
2It should be noted that source drain contact metal silicide 21 generation types and thickness all are different from the extension super thin metal silicide 18 of its below, the resistance of source drain contact metal silicide 21 is lower than extension super thin metal silicide 18 owing to its thickness is thicker.Although have the gap between source drain contact metal silicide 21 and the side wall 15, the extension super thin metal silicide 18 of its below still can provide good source leakage conductance electric pathway, has reduced dead resistance.
At last, with reference to Fig. 8, carry out the manufacturing of follow-up MOS device.Deposit the interlayer dielectric layer (ILD) 22 that for example consists of for silica, silicon oxynitride (can mix C), porous material, low-k materials in total.Cmp planarization ILD22 is until expose grid 13.Photoetching in ILD22/dry etching forms drain contact hole, source, then fills drain contact material in source in drain contact hole, source, and for example W, Al, Ti, Ta and nitride thereof form source drain contact 23.
The MOSFET device architecture that forms at last comprises: substrate 10, STI11 in the substrate 10 surrounds and limits active area, be formed with the gate stack that is consisted of by gate dielectric 12 and grid 13 on the active area, has source drain extension region 14 in the substrate 10 of gate stack both sides, has side wall 15 on the substrate 10 of gate stack structure both sides, has heavy-doped source drain region 16 in the substrate 10 of side wall 15 both sides, 16 surfaces, heavy-doped source drain region have epitaxially grown super thin metal silicide 18, epitaxially grown super thin metal silicide 18 tops of side wall 15 both sides have the lifting source leakage 19 of SEG growth, the lifting source is leaked and is formed active drain contact metal silicide 21 on 19, ILD layer 22 covers STI11, the lifting source leaks 19, source drain contact metal silicide 21, side wall 15, source drain contact 23 pass ILD layer 22 and electrically contact with source drain contact metal silicide 21.Wherein, the interface along channel direction of epitaxially grown super thin metal silicide 18 and source drain extension region 14 (or channel region) is parallel to the side of side wall 15 and preferably coplanar, eliminated the blind area of metal silicide, thereby so that living resistance is omitted in the source further reduces.
According to Novel MOS FET device of the present invention and manufacture method thereof, owing to having increased epitaxially grown super thin metal silicide in the side of leaking down, lifting source, it is directly contacted with channel region, avoid occurring side wall and the source high resistance area between leaking, omit living resistance and contact resistance thereby further reduced the source, significantly improved device performance.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and device architecture is made various suitable changes and equivalents.In addition, can be made by disclosed instruction and manyly may be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, purpose of the present invention does not lie in to be limited to as being used for and realizes preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.
Claims (20)
1. semiconductor device, comprise substrate, be arranged in substrate channel region, be arranged in substrate source-drain area, be positioned at gate stack structure on the channel region, be positioned at the side wall of gate stack structure both sides, the source drain contact metal silicide that leak in the lifting source is leaked, is positioned in the lifting source that is positioned on the source-drain area of side wall both sides, it is characterized in that: also have epitaxially grown super thin metal silicide between source-drain area and the leakage of lifting source.
2. semiconductor device as claimed in claim 1, wherein, source-drain area comprises source drain extension region and heavy-doped source drain region.
3. semiconductor device as claimed in claim 1, wherein, epitaxially grown super thin metal silicide contacts with the channel region of side wall below.
4. semiconductor device as claimed in claim 1, wherein, epitaxially grown super thin metal silicide comprises NiSi
2-y(0≤y＜1), Ni
1-xPt
ySi
2-y(0＜x＜1,0≤y＜1), CoSi
2-y(0≤y＜1) or Ni
1-xCO
ySi
2-y(0＜x＜1,0≤y＜1).
5. semiconductor device as claimed in claim 1, wherein, substrate is Si, SOI, SiGe or SiC.
6. semiconductor device as claimed in claim 1, wherein, source drain contact metal silicide comprises CoSi
2, NiSi, NiPtSi, NiCoSi
2
7. semiconductor device as claimed in claim 1, wherein, gate stack structure comprises gate dielectric and grid.
8. semiconductor device as claimed in claim 7, wherein, gate dielectric comprises silica, silicon oxynitride or high k material, grid comprises doped polycrystalline silicon, metal, metal alloy or metal nitride.
9. semiconductor device as claimed in claim 1 wherein, promotes the source bottom pour ladle and draws together Si, Si
1-xGe
xOr Si
1-xC
x(0＜x＜1).
10. semiconductor device as claimed in claim 1 wherein, carries out original position N-shaped or p-type doping to it when leak in the lifting source.
11. a method, semi-conductor device manufacturing method comprises:
Form gate stack structure and side wall at substrate;
In substrate, form source-drain area, constituting channel district between the source-drain area;
In source-drain area, form epitaxially grown super thin metal silicide;
Leak in the lifting source on the epitaxially grown super thin metal silicide of side wall both sides;
Leak formation source drain contact metal silicide in the source that promotes.
12. such as the method, semi-conductor device manufacturing method of claim 11, wherein, successively take gate stack structure and side wall as mask, twice injection forms the source-drain area that source drain extension region and heavy-doped source drain region consist of.
13. the method, semi-conductor device manufacturing method such as claim 11, wherein, deposit the first metal layer on source-drain area, annealing is so that the pasc reaction in the first metal layer and the source-drain area and divest unreacted the first metal layer, forms epitaxially grown super thin metal silicide and contacts with channel region below the side wall.
14. such as the method, semi-conductor device manufacturing method of claim 13, wherein, the first metal layer comprises Ni, Co, Pt and alloy thereof, thickness is 1 to 5nm, and formed epitaxially grown super thin metal silicide comprises NiSi
2-y(0≤y＜1), Ni
1-xPt
ySi
2-y(0＜x＜1,0≤y＜1), CoSi
2-y(0≤y＜1) or Ni
1-xCO
ySi
2-y(0＜x＜1,0≤y＜1).
15. such as the method, semi-conductor device manufacturing method of claim 11, wherein, adopt MBE, CVD or ALD to form the lifting source at epitaxially grown super thin metal silicide and leak.
16. such as the method, semi-conductor device manufacturing method of claim 11, wherein, promote the source bottom pour ladle and draw together Si, Si
1-xGe
xOr Si
1-xC
xWhen leak (0＜x＜1), lifting source it is carried out N-shaped or p-type in-situ doped.
17. such as the method, semi-conductor device manufacturing method of claim 11, wherein, leak deposit the second metal level in the lifting source, annealing so that the second metal level in leaking with the lifting source pasc reaction and divest unreacted the second metal level, formation source drain contact metal silicide.
18. such as the method, semi-conductor device manufacturing method of claim 17, wherein, the second metal level comprises Ni, Co, Pt and alloy thereof, thickness is 1 to 30nm, and formed source drain contact metal silicide comprises CoSi
2, NiSi, NiPtSi, NiCoSi
2
19. such as the method, semi-conductor device manufacturing method of claim 13 or 17, wherein, 500 to 850 ℃ of lower annealing.
20. such as the method, semi-conductor device manufacturing method of claim 11, wherein, substrate is Si, SOI, SiGe or SiC.
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| CN104218081A (en) * | 2013-05-31 | 2014-12-17 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| CN105428407A (en) * | 2015-11-16 | 2016-03-23 | 株洲南车时代电气股份有限公司 | IGBT device and forming method therefor |
| CN108305901A (en) * | 2018-02-12 | 2018-07-20 | 上海集成电路研发中心有限公司 | A kind of FinFET and preparation method thereof |
| CN110828577A (en) * | 2019-11-21 | 2020-02-21 | 海光信息技术有限公司 | Semiconductor device and method for manufacturing the same |
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| US20090023261A1 (en) * | 2007-07-20 | 2009-01-22 | Sony Corporation | Method for manufacturing semiconductor device |
| CN101483191A (en) * | 2008-01-07 | 2009-07-15 | 国际商业机器公司 | Semiconductor structures and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104218081A (en) * | 2013-05-31 | 2014-12-17 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| CN105428407A (en) * | 2015-11-16 | 2016-03-23 | 株洲南车时代电气股份有限公司 | IGBT device and forming method therefor |
| CN105428407B (en) * | 2015-11-16 | 2018-07-13 | 株洲南车时代电气股份有限公司 | A kind of IGBT device and forming method thereof |
| CN108305901A (en) * | 2018-02-12 | 2018-07-20 | 上海集成电路研发中心有限公司 | A kind of FinFET and preparation method thereof |
| WO2019153724A1 (en) * | 2018-02-12 | 2019-08-15 | 上海集成电路研发中心有限公司 | Finfet device and preparation method therefor |
| CN110828577A (en) * | 2019-11-21 | 2020-02-21 | 海光信息技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN110828577B (en) * | 2019-11-21 | 2023-09-26 | 海光信息技术(成都)有限公司 | Semiconductor device and method for manufacturing the same |
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