CN105428407B - A kind of IGBT device and forming method thereof - Google Patents
A kind of IGBT device and forming method thereof Download PDFInfo
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- CN105428407B CN105428407B CN201510786049.9A CN201510786049A CN105428407B CN 105428407 B CN105428407 B CN 105428407B CN 201510786049 A CN201510786049 A CN 201510786049A CN 105428407 B CN105428407 B CN 105428407B
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- 210000003323 beak Anatomy 0.000 abstract description 20
- 239000000758 substrate Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
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- 238000002513 implantation Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
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- 238000010586 diagram Methods 0.000 description 2
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- -1 phosphonium ion Chemical class 0.000 description 2
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- 229910010271 silicon carbide Inorganic materials 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
This application provides a kind of IGBT devices, including：Semiconductor structure, the semiconductor structure include drift region, and well region, emitter region, the emitter region top surface is higher by the upper surface of the semiconductor structure, and bottom surface is 0~1 μm at a distance from the upper surface of the semiconductor structure；The emitter being electrically connected between the emitter region of the well region both sides and with the emitter region, grid region positioned at the emitter both sides, the grid region has step part and horizontal component, the step part and the horizontal component are structure as a whole, the horizontal component in the grid region covers well region and drift region of the emitter region backwards to the emitter side, and the step part covers the top surface of at least partly described emitter region.Influence this configuration avoids grid region end " beak " structure to device threshold voltage, meanwhile, cut-off current is shortened in the path of well region, reduces loss, and avoid latch-up to the greatest extent.
Description
Technical field
This application involves technical field of semiconductors, more particularly to a kind of IGBT device and forming method thereof.
Background technology
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviation IGBT) is by double
The compound full-control type voltage driven type power semiconductor of polar form triode (BJT) and insulating gate type field effect tube (MOSFET) composition
Device has the low conduction voltage drop of the high input impedance and power transistor (i.e. huge transistor, abbreviation GTR) of MOSFET element concurrently
Both sides advantage, to be widely applied to every field.
IGBT device structure as shown in Figure 1, be disposed with collecting zone 101, buffering area from bottom to top in the prior art
102, drift region 103 and in the drift region, the well region 104 of upper surface and drift region upper surface flush are located at well region upper table
Emitter 105 in face is located in the well region, respectively with the emitter region 106 of two side contacts of the emitter, the covering trap
Area, and part covers the grid region 107 of the emitter region, wherein grid region includes grid and the gate oxidation that is wrapped on the outside of grid
Layer.
However, the IGBT device of such structure, the gate oxide close to the grid region end of emitter region side is easy to form " bird
Mouth " structure.If Fig. 2 is the schematic enlarged-scale view in Fig. 1 in dotted line frame, wherein 105 be emitter part, 107 be grid region part, empty
The part that line circle is drawn is " beak " structure that gate oxide is formed.And grid region end " beak " if structure with below grid region
Well region 104 contacts, and can be had an impact to device threshold voltage.
It, usually will by emitter region part to prevent grid region end " beak " structure from being had an impact to device threshold voltage
The grid region of " beak " part keeps apart with well region.However, such method needs the upper surface of emitter region to completely attach to " beak " portion
Cut-off current is caused to bypass path length (such as Fig. 1 and Fig. 3 of emitter region so that the lateral distance of emitter region is big in the grid region divided
In dotted arrow), loss is big, and is easy to cause latch-up.
Invention content
In order to solve the above technical problems, a kind of IGBT device of the embodiment of the present application offer and forming method thereof, avoids grid
Influence of area end " beak " structure to device threshold voltage, meanwhile, cut-off current is shortened in the path of well region, reduces damage
Consumption, and latch-up is avoided to the greatest extent.
To solve the above problems, an embodiment of the present invention provides following technical solutions：
A kind of IGBT device, including：
Semiconductor structure, the semiconductor structure include the drift of upper surface and the upper surface flush of the semiconductor structure
Area, the well region being located in the upper surface of the drift region, and it is located at the well region both sides, and top surface is higher by the semiconductor junction
The emitter region of the upper surface of structure, the bottom surface of the emitter region are 0~1 μm at a distance from the upper surface of the semiconductor structure；
Emitter, the emitter are located between the emitter region of the well region both sides, the emitter and the emitter region
Electrical connection；
Grid region, the grid region are located at the emitter both sides, and the grid region has step part and a horizontal component, described
Exponent part and the horizontal component are structure as a whole, and the horizontal component in the grid region covers the emitter region backwards to the emitter
The well region of side and drift region, the step part cover the top surface of at least partly described emitter region.
Preferably, the side of the step part in the grid region and the angle of the horizontal component in the grid region are 45 °~135 °.
Preferably, the semiconductor structure further includes the outer well region in the upper surface of the drift region, the outer trap
Area surrounds the side and lower surface of the well region；
The conduction type of the outer well region is identical as the conduction type of the drift region, and the impurity doping of the outer well region is dense
Impurity doping concentration of the degree more than the drift region.
Preferably, the semiconductor structure further include positioned at the well region both sides emitter region between well region in, and on
The lateral length of the interior well region on surface and the well region upper surface flush, the interior well region is more than the transverse direction length of the emitter
Degree；
The conduction type of the interior well region is identical as the conduction type of the well region, the impurity doping concentration of the interior well region
More than the impurity doping concentration of the well region.
Preferably, there is the interior well region between the emitter region groove structure, the emitter to be located at the groove structure
It is interior.
A kind of forming method of IGBT device, including：
Semiconductor structure is provided, the upper layer of the semiconductor structure is drift region；
Lug boss is formed in the drift region upper surface；
Grid region is formed in the lug boss both sides, the grid region has step part and horizontal component, the step part
It is structure as a whole with the horizontal component, the horizontal component in the grid region covers the drift region of the lug boss side, described
Lug boss top surface described in exponent part covering part, and the step part of the lug boss both sides is in the lug boss top surface not phase
Even；
First conduction type doping is carried out to the lug boss top surface, forms well region, the lateral length of the well region is more than
The lateral length of the lug boss；
Second conduction type doping carried out to the lug boss top surface, the doping depth of second conduction type doping with
The difference in height of the lug boss is -1~1 μm；
The part that the lug boss is not covered by the grid region is etched, emitter region is formed；
Emitter is formed between the emitter region, the emitter is electrically connected with the emitter region.
Preferably, the cross section of the lug boss is isosceles trapezoid.
Preferably, the angle on the bevel edge of the isosceles trapezoid and bottom edge is 45 °~135 °.
Preferably, it after the formation lug boss, is formed before grid region, further includes：
The doping of the second conduction type is carried out to the upper surface of the semiconductor structure, forms outer well region, the outer well region
Lateral length be more than the well region lateral length.
Preferably, it after the formation grid region, is formed before well region, further includes：
Second conduction type doping is carried out to the lug boss top surface, forms outer well region, the lateral length of outer well region is more than
The lateral length of the well region.
Preferably, it after the formation emitter region, is formed before emitter, further includes：
First conduction type doping is carried out to the lug boss top surface, forms interior well region, the lateral length of the interior well region
More than the lateral length of the emitter, it is less than the lateral length of the lug boss.
Preferably, the etching depth of the etching lug boss is more than or equal to the height of the lug boss, is less than described
The doping depth of the height of lug boss and the well region and.
Preferably, the etching depth of the etching lug boss is more than the height of the lug boss, is less than the protrusion
The doping depth of the height in portion and the interior well region and.
Preferably, described to form lug boss in the drift region upper surface, including：
The upper surface for etching the drift region forms lug boss in the drift region upper surface.
Compared with prior art, beneficial effects of the present invention are：
Since in IGBT device of the present invention, the top surface of the emitter region is higher by the upper surface of the semiconductor structure, to
The end in the grid region of covering emitter region side is raised so that the endpoint of grid region step part is the end in grid region.And grid region platform
The endpoint of exponent part is located at the top surface of the emitter region, can be detached with well region, avoids grid region end " beak " structure to device
The influence of part threshold voltage.Simultaneously as cut-off current surrounds the edge of emitter region, the bottom of the emitter region in the path of well region
Face is 0~1 μm at a distance from the upper surface of the semiconductor structure, so as to shorten cut-off current in the path of well region, is reduced
Loss, and avoid latch-up to the greatest extent.
Description of the drawings
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present application, for
For those of ordinary skill in the art, without having to pay creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1~Fig. 3 is prior art IGBT device cross-sectional view；
Fig. 4 is the IGBT device cross-sectional view that the embodiment of the present invention one provides；
Fig. 5~Fig. 6 is IGBT device cross-sectional view provided by Embodiment 2 of the present invention；
Fig. 7 is the flow chart for the IGBT device forming method that the embodiment of the present invention three provides；
Fig. 8~Figure 19 is the cross-sectional view that the embodiment of the present invention three provides IGBT device；
Figure 20~Figure 21 is the IGBT device cross-sectional view of the present invention.
Specific implementation mode
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
As stated in the background art, the IGBT device of existing structure, the gate oxide close to the grid region end of emitter region side
It is easy to form " beak " structure.If Fig. 2 is the schematic enlarged-scale view in Fig. 1 in dotted line frame, wherein 105 be emitter part, 107 are
Grid region part, the part that circle of dotted line is drawn are " beak " structure that gate oxide is formed.And grid region end " beak " if structure
It contacts, device threshold voltage can be had an impact with the well region 104 below grid region.
It, usually will by emitter region part to prevent grid region end " beak " structure from being had an impact to device threshold voltage
The grid region of " beak " part keeps apart with well region.However, such method needs the upper surface of emitter region to completely attach to " beak " portion
Cut-off current is caused to bypass path length (such as Fig. 1 and Fig. 3 of emitter region so that the lateral distance of emitter region is big in the grid region divided
In dotted arrow), loss is big, and is easy to cause latch-up.
In view of this, the present invention provides a kind of IGBT device, including：Semiconductor structure, the semiconductor structure include upper
The drift region on surface and the upper surface flush of the semiconductor structure, the well region being located in the upper surface of the drift region, and
Positioned at the well region both sides, and top surface is higher by the emitter region of the upper surface of the semiconductor structure, the bottom surface of the emitter region with
The distance of the upper surface of the semiconductor structure is 0~1 μm；Emitter, the emitter are located at the transmitting of the well region both sides
Between area, the emitter is electrically connected with the emitter region；Grid region, the grid region are located at the emitter both sides, the grid region
With step part and horizontal component, the step part and the horizontal component are structure as a whole, the horizontal part in the grid region
Divide well region and drift region of the covering emitter region backwards to the emitter side, the step part covering at least partly described
The top surface of emitter region.
Since in IGBT device of the present invention, the top surface of the emitter region is higher by the upper surface of the semiconductor structure, to
The end in the grid region of covering emitter region side is raised so that the endpoint of grid region step part is the end in grid region.And grid region platform
The endpoint of exponent part is located at the top surface of the emitter region, can be detached with well region, avoids grid region end " beak " structure to device
The influence of part threshold voltage.Simultaneously as cut-off current surrounds the edge of emitter region, the bottom of the emitter region in the path of well region
Face is 0~1 μm at a distance from the upper surface of the semiconductor structure, so as to shorten cut-off current in the path of well region, is reduced
Loss, and avoid latch-up to the greatest extent.
It is the central idea of the present invention above, following will be combined with the drawings in the embodiments of the present invention, to the embodiment of the present invention
In technical solution be clearly and completely described, it is clear that described embodiments are only a part of the embodiments of the present invention,
Instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative labor
The every other embodiment obtained under the premise of dynamic, shall fall within the protection scope of the present invention.
Embodiment one
The present embodiment provides a kind of IGBT devices, referring to FIG. 4, Fig. 4 is the section of the IGBT device of the embodiment of the present invention
Structural schematic diagram, including：
Semiconductor structure, the semiconductor structure include the drift of upper surface and the upper surface flush of the semiconductor structure
Area 201, the well region 202 being located in the upper surface of the drift region, and it is located at the well region both sides, and top surface is higher by described half
The emitter region 203 of the upper surface of conductor structure；The bottom surface of the emitter region 203 is at a distance from the upper surface of the semiconductor structure
It is 0~1 μm；
Emitter 204, the emitter are located between the emitter region 203 of well region both sides, the emitter and the transmitting
Area is electrically connected；
Grid region, the grid region are located at emitter both sides, and the grid region has step part 206 and horizontal component 207, described
Step part and the horizontal component are structure as a whole, and the horizontal component in the grid region covers the emitter region backwards to the transmitting
The well region of pole side and drift region, the step part cover the top surface of at least partly described emitter region.
Wherein, semiconductor structure can be silicon substrate, or silicon carbide substrates.In the present embodiment, described partly to lead
Body structure is silicon substrate.
There is the second conduction type, the well region 202 to have the first conduction type, the emitter region for the drift region 201
203 have the second conduction type.
First conduction type can be N-type or p-type, and second conduction type can be p-type or N-type, described the
The polarity of one conduction type and the second conduction type is opposite.I.e. when the first conduction type is N-type, second conduction type is
P-type；When the first conduction type is p-type, second conduction type is N-type.In an embodiment of the present invention, the first conductive-type
Type is p-type, and the second conduction type is N-type.Wherein, the N-type ion includes phosphonium ion, arsenic ion, antimony ion etc., the p-type
Ion includes boron ion etc..
In the present embodiment, the drift region 201 is located in the epitaxial layer of semiconductor structure upper surface, the drift region
The upper surface flush of upper surface and the semiconductor structure.
The material of the drift region 201 is the monocrystalline silicon doped with N-type impurity, such as doped with phosphorus；The well region 202
In in the upper surface of drift region, the material of the well region 202 is the monocrystalline silicon doped with p type impurity, such as doped with boron；It is described
203 top surface of emitter region is higher by the upper surface of the semiconductor structure, be located at 202 upper surface of the well region both sides, and with it is described
The upper surface of well region 202 is connected, and the bottom surface of the emitter region is 0~1 μm at a distance from the upper surface of the semiconductor structure, and
And the bottom surface of the emitter region 203 can be higher by 0~1 μm of the upper surface of the semiconductor structure, can also be less than and described partly lead
0~1 μm of the upper surface of body structure, the material of the emitter region 203 are the monocrystalline silicon doped with N-type, such as doped with arsenic, phosphorus.
The emitter 204 is metal electrode, can be formed by sputtering, deposited metal material.The emitter is located at
It between the emitter region of well region both sides, is in direct contact with the emitter region, forms electrical connection.
The grid region is located at emitter both sides, and the grid region has step part 206 and horizontal component 207, the step
Part and the horizontal component are structure as a whole, and the horizontal component in the grid region covers the emitter region backwards to the emitter one
The well region of side and drift region, the step part cover the top surface of at least partly described emitter region.
Wherein, the grid region includes grid and wraps up the gate oxide of the grid, specifically, on the downside of the grid
Gate oxide can be silica, can be generated by thermal oxidation method.The grid can be polysilicon, and the grid can be with
It is formed by the method for deposition.It can be silica to wrap up the gate oxide on the upside of the grid, can be by the grid
Thermal oxidation method is carried out to be formed.
Since in the present embodiment IGBT device, the top surface of the emitter region is higher by the upper surface of the semiconductor structure, from
And the end in the grid region of covering emitter region side is raised so that the endpoint of grid region step part is the end in grid region.And grid region
The endpoint of step part is located at the top surface of the emitter region, so as to be detached with well region, avoids grid region end " beak " knot
Influence of the structure to device threshold voltage.
Simultaneously as cut-off current the path of well region surround emitter region edge, the bottom surface of the emitter region with it is described
The distance of the upper surface of semiconductor structure is 0~1 μm, so as to shorten cut-off current in the path of well region, reduces loss, and
Avoid latch-up to the greatest extent.
In addition, in the prior art, to avoid the uneven influence threshold voltage of the gate oxide thickness of " beak " sharp-tongued part,
The transverse diffusion distance long enough of emitter region is needed, and in order to shorten the path of cut-off current as possible, need the transverse direction of emitter region
Diffusion length is short as possible, and therefore, it is necessary to accurately control the transverse diffusion distance of emitter region so that the technique controlling difficulty of the part
Height, and reduce the design freedom of emitter region.
And in the present embodiment, due to solving above-mentioned contradiction, so that the formation process of the present embodiment device is more
Simply, control difficulty is greatly reduced.
Embodiment two
The present embodiment provides a kind of IGBT devices, referring to FIG. 5, Fig. 5 is the section of the IGBT device of the embodiment of the present invention
Structural schematic diagram.
In the present embodiment, the IGBT device includes：
Semiconductor structure, the semiconductor structure include the drift of upper surface and the upper surface flush of the semiconductor structure
Area 301, the well region 302 being located in the upper surface of the drift region, and it is located at the well region both sides, it is connected with the well region,
And top surface is higher by the emitter region 303 of the upper surface of the semiconductor structure, the bottom surface of the emitter region and the semiconductor structure
Upper surface distance be 0~1 μm；
In the present embodiment, the drift region 301 is the areas N-, and well region 302 is p-well, and emitter region 303 is the areas N+.
Emitter 304, the emitter 304 are located between the emitter region 303 of the well region both sides, the emitter and institute
State emitter region electrical connection；
Grid region positioned at the emitter both sides, the grid region have step part 306 and horizontal component 307, described
Exponent part and the horizontal component are structure as a whole, and the horizontal component in the grid region covers the emitter region backwards to the emitter
The well region of side and drift region, the top surface of the step part covering at least partly emitter region 303.
Further to shorten the cut-off current in the path of well region, in the present embodiment, as shown in fig. 6, by the grid
The side 306 of the step part in area and the angle of the horizontal component 307 in the grid region are 45 °~135 °, to ensure to emit
Further shorten the cut-off current under the premise of the cross-sectional area in area in the path of well region, to reduce loss, utmostly
Avoid latch-up.
In the present embodiment, in the IGBT device, the semiconductor structure further includes the upper table positioned at the drift region
Outer well region 308 in face, the outer well region 308 surround the side and lower surface of the well region；The conduction type of the outer well region
Identical as the conduction type of the drift region, the impurity doping concentration of the outer well region is dense more than the doping of the impurity of the drift region
Degree.
Specifically, as shown in figure 5, the outer well region 308 is N traps, which can be used as carrier accumulation layer, according to
Carrier balance principle, carrier accumulation layer will prevent and store the hole launched from collecting zone P+ substrates, Jin Erxian
Writing reduces on-state voltage drop, also, because VOID POSITIONS is close from emitter, once shutdown, and be pumped quickly, so to shutdown
What speed influence almost without.Therefore, which can be lost lower than traditional IGBT, and on-state voltage drop has been better achieved
With the compromise of turn-off power loss.
In the present embodiment, in the IGBT device, the semiconductor structure further includes the hair positioned at the well region both sides
It penetrates in the well region between area, and the interior well region 309 of upper surface and the well region upper surface flush, the lateral length of the interior well region
More than the lateral length of the emitter；The conduction type of the interior well region is identical as the conduction type of the well region, described interior
The impurity doping concentration of well region is more than the impurity doping concentration of the well region.
Specifically, as shown in figure 5, the interior well region 309 is the areas P+, the doping concentration in the areas P+ is higher than p-well 302, due to P+
The ohmic contact characteristic in area is better than p-well, can form good electrical contact；Also, the conducting resistance ratio P that the areas P+ 309 are adulterated
The conducting resistance of trap doping is small, and pressure drop of the electric current in the areas P+ will be lower when shutdown, so as to so that turn-off power loss is lower and more
Anti- latch-up.
Also, further to shorten the cut-off current in the path of well region, in the present embodiment, between the emitter region
Interior well region be groove structure, the emitter is located in the groove structure.
Specifically, can be performed etching between the emitter region, groove structure, and the shape in the groove structure are formed
At emitter.
It should be noted that during performing etching, to retain well region in a part, to keep its corresponding function.
Cut-off current can be made in trap as shown in dotted arrow in Fig. 5 due to being groove structure between two emitter region
The path in area becomes shorter, to be further reduced loss, and avoids latch-up to the greatest extent.
In the present embodiment, 301 lower section of drift region of the semiconductor structure is disposed with buffering area 310, collecting zone
311 and collector 312.
In the present embodiment, since in IGBT device of the present invention, the top surface of the emitter region is higher by the semiconductor structure
Upper surface, to raised covering emitter region side grid region end so that the endpoint of grid region step part is grid region
End.And the endpoint of grid region step part is located at the top surface of the emitter region, can be detached with well region, avoids grid region end
Influence of " beak " structure to device threshold voltage.
Simultaneously as cut-off current the path of well region surround emitter region edge, the bottom surface of the emitter region with it is described
The distance of the upper surface of semiconductor structure is 0~1 μm, so as to shorten cut-off current in the path of well region, reduces loss, and
Avoid latch-up to the greatest extent.In addition, in the prior art, to avoid the gate oxide thickness of " beak " sharp-tongued part not
Threshold voltage is uniformly influenced, the transverse diffusion distance long enough of emitter region is needed, and in order to shorten the path of cut-off current as possible,
Need the transverse diffusion distance of emitter region short as possible, therefore, it is necessary to the transverse diffusion distances in accurate delivery area so that the part
Technique controlling difficulty is high, and reduces the design freedom of emitter region.And in the present embodiment, due to solving above-mentioned contradiction,
So that the formation process of the present embodiment device is simpler, control difficulty is greatly reduced.
Embodiment three
A kind of forming method of IGBT device is present embodiments provided, as shown in fig. 7, for IGBT device shape in the present embodiment
At the flow chart of method, including：
Step 101：Semiconductor structure is provided, the upper layer of the semiconductor structure is as drift region；
Step 102：Lug boss is formed in the drift region upper surface；
Step 103：Grid region is formed in the lug boss both sides, the grid region has step part and horizontal component, described
Step part and the horizontal component are structure as a whole, and the horizontal component in the grid region covers the drift of the lug boss side
Area, lug boss top surface described in the step part covering part, and the step part of the lug boss both sides is in the lug boss
Top surface is not attached to；
Step 104：First conduction type doping is carried out to the lug boss top surface, forms well region, the transverse direction of the well region
Length is more than the lateral length of the lug boss；
Step 105：Second conduction type doping is carried out to the lug boss top surface, the second conduction type doping is mixed
Miscellaneous depth and the difference in height of the lug boss are -1~1 μm；
Step 106：The part that the lug boss is not covered by the grid region is etched, emitter region is formed；
Step 107：Emitter is formed between the emitter region, the emitter is electrically connected with the emitter region.
Fig. 8~Figure 19 shows the cross-sectional view of the IGBT device of the embodiment of the present invention.
Step 101 is executed, as shown in figure 8, providing semiconductor structure, the semiconductor structure upper layer is as drift region 401.
The semiconductor structure can be silicon substrate, or silicon carbide substrates.In the present embodiment, the semiconductor
Structure is silicon substrate.
Specifically, the semiconductor structure is the silicon substrate with the second conduction type, it is in the present embodiment, described partly to lead
Body structure is the silicon substrate with N-type impurity.Specifically, impurity concentration 5e12~5e15cm of the N-type substrate-3。
Step 102 is executed, lug boss is formed in the drift region upper surface；
Specifically, as shown in figure 9, being performed etching on the drift region, formation lug boss.In this step, the quarter
It is 0.1~3 μm to lose depth.
In the present embodiment, 45 °~135 ° of inclination angle of etching can be set in etching process, and it is in isosceles to make the lug boss
Trapezoidal, the bevel edge of the isosceles trapezoid and the angle [alpha] on bottom edge are 45 °~135 °, to keep the cut-off current path shorter.
Step 103 is executed, grid region is formed in the lug boss both sides, the grid region has step part and horizontal component,
The step part and the horizontal component are structure as a whole, and the horizontal component in the grid region covers the drift of the lug boss side
Area is moved, lug boss top surface described in the step part covering part, and the step part of the lug boss both sides is in the protrusion
Portion top surface is not attached to.
Since the lug boss formed in step 102 is isosceles trapezoid, the bevel edge of the isosceles trapezoid and the angle [alpha] on bottom edge are
45 °~135 °, therefore, the angle of the side of the step part in the grid region being here formed as and the horizontal component is also 45 °~
135°.By the setting, cut-off current is enabled to further to shorten in the path of well region, to reduce loss, utmostly
Avoid latch-up.
Specifically, the step can be divided into following steps：
Step 1031, gate oxide is formed on the semiconductor structure.
Specifically, as shown in Figure 10, carrying out thermal oxidation technology in the semiconductor structure upper surface, forming gate oxide
402, the gate oxide is silica, and thickness is 50nm~150nm.
Step 1032, grid is formed on the gate oxide.
Specifically, as shown in figure 11, polysilicon deposition is carried out on the gate oxide, it is 0.2~2 μm to form thickness
Grid 403.When deposition, the impurity doping concentration for controlling the polysilicon is 1e17~1e21cm-3, the doping type is N-type
Doping, impurity can be phosphorus.
Step 1033, the grid for etching the lug boss top surface is formed in the lug boss top surface and is open.
Specifically, as shown in figure 12, due to forming opening 404 in the lug boss top surface so that the lug boss both sides
The step part in grid region be not attached in the lug boss top surface.
Step 1034, the gate oxide wrapped up on the upside of the grid is formed.
Specifically, carrying out thermal oxide, the gate oxide on the upside of the grid is wrapped up.The gate oxide is silica.
In the present embodiment, as shown in figure 13, grid region 405 is ultimately formed, it can be seen that the grid region 405 is described convex
Portion both sides are played, there is step part and horizontal component, the step part and the horizontal component to be structure as a whole in the grid region,
The horizontal component in the grid region covers the drift region of the lug boss side, lug boss top described in the step part covering part
Face, and the step part of the lug boss both sides is not attached in the lug boss top surface.
Step 104 is executed, the first conduction type doping is carried out to the lug boss top surface, forms well region, the well region
Lateral length is more than the lateral length of the lug boss.
Specifically, carrying out the first conduction type doping to lug boss top layer openings part 404, well region 406 is formed.
Specifically, as shown in figure 14, in the present embodiment, first conduction type is p-type, to the lug boss top layer
Opening portion carries out p type impurity injection, the propulsion of impurity is carried out, to form well region 406, i.e. p-well.
In the present embodiment, the p type impurity is boron, 10~200keV of Implantation Energy, dosage 5e11~1e15cm-2.
When carrying out the propulsion of foreign ion, 800~1200 DEG C of temperature, 50~800min of time are promoted.
In other embodiments of the invention, the principle for considering saving processing step, can walk the propulsion in the application
Suddenly it is merged with step 1034, that is, after executing step 1033, carry out step 104, in the progradation of step 104, lead to
Enter oxygen, forms the gate oxide wrapped up on the upside of the grid.Later, the oxide layer formed opening portion by etching technics
Removal.
Step 105 is executed, the second conduction type doping, the second conduction type doping are carried out to the lug boss top surface
Doping depth be equal to the lug boss height；
Specifically, as shown in figure 15, the second conduction type doping, second conductive-type are carried out to the lug boss top surface
The doping depth of type doping is equal to the height of the lug boss.
In the present embodiment, second conduction type is doped to n-type doping, injects phospha to the lug boss top surface
Matter, 10~200keV of Implantation Energy, dosage 1e12~5e16cm-2.Later, impurity propulsion is carried out, temperature 800~1200 is promoted
DEG C, 10~100min of time.
Step 106 is executed, the part that the lug boss is not covered by the grid region is etched, forms emitter region.
Specifically, as shown in figure 16, in this step, etching the part that the lug boss is not covered by the grid region, shape
At emitter region 407.
Wherein, the etching depth of the etching is more than or equal to the height of the lug boss.In the present embodiment, the etching
Depth is more than the height of the lug boss so that the emitter bottom surface subsequently formed between the emitter region is less than the well region
Upper surface so that cut-off current reach emitter path it is shorter.
After executing step 106, in the present embodiment, can also include：
Step 200：First conduction type doping is carried out to the lug boss top surface, forms interior well region, the interior well region
Lateral length is more than the lateral length of emitter, is less than the lateral length of the lug boss.
Specifically, as shown in figure 17, first conduction type is p-type, and implanted dopant can be boron.Implantation Energy 10~
200keV, dosage 1e12~5e16cm-2.Promote 800~1200 DEG C of temperature, 50~800min of time.
P-type doping is carried out in interior well region, forms the interior well region that impurity doping concentration is more than the impurity doping concentration of well region
The lateral length of 408, the i.e. areas P+, the interior well region is more than the open-topped lateral length of the lug boss, is less than the lug boss
Lateral length.Since the ohmic contact characteristic in the areas P+ is better than well region 406 (p-well), good electrical contact can be formed；And
And the conducting resistance that the areas P+ 408 are adulterated is smaller than the conducting resistance that p-well is adulterated, pressure drop of the electric current in the areas P+ will be lower when shutdown,
So as to so that turn-off power loss is lower and more anti-latch-up.
Step 107 is executed, forms emitter between the emitter region, the emitter is electrically connected with the emitter region.
Specifically, as shown in figure 18, emitter is formed on the well region between the emitter region, by depositing operation,
It is described to penetrate deposited metal on the well region between area, to form emitter 409.
It should be noted that should also include forming buffering area 410, collecting zone as shown in figure 19 in the present embodiment
411 and collector 412 process, which can be specific as follows：
Step 108, the doping of the second conduction type is carried out to semiconductor lower surface, forms buffering area 410.
Specifically, carrying out n-type doping in semiconductor lower surface, implanted dopant is phosphorus.10~200keV of Implantation Energy, dosage
1e12~5e16cm-2, promote 800~1200 DEG C of temperature, 50~800min of time.
Step 109, the doping of the first conduction type is carried out to semiconductor lower surface, forms collecting zone 411.
Specifically, carrying out p-type doping in semiconductor lower surface, implanted dopant is boron, 10~200keV of Implantation Energy, dosage
1e12~5e16cm-2, promote 800~1200 DEG C of temperature, 50~800min of time.
Step 110, metal deposit is carried out to semiconductor lower surface, forms collector 412.
Consider that the principle of saving processing step, this step can merge with step 107.Specifically, needing to execute step
When 107, this step is skipped, until when this step, metal deposit is carried out, forms emitter and collector.
In addition, in other embodiments of the invention, the method can also be after step 102 or step 1033, half-and-half
The upper surface of conductor structure carries out the doping of the second conduction type, outer well region is formed, specifically, passing through ion in the present embodiment
Injection forms the N traps injection region of N-type impurity, to further promote the electric property of device.
Wherein, outer well region 501st area as shown in figure 20 that step 102 is formed, the outer well region such as Figure 21 formed after step 1033
Shown 601st area.
By increasing by one layer of outer well region in well region and the drift regions N-, it can be used as carrier accumulation layer, according to carrier
Equilibrium principle, which will prevent and stores the hole launched from collecting zone P+ substrates, and then significantly drop
Low on-state voltage drop, also, because VOID POSITIONS is close from emitter, once shutdown, and be pumped quickly, so to turn-off speed
What influenced almost without.Therefore, which can be lost lower than traditional IGBT, and on-state voltage drop and pass has been better achieved
The compromise of breakdown consumption.
Since in the present embodiment IGBT device, the top surface of the emitter region is higher by the upper surface of the semiconductor structure, from
And the end in the grid region of covering emitter region side is raised so that the endpoint of grid region step part is the end in grid region.And grid region
The endpoint of step part is located at the top surface of the emitter region, so as to be detached with well region, avoids grid region end " beak " knot
Influence of the structure to device threshold voltage.Simultaneously as cut-off current surrounds the edge of emitter region, the hair in the path of well region position
The bottom surface for penetrating area is 0~1 μm at a distance from the upper surface of the semiconductor structure, so as to shorten cut-off current on the road of well region
Diameter reduces loss, and avoids latch-up to the greatest extent.
Also, in the present embodiment, lug boss top surface carry out well region propulsion, compared with manufacture craft compare,
Under same impurity implantation dosage, the p type impurity doping concentration below the grid oxygen in the present embodiment is by slightly higher (because impurity is not required to
Be diffused into the region for carving the silicon fallen), therefore to ensure same threshold voltage, need to reduce p-well implantation dosage, to formed compared with
Short well region diffusion length.What well region diffusion length shortened can make conducting channel shorten, and to reduce channel resistance, reduction is led
Logical pressure drop, makes conduction loss reduce.
It should be noted that each embodiment in this specification is described in a progressive manner, each embodiment weight
Point explanation is all difference from other examples, and the same or similar parts between the embodiments can be referred to each other.
For device class embodiment, since it is basically similar to the method embodiment, so fairly simple, the related place ginseng of description
See the part explanation of embodiment of the method.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only that
A little elements, but also include other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
For convenience of description, it is divided into various units when description apparatus above with function to describe respectively.Certainly, implementing this
The function of each unit is realized can in the same or multiple software and or hardware when invention.
Technical solution provided herein is described in detail above, specific case used herein is to this Shen
Principle and embodiment please is expounded, the explanation of above example is only intended to help understand the present processes and its
Core concept；Meanwhile for those of ordinary skill in the art, according to the thought of the application, in specific implementation mode and application
There will be changes in range, in conclusion the contents of this specification should not be construed as limiting the present application.
Claims (14)
1. a kind of IGBT device, which is characterized in that including：
Semiconductor structure, the semiconductor structure include the drift region of upper surface and the upper surface flush of the semiconductor structure,
Well region in the upper surface of the drift region, and it is located at the well region both sides, and top surface is higher by the semiconductor structure
Upper surface emitter region, the bottom surface of the emitter region at a distance from the upper surface of the semiconductor structure be 0~1 μm；
Emitter, the emitter are located between the emitter region of the well region both sides, and the emitter is electrically connected with the emitter region
It connects；
Grid region, the grid region are located at the emitter both sides, and the grid region has step part and horizontal component, the stage portion
Divide and the horizontal component is structure as a whole, the horizontal component in the grid region covers the emitter region backwards to the emitter side
Well region and drift region, the step part cover the top surface of at least partly described emitter region.
2. device according to claim 1, which is characterized in that the side of the step part in the grid region and the grid region
The angle of horizontal component is 45 °~135 °.
3. device according to claim 2, which is characterized in that the semiconductor structure further includes being located at the drift region
Outer well region in upper surface, the outer well region surround the side and lower surface of the well region；
The conduction type of the outer well region is identical as the conduction type of the drift region, and the impurity doping concentration of the outer well region is big
Impurity doping concentration in the drift region.
4. device according to claim 2, which is characterized in that the semiconductor structure further includes being located at the well region both sides
Emitter region between well region in, the transverse direction of the and interior well region of upper surface and the well region upper surface flush, the interior well region is long
Lateral length of the degree more than the emitter；
The conduction type of the interior well region is identical as the conduction type of the well region, and the impurity doping concentration of the interior well region is more than
The impurity doping concentration of the well region.
5. device according to claim 4, which is characterized in that the interior well region between the emitter region has groove structure,
The emitter is located in the groove structure.
6. a kind of forming method of IGBT device, which is characterized in that including：
Semiconductor structure is provided, the upper layer of the semiconductor structure is drift region；
Lug boss is formed in the drift region upper surface；
Grid region is formed in the lug boss both sides, the grid region has step part and horizontal component, the step part and institute
It states horizontal component to be structure as a whole, the horizontal component in the grid region covers the drift region of the lug boss side, the stage portion
Divide lug boss top surface described in covering part, and the step part of the lug boss both sides is not attached in the lug boss top surface；
First conduction type doping is carried out to the lug boss top surface, forms well region, the lateral length of the well region is more than described
The lateral length of lug boss；
Second conduction type doping carried out to the lug boss top surface, the doping depth of second conduction type doping with it is described
The difference in height of lug boss is -1~1 μm；
The part that the lug boss is not covered by the grid region is etched, emitter region is formed；
Emitter is formed between the emitter region, the emitter is electrically connected with the emitter region.
7. according to the method described in claim 6, it is characterized in that, the cross section of the lug boss is isosceles trapezoid.
8. the method according to the description of claim 7 is characterized in that the bevel edge of the isosceles trapezoid and the angle on bottom edge are 45 °
~135 °.
9. according to the method described in claim 8, it is characterized in that, after the formation lug boss, is formed before grid region, also wrapped
It includes：
The doping of the second conduction type is carried out to the upper surface of the semiconductor structure, forms outer well region, the cross of the outer well region
It is more than the lateral length of the well region to length.
10. according to the method described in claim 8, it is characterized in that, after the formation grid region, is formed before well region, also wrapped
It includes：
Second conduction type doping is carried out to the lug boss top surface, forms outer well region, the lateral length of outer well region is more than described
The lateral length of well region.
11. according to the method described in claim 8, it is characterized in that, after the formation emitter region, formed before emitter,
Further include：
First conduction type doping is carried out to the lug boss top surface, forms interior well region, the lateral length of the interior well region is more than
The lateral length of the emitter is less than the lateral length of the lug boss.
12. according to the method described in claim 8, it is characterized in that, the etching depth of the etching lug boss is more than etc.
In the height of the lug boss, be less than the height of the lug boss and the doping depth of the well region and.
13. according to the method for claim 11, which is characterized in that the etching depth of the etching lug boss is more than institute
State the height of lug boss, be less than the doping depth of height and the interior well region of the lug boss and.
14. according to the method described in claim 6, it is characterized in that, described form lug boss, packet in the drift region upper surface
It includes：
The upper surface for etching the drift region forms lug boss in the drift region upper surface.
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| CN102184862A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Method for etching grid groove of groove power device |
| CN102938416A (en) * | 2011-08-16 | 2013-02-20 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN103632939A (en) * | 2012-08-15 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Method for optimizing top rounded corner of power device groove |
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| CN102184862A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Method for etching grid groove of groove power device |
| CN102938416A (en) * | 2011-08-16 | 2013-02-20 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN103632939A (en) * | 2012-08-15 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Method for optimizing top rounded corner of power device groove |
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