CN106129110A - A kind of dual pathways RC IGBT device and preparation method thereof - Google Patents
A kind of dual pathways RC IGBT device and preparation method thereof Download PDFInfo
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Abstract
A kind of dual pathways RC IGBT device and preparation method thereof.The invention belongs to power semiconductor device technology field, a kind of dual pathways of concrete offer is against conductivity type insulated gate bipolar transistor (RC IGBT) and preparation method thereof, for optimizing the forward IGBT characteristic of tradition RC IGBT, improve backward diode characteristic simultaneously, improve the reliability of device；The present invention has twin-channel unilateal conduction path by being formed at the device back side, completely eliminates snapback phenomenon, and have the conduction voltage drop identical with tradition IGBT under forward IGBT mode of operation；Under backward diode afterflow mode of operation, there is little conduction voltage drop；Simultaneously because need not increase back P+ collector width can use little back side cellular width, overcome tradition RC IGBT device electric current and the problem of temperature homogeneity, substantially increase reliability, and its preparation technology is mutually compatible with tradition RC IGBT device technique.
Description
Technical field
The invention belongs to power semiconductor device technology field, relate to insulated gate bipolar transistor (IGBT), specifically relate to
And against conductivity type insulated gate bipolar transistor (RC-IGBT) and preparation method thereof.
Background technology
Insulated gate bipolar transistor (IGBT) is the novel electric power electricity that a kind of MOS field effect and bipolar transistor are compound
Sub-device；Its existing MOSFET is prone to drive, and controls simple advantage, has again power transistor turns pressure drop low, on state current
Greatly, little advantage is lost, it has also become one of core electron components and parts in modern power electronic circuit, is widely used in such as
The every field of the national economy such as communication, the energy, traffic, industry, medical science, household electrical appliance and Aero-Space.The application of IGBT is right
The lifting of power electronic system performance serves particularly important effect.
In power electronic system, IGBT typically requires collocation fly-wheel diode (Free Wheeling Diode, FWD)
It is used to ensure that the safety and stability of system；Therefore in tradition IGBT module or single tube device, it will usually have FWD with it the most also
Connection, the program not only increases the number of device, the volume of module and production cost, and the increase of solder joint number in encapsulation process
Can affect the reliability of device, ghost effect produced by metal connecting line has an effect on the overall performance of device.
In order to solve this problem, it is achieved the integration of product, document " Takahash, H；Yamamoto,A；Aono,S；
Mi nato,T.1200V Reverse Conducting IGBT.Proceedings of 2004International
Symposium on Power Semiconductor Devices&ICs, 2004, pp.24-27 " propose inverse conductivity type IGBT
(Reverse Cond ucting IGBT, RC-IGBT), is successfully integrated in inside IGBT by fly-wheel diode, and its structure is such as
Shown in Fig. 1.Compared to tradition without the IGBT of afterflow ability, this structure made at its back and metal collector 10 and N-type electric
The N-type collecting zone 11 that field stop layer 8 connects, this region defines parasitic diode with drift region 7, p-type base in device 4 and N-
Structure, under freewheeling mode, the conducting of this parasitic diode provides current path；But the introducing of this structure back N-type collecting zone 11
Cause adverse effect also to the forward conduction characteristic of device.As seen from Figure 1, surface channel district in device architecture, N-drift region 7
Parasitic VDMOS structure is defined, when forward conduction, under the conditions of small area analysis, due to pressure drop not with back N-type collecting zone 11
Foot, the PN junction that back p-type collecting zone 9 is formed with N-type electric field trapping layer 8 cannot be opened, from the electronics of Channeling implantation N-drift region 7
Directly flow out from N-type collecting zone 11, cause device to present VDMOS characteristic；Along with the increase of electric current, only increase to when electric current
After to a certain degree making the pressure drop between p-type collecting zone 9 and N-type electric field trapping layer 8 be higher than PN junction cut-in voltage, p-type collecting zone 9
Just can inject hole in N-type electric field trapping layer 8 and N-drift region 7, form conductivity modulation effect, now due to N-drift region 7
In conductivity modulation effect, the forward voltage drop of device can decline rapidly so that Device current-voltage curve presents and turns back
(Snapback) phenomenon；Snapback phenomenon becomes apparent under cryogenic, and this can cause the device cannot be normally-open, seriously
Affect the stability of power electronic system.For traditional RC-IGBT, the suppression of Snapback phenomenon is multiple MOS in front
By increasing the width increase back side cellular width of back P+ collecting zone in the case of cellular parallel connection, thus it is horizontal to increase electronic current
To the path of flowing, increase the resistance on current path so that it is under less electric current, so that it may so that back is away from N-type current collection
The pressure drop that the p-type collecting zone in district 11 and N-type electric field trapping layer 8 are formed reaches the cut-in voltage of PN junction.But, this method has
Problems with: 1) forward IGBT conducting time: owing to the existence of parasitic VDMOS is difficult to be completely eliminated Snapback phenomenon, N-type current collection
The existence in district 11 makes the conduction voltage drop of the tradition RC-IGBT conduction voltage drop more than tradition IGBT, and the P+ collecting zone that increases
Width can cause the device current flow uniformity problem when forward IGBT turns on, and causes serious current convergence and temperature uneven
Even, have a strong impact on the reliability of RC-IGBT device；2) during backward diode afterflow conducting: the P+ collector width of increase increases
P-type collecting zone 9, to injecting the extraction in hole in N-drift region 7, increases the path of electric current simultaneously, adds leading of diode
Lead to pressure drop, and the width of the P+ collecting zone increased can cause the device current flow uniformity problem when backward diode afterflow,
Cause serious current convergence and non-uniform temperature, have a strong impact on the reliability of RC-IGBT device.
Summary of the invention
It is an object of the invention to provide a kind of dual pathways RC-IGBT device and preparation method thereof, be used for optimizing tradition RC-
The forward IGBT characteristic of IGB T, improves backward diode characteristic simultaneously, improves the reliability of device；Dual pathways RC-of the present invention
IGB T device has twin-channel unilateal conduction path by being formed at the device back side, under forward IGBT mode of operation completely
Eliminate snapback phenomenon, and there is the conduction voltage drop identical with tradition IGBT；Under backward diode afterflow mode of operation
There is little conduction voltage drop；Simultaneously because need not increase back P+ collector width can use little back side cellular width, gram
Take traditional RC-IGBT device current and the problem of temperature homogeneity, substantially increased reliability, and its preparation technology is with traditional
RC-I GBT device technology is mutually compatible.
For achieving the above object, the present invention uses the technical scheme to be:
A kind of dual pathways RC-IGBT device, its structure cell is as in figure 2 it is shown, include emitter structure, grid structure, collection
Electrode structure and drift region structure, described emitter structure includes metal emitting 1, P+ ohmic contact regions 2, N+ launch site 3 and P
Type base 4, wherein launch site 3, P+ ohmic contact regions 2 and N+ is separate is arranged in p-type base 4, and P+ ohmic contact regions 2
All contact with metal emitting 1 with the surface of N+ launch site 3；Described drift region structure includes N-drift region 7 and the resistance of N-type electric field
Only layer 8, described N-type electric field trapping layer 8 is arranged at the back side, N-drift region 7；Described grid structure includes gate electrode 6 and gate oxide
5, between described gate electrode 6 and N+ launch site 3, p-type base 4 and N-drift region 7 three, gate oxide 5 is set；Described drift region
Structure between described emitter structure/grid structure and described collector structure, described front, N-drift region 7 and emitter stage
The p-type base 4 of structure and the gate oxide 5 of grid structure contact；
It is characterized in that, described collector structure includes p-type collecting zone 9, metal collector 10, N-type collecting zone 11, first
Dielectric layer 12, metal ohmic contact 13, Schottky contact metal 14 and second dielectric layer 15；Described p-type collecting zone 9 and N-type electricity
Field stop layer 8 back face touches, and described N-type collecting zone 11 is positioned at p-type collecting zone 9, and described metal collector 10 is arranged at p-type
Collecting zone 9 back side and with N-type collecting zone 11 part contact, described second dielectric layer 15 is arranged side by side with metal collector 10, institute
State metal ohmic contact 13 and Schottky contact metal 14 is arranged side by side in second dielectric layer 15 and Schottky contact metal 14
And metal collector 10 is spaced second dielectric layer 15, described metal ohmic contact 13 is connected with N-type electric field trapping layer 8 and forms Europe
Nurse contacts, and described Schottky contact metal 14 is connected with N-type collecting zone 11 and forms Schottky contacts, metal ohmic contact 13 He
First medium layer 12 is set between Schottky contact metal 14 and p-type collecting zone 9, and metal ohmic contact 13 and Schottky contacts
Metal 14 is in first medium layer 12 back side phase short circuit.
Further, described grid structure is planar gate structure or slot grid structure；Described drift region structure be NPT structure or
FS structure；The semi-conducting material of described RC-IGBT device uses Si, SiC, GaAs or GaN to make；Described first medium layer
Dielectric material is SiO2、HfO2、Al2O3、Si3N4Contour k dielectric material.
The preparation method of above-mentioned dual pathways RC-IGBT, comprises the following steps:
The first step: choose N-drift region FZ silicon chip being lightly doped in order to form RC-IGBT；By repeatedly photoetching, oxidation, from
Son injection, annealing, depositing technics make the Facad structure of RC-IGBT at front side of silicon wafer, including emitter structure and grid structure；
Second step: upset silicon chip, thinning silicon chip back side is to desired thickness；
3rd step: the predeterminable area at silicon chip back side passes through ion implanting N-type impurity the N-type of the making RC-IGBT that anneals
Field stop layer, the thickness of the N-type field stop layer of formation is 2～5 microns；
4th step: photoetching, the predeterminable area at silicon chip back side passes through ion implanting p type impurity and makes the p-type collection of RC-IGBT
Electricity district, the thickness of the p-type collecting zone of formation is 0.5～1 micron；
5th step: photoetching, the predeterminable area at silicon chip back side passes through ion implanting N-type impurity the making RC-IGBT that anneals
N-type collecting zone, the thickness of the N-type collecting zone of formation is less than the thickness of p-type collecting zone 0.1～0.3 micron；
6th step: oxidation or dielectric layer deposited, photoetching etch media form first medium layer, the thickness of first medium layer
Less than 0.1 micron；
7th step: deposit photoetching, etching metal formation metal ohmic contact and Schottky contact metal；
8th step: deposit photoetching, etch media layer formation second dielectric layer；
9th step: deposit photoetching, etching metal formation metal collector；
I.e. it is prepared into dual pathways RC-IGBT.
Further, in described processing step the preparation of the 3rd step N-type field stop layer can at the Facad structure of RC-IGBT,
Carry out including before the preparation of cellular MOS structure and terminal structure；Or can directly select there is N-type field stop layer and N-drift region
Two-layer epitaxial material as the initial silicon sheet material of technique, the i.e. the 3rd step can be omitted.
It should be noted that in order to simplify description, above-mentioned device architecture and preparation method are with n-channel RC-IGBT device
As a example by illustrate, but present disclosure applies equally to the preparation of p-channel RC-IGBT device；And in the preparation method of above-mentioned RC-IGBT
Processing step and process conditions can be set according to actual needs.
The dual pathways RC-IGBT device that the present invention provides, when IGBT forward bias, emitter metal 1 connecting to neutral current potential, collection
Electrode metal 10 connects high potential, and gate electrode 6 connects high potential.The Schottky that N-type collecting zone 11 is formed with schottky metal 14
Knot, owing to metal collector 10 connects high potential, forms the barrier layer of carrier in N-type collecting zone 11, and this schottky junction is reverse-biased,
Electric current can not be circulated by this schottky junction, therefore metal collector 10, N-type collecting zone 11, schottky metal 14, Ohmic contact
The path current of metal 13 and N-type field stop layer 8 can not turn on；Additionally, due to N-type collecting zone 11 is wrapped up by P collector region 9, and
And P collector region 9 and N-type collecting zone 11 isoelectric level, therefore when IGBT forward bias, N-type collecting zone 11 is shielded completely by P collector region 9
Cover.When gate electrode 6 connects high potential, device surface MOS raceway groove is opened, electronics by N+ launch site 3 through the surface ditch in P-body district 4
Road injects in N-drift region 7, along with the increase of collector electrode metal 10 voltage, when the pressure drop of P collector region 9 and N-type field stop layer 8 surpasses
After crossing the conduction voltage drop of PN junction, surface MOS raceway groove flow into electronic current in N-drift region 7 and drift about as by P-body district 4, N-
District 7 and the base current of the PNP transistor of P collector region 9 composition, make PNP transistor turn on, a large amount of holes by P collector region 9 through N
Type electric field trapping layer 8 injects in N-drift region 7.Therefore, present configuration is not only completely eliminated to tradition RC-IGBT just
Snapback phenomenon when conducting, and there is the forward conduction voltage drop identical with tradition IGBT, without the need for increasing the back of the body
The width of portion's P collector region 9 can use little back side cellular width, solves tradition RC-IGBT device current and temperature homogeneity
Problem, substantially increase reliability.
For present configuration under diode continuousing flow pattern, the negative electrode (emitter stage) of device is high potential, anode (current collection
Pole) be zero potential, its equivalent circuit as it is shown on figure 3, the path of diode current will be made up of two kinds of conductive channels at back, as
Shown in Fig. 4.First, N-type field stop layer 8, P collector region 9, N-type collecting zone 11, first medium layer 12 and metal ohmic contact 13 and
Schottky metal 14 constitutes the parasitic MOSFET structure of gate-drain short circuit, and for this parasitism MOSFET, P collector region 9 is substrate, N
Type field stop layer 8 is drain region, and N-type collecting zone 11 is source region, and first medium layer 12 is gate medium, metal ohmic contact 13 and Xiao Te
Base Metal 14 is grid.By adjusting the thickness of first medium layer 12 and material and the concentration of P collector region 9 and width, make this
Parasitic MOSFET has the threshold voltage between 0～0.1V.Post described in exceeding when the potential difference of device cathodes of the present invention and anode
After the cut-in voltage sum of the threshold voltage giving birth to MOSFET and the P N formed by drift region 7, P-body district 4 and N-knot, now
The above-mentioned PN junction formed by drift region 7, P-body district 4 and N-is opened and parasitic M OS raceway groove is opened, and device enters diode and continues
Stream conduction mode, electric current flows into from surface PN junction and flows out device from back parasitic MOS channel；When negative electrode and the potential difference of anode
Continue to increase, when the potential difference of negative electrode and anode exceedes Schottky contact metal 14 and the schottky junction of N-type collecting zone 11 formation
Cut-in voltage and the cut-in voltage sum of PN junction that formed by drift region 7, P-body district 4 and N-after, back is except parasitic MOS
Outside raceway groove is opened, schottky metal 14 and N-type collecting zone 11 schottky junction formed also is opened, and now one part of current is at the back of the body
Portion is by by N-drift region 7, N-type field stop layer 8, metal ohmic contact 13, Schottky contact metal 14, N-type collecting zone 11
Current path flows out, back be the conducting of double conductive channel, i.e. electric current after the inflow of surface PN junction from back parasitic MOS channel and Xiao
Special base junction two passes flows out device.By selecting suitable schottky metal 14, the Xiao Te that available～0.3V is even lower
Base cut-in voltage.Therefore, under the mode of operation of fly-wheel diode, the present invention has two conductive paths in device back, has
Lower conduction voltage drop, more excellent diode current flow characteristic.Especially, under forward IGBT conduction mode, back is parasitic
MOSFET can not turn on, and now schottky junction is also reverse-biased cut-off state, therefore is used for continuing under forward IGBT conduction mode
Two paths at the back of stream diode are all to block.
In sum, the dual pathways RC-IGBT device that the present invention provides completely eliminates under forward IGBT mode of operation
Sna pback phenomenon, and there is the conduction voltage drop identical with tradition IGBT；Due to the back of the body under backward diode afterflow mode of operation
The existence of the double conductive channel in portion has little conduction voltage drop；Can use little simultaneously because need not increase back P collector region width
Back side cellular width, solve tradition RC-IGBT device current and the problem of temperature homogeneity, substantially increase reliability；
And the preparation method that the present invention provides is mutually compatible with tradition RC-IGBT device technology.
Accompanying drawing explanation
Fig. 1 is traditional RC-IGBT device cellular structural representation.
Fig. 2 is the dual pathways RC-IGBT device cellular structural representation that the present invention provides.
In Fig. 1 to Fig. 2,1 is metal emitting, and 2 is P+ ohmic contact regions, and 3 is N+ launch site, and 4 is p-type base, and 5 is grid
Oxide layer, 6 is polysilicon gate, and 7 is N-drift region, and 8 is N-type electric field trapping layer, and 9 is p-type collecting zone, and 10 is metal current collection
Pole, 11 is N-type collecting zone, and 12 is first medium layer, and 13 is metal ohmic contact, and 14 is Schottky contact metal, and 15 is second
Dielectric layer.
Fig. 3 is operated in equivalent circuit mould during diode continuousing flow pattern for the dual pathways RC-IGBT device that the present invention provides
Type.
Fig. 4 is operated in dual pathways conduction during diode continuousing flow pattern for the dual pathways RC-IGBT device that the present invention provides
Pattern diagram.
The manufacturing process flow schematic diagram of the dual pathways RC-IGBT device that Fig. 5 provides for the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, principle and characteristic to the present invention are described further, and example is served only for explaining this
Invention, is not intended to limit the scope of the present invention.
The present embodiment provides the dual pathways RC-IGBT device of 600V electric pressure, and its structure cell is as in figure 2 it is shown, include
Emitter structure, collector structure, grid structure and drift region structure；Described emitter structure includes metal emitting 1, P+ Europe
Nurse contact area 2, N+ launch site 3 and p-type base 4, wherein launch site 3, P+ ohmic contact regions 2 and N+ is positioned at p-type base independently of each other
In district 4, and the surface of launch site 3, P+ ohmic contact regions 2 and N+ all contacts with metal emitting 1；Described drift region structure bag
Including N-drift region 7 and N-type electric field trapping layer 8, described N-type electric field trapping layer 8 is arranged at the back side, N-drift region 7；Described grid is tied
Structure includes gate electrode 6 and gate oxide 5, gate electrode 6 and N+ launch site 3, the drift region 7, p-type base 4 and N-of described grid structure
Across gate oxide 5 between three；Described drift region structure is positioned at described emitter structure/grid structure and described collector junction
Between structure, front, described N-drift region 7 contacts with the p-type base 4 of emitter structure and the gate oxide 5 of grid structure；
It is characterized in that, described collector structure includes p-type collecting zone 9, metal collector 10, N-type collecting zone 11, first
Dielectric layer 12, metal ohmic contact 13, Schottky contact metal 14 and second dielectric layer 15；Described p-type collecting zone 9 and N-type electricity
Field stop layer 8 back face touches, and described N-type collecting zone 11 is positioned at p-type collecting zone 9 and is positioned at the bottom of p-type collecting zone 9, institute
Stating p-type collecting zone 9 thickness is 0.5～1 micron, and described N-type collecting zone 11 thickness is more micro-than p-type collecting zone 9 thickness little 0.1～0.3
Rice；Described metal collector 10 be arranged at p-type collecting zone 9 back side and with N-type collecting zone 11 part contact, described second medium
Layer 15 is arranged side by side with metal collector 10, and described metal ohmic contact 13 and Schottky contact metal 14 are arranged side by side in second
In dielectric layer 15 and Schottky contact metal 14 and metal collector 10 are spaced second dielectric layer 15, described metal ohmic contact
13 are connected with N-type electric field trapping layer 8 and form Ohmic contact, and described Schottky contact metal 14 is connected also with N-type collecting zone 11
Form Schottky contacts, first medium layer is set between metal ohmic contact 13 and Schottky contact metal 14 and p-type collecting zone 9
12, and metal ohmic contact 13 with Schottky contact metal 14 in first medium layer 12 back side phase short circuit；Described first medium layer
12 thickness are less than 0.1 micron；Hinder with N-type electric field by adjusting the thickness of first medium layer 12 and material and N-type collecting zone 11
Stop concentration and the width of P collector region 9 between layer 8, make back parasitism MOSFET have the threshold voltage between 0～0.1V；Pass through
Select suitable schottky metal 14, make the schottky junction of formation have the even lower cut-in voltage of 0.3V.
The preparation method of dual pathways RC-IGBT of above-mentioned 600V electric pressure, as it is shown in figure 5, specifically include following steps:
The first step: choosing doping content is 2 × 1014Individual/cm3, thickness is that the FZ silicon chip that is lightly doped of 300～500 microns is used
To form the N-drift region of RC-IGBT；By repeatedly photoetching, oxidation, ion implanting, annealing, depositing technics in front side of silicon wafer system
Make the Facad structure of RC-IGBT, including emitter structure and grid structure；
Second step: upset silicon chip, the thickness of thinning silicon chip back side to 40～60 micron；
3rd step: at silicon chip back side by ion implanting N-type impurity the N-type field stop layer 8 of the making RC-IGBT that anneals,
The thickness of the N-type field stop layer formed is 2～3 microns, and ion implantation energy is 1000keV～2000keV, and implantation dosage is 1
×1014Individual/cm2, using laser annealing technique, annealing temperature is 400-500 DEG C, and annealing time is 30～60 minutes；
4th step: photoetching, in the subregion of silicon chip back side, the p-type by ion implanting p type impurity making RC-IGBT is saturating
Bright collecting zone, the thickness of the p-type collecting zone 9 of formation is 0.5 micron, and ion implantation energy is 60keV, and implantation dosage is 1 × 1014
Individual/cm2；
5th step: photoetching, in the subregion of silicon chip back side by ion implanting N-type impurity the making RC-IGBT that anneals
N-type collecting zone 11, the thickness of the N-type collecting zone 11 of formation is less than the thickness of p-type collecting zone 9 0.2 micron, N-type collecting zone 11
And the width of P collector region 9 is 0.2 micron between N-type electric field trapping layer 8, ion implantation energy is 15keV, implantation dosage is 2 ×
1014Individual/cm2, annealing temperature is 450 DEG C, and annealing time is 30～60 minutes；
6th step: oxidation or dielectric layer deposited, photoetching etch media form first medium layer 12, first medium layer 12
Thickness is 0.05 micron, and the width of dielectric layer 12 is 0.3 micron, and dielectric layer 12 stops with N-type electric field at described N-type collecting zone 11
Between layer 8 P collector region 9 surface and beyond the N-type collecting zone 11 extending to both sides of partial symmetry and N-type electric field trapping layer
The surface of 8；
7th step: deposit photoetching, etching metal Al are at the surface of N-type electric field trapping layer 8 and first medium layer 12
Left part surface forms metal ohmic contact 13, described metal ohmic contact 13 and the formation Europe, surface of N-type electric field trapping layer 8
Nurse contacts；Deposit photoetching, etching W metal at N-type collecting zone 11 near the part surface of first medium layer 12 and dielectric layer
The right part surface of 12 forms Schottky contact metal 14, described Schottky contact metal 14 and the surface of N-type collecting zone 11
Form Schottky contacts；And described metal ohmic contact 13 and Schottky contact metal 14 are in the surface phase of first medium layer 12
Short circuit；
8th step: deposit photoetching, etch media layer formation second dielectric layer 15；
9th step: deposit photoetching, etching metal, forms metal collector 10；
I.e. it is prepared into dual pathways RC-IGBT.
The above, the only detailed description of the invention of the present invention, any feature disclosed in this specification, unless especially
Narration, all can be by other equivalences or have the alternative features of similar purpose and replaced；Disclosed all features or all sides
Method or during step, in addition to mutually exclusive feature and/or step, all can be combined in any way.
Claims (6)
1. a dual pathways RC-IGBT device, its structure cell includes emitter structure, grid structure, collector structure and drift
Moving plot structure, described emitter structure includes metal emitting (1), P+ ohmic contact regions (2), N+ launch site (3) and p-type base
(4), wherein P+ ohmic contact regions (2) and N+ launch site (3) are separate is arranged in p-type base (4), and P+ ohmic contact regions
(2) all contact with metal emitting (1) with the surface of N+ launch site (3)；Described drift region structure include N-drift region (7) and
N-type electric field trapping layer (8), described N-type electric field trapping layer (8) is arranged at N-drift region (7) back side；Described grid structure includes grid
Electrode (6) and gate oxide (5), described gate electrode (6) and N+ launch site (3), p-type base (4) and N-drift region (7) three it
Between gate oxide (5) is set；Described drift region structure be positioned at described emitter structure/grid structure and described collector structure it
Between, described N-drift region (7) front contacts with the p-type base (4) of emitter structure and the gate oxide (5) of grid structure；
It is characterized in that, described collector structure include p-type collecting zone (9), metal collector (10), N-type collecting zone (11),
One dielectric layer (12), metal ohmic contact (13), Schottky contact metal (14) and second dielectric layer (15)；Described p-type current collection
District (9) touches with N-type electric field trapping layer (8) back face, and described N-type collecting zone (11) is positioned at p-type collecting zone (9), described gold
Belong to colelctor electrode (10) be arranged at p-type collecting zone (9) back side and with N-type collecting zone (11) part contact, described second dielectric layer
(15) being arranged side by side with metal collector (10), described metal ohmic contact (13) and Schottky contact metal (14) are arranged side by side
In second dielectric layer (15) and Schottky contact metal (14) and metal collector (10) interval second dielectric layer (15), institute
State metal ohmic contact (13) be connected with N-type electric field trapping layer (8) and form Ohmic contact, described Schottky contact metal (14)
It is connected with N-type collecting zone (11) and forms Schottky contacts, metal ohmic contact (13) and Schottky contact metal (14) and p-type
First medium layer (12) is set between collecting zone (9), and metal ohmic contact (13) and Schottky contact metal (14) are in first
Dielectric layer (12) back side phase short circuit.
2. dual pathways RC-IGBT device as described in claim 1, it is characterised in that described grid structure be planar gate structure or
Slot grid structure.
3. dual pathways RC-IGBT device as described in claim 1, it is characterised in that described drift region structure is NPT structure or FS
Structure.
4. dual pathways RC-IGBT device as described in claim 1, it is characterised in that the semi-conducting material of described RC-IGBT device
Si, SiC, GaAs or GaN is used to make.
5. dual pathways RC-IGBT device as described in claim 1, it is characterised in that the dielectric material of described first medium layer is
SiO2、HfO2、Al2O3Or Si3N4。
6. the preparation method of dual pathways RC-IGBT as described in claim 1, comprises the following steps:
The first step: choose N-drift region FZ silicon chip being lightly doped in order to form RC-IGBT；Noted by repeatedly photoetching, oxidation, ion
Enter, anneal, depositing technics makes the Facad structure of RC-IGBT at front side of silicon wafer, including emitter structure and grid structure；
Second step: upset silicon chip, thinning silicon chip back side is to desired thickness；
3rd step: the predeterminable area at silicon chip back side is hindered by the N-type field of ion implanting N-type impurity the making RC-IGBT that anneals
Only layer, the thickness of the N-type field stop layer of formation is 2～5 microns；
4th step: photoetching, the predeterminable area at silicon chip back side passes through ion implanting p type impurity and makes the p-type current collection of RC-IGBT
District, the thickness of the p-type collecting zone of formation is 0.5～1 micron；
5th step: photoetching, the predeterminable area at silicon chip back side passes through ion implanting N-type impurity the N-type of the making RC-IGBT that anneals
Collecting zone, the thickness of the N-type collecting zone of formation is less than the thickness of p-type collecting zone 0.1～0.3 micron；
6th step: oxidation or dielectric layer deposited, photoetching etch media form first medium layer, and the thickness of first medium layer is less than
0.1 micron；
7th step: deposit photoetching, etching metal formation metal ohmic contact and Schottky contact metal；
8th step: deposit photoetching, etch media layer formation second dielectric layer；
9th step: deposit photoetching, etching metal formation metal collector；
I.e. it is prepared into dual pathways RC-IGBT.
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| CN107946243A (en) * | 2017-12-22 | 2018-04-20 | 江苏宏微科技股份有限公司 | A kind of back side design of RC IGBT |
| CN110571264A (en) * | 2019-09-17 | 2019-12-13 | 重庆邮电大学 | SA-LIGBT device with multichannel current bolt |
| CN111261698A (en) * | 2020-02-14 | 2020-06-09 | 电子科技大学 | RC-LIGBT device for eliminating voltage folding phenomenon |
| CN113270475A (en) * | 2021-04-08 | 2021-08-17 | 西安电子科技大学 | Short-circuit anode transverse insulated gate bipolar transistor controlled by Schottky junction barrier and manufacturing method thereof |
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| CN110571264B (en) * | 2019-09-17 | 2023-03-24 | 重庆邮电大学 | SA-LIGBT device with multichannel current bolt |
| CN111261698A (en) * | 2020-02-14 | 2020-06-09 | 电子科技大学 | RC-LIGBT device for eliminating voltage folding phenomenon |
| CN111261698B (en) * | 2020-02-14 | 2021-08-06 | 电子科技大学 | RC-LIGBT device for eliminating voltage folding phenomenon |
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