CN110504310A - A kind of RET IGBT and preparation method thereof with automatic biasing PMOS - Google Patents
A kind of RET IGBT and preparation method thereof with automatic biasing PMOS Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention belongs to power semiconductor device technology fields, are related to a kind of RET IGBT and preparation method thereof with automatic biasing PMOS.The present invention is by the way that N-type charge storage layer to be placed between p-type base area and p type buried layer, while improving device forward conduction characteristic, influence of the N-type N-type charge storage layer to the breakdown voltage of device can be shielded, by introducing PMOS structure, additional access is provided for the extraction in hole, accelerate the extraction speed of carrier, improve the switching speed of device, reduce the turn-off power loss of device, the separate gate structures of emitter embedded type can satisfy the further constriction of part table to improve and be easy to the metal contact hole of making devices emitter under conditions of device forward conduction characteristic while can further decrease the Miller capacitance of device simultaneously.
Description
Technical field
The invention belongs to power semiconductor device technology fields, are related to a kind of emitter embedded type with automatic biasing PMOS
The insulated gate bipolar transistor (RET IGBT) of groove.
Technical background
Insulated gate bipolar transistor (IGBT) is as power electronic devices of new generation because it combines field effect transistor
The advantages of managing (MOSFET) and bipolar crystal type transistor (BJT), both there is MOSFET to be easy to, and driving, input impedance is low, switchs
Fireballing advantage, and have the advantages that BJT on state current density is big, conduction voltage drop is low, loss is small, stability is good.Thus send out
Exhibition is one of the core electron component in modern power electronic circuit, is widely used in traffic, communication, household electrical appliance and boat
Empty space flight every field.The utilization of IGBT significantly improves the performance of power electronic system.
Between more than 30 years since emerging from IGBT, how to have reduced the switching loss of IGBT, improve device conduction voltage drop and
The tradeoff of turn-off power loss is always the emphasis of people's research.Planar gate punch IGBT (PT- of the IGBT from the first generation
IGBT) to the field prevention type trench IGBT (FS-IGBT) in the 6th generation, researcher by continuously improve IGBT Facad structure and
Backside structure makes the performance of IGBT be continuously available promotion, however, performance is appointed so can be into one for the 6th generation FS-IGBT
Step is improved, and on this basis, the 7th generation gap slot charge storage type IGBT (CSTBT) is developed.Compared to FS-IGBT,
CSTBT provides hole due to introducing one layer of N-type charge storage layer, the introducing of N-type carrier accumulation layer below p-type base area
Potential barrier improves device drift region Carrier Profile, reduces the conduction voltage drop of device so that surface carrier concentration enhances,
Optimize the tradeoff between the conduction voltage drop of device and switching loss.However, charge storage layer can make the breakdown potential of device
Pressure is raw to degenerate.In order to guarantee that the breakdown voltage of device will not degenerate, the depth of trench gate needs do it is deep, however
Deep trench gate depth can be such that the gate capacitance especially Miller capacitance of device increases, and reduce the switching speed of device, increase
The switching loss of device.
Summary of the invention
Make to improve the trench gate of influence and depth that the introducing of carrier accumulation layer causes CSTBT breakdown characteristics to be degenerated
Device the influence that increases of Miller capacitance, the invention proposes a kind of RET IGBT structure such as Fig. 2 with automatic biasing PMOS
Shown, the present invention is embedded in N-type charge storage layer in p-type base area, so that device is in reverse withstand voltage, N-type charge storage layer is by P
The isolation of type base area, eliminates influence of the N-type charge storage layer to device electric breakdown strength, what the PMOS structure of introducing was turned off in device
When for the extraction in hole provide additional access, accelerate the extraction speed of carrier, reduce the turn-off power loss of device.
The separate gate structures of emitter embedded type can satisfy the further constriction of part table to improve the item of device forward conduction characteristic
It is easy to the metal contact hole of making devices emitter under part while the Miller capacitance of device can be further decreased.
Technical scheme is as follows:
A kind of RET IGBT structure with automatic biasing PMOS, half structure cell are as shown in Figure 2, comprising: from bottom to up
Back collector electrode metal 1, p-type collecting zone 2, N-type field stop layer 3 and the drift region N- 4 being cascading are located at the drift region N-
The groove structure of 4 tops, the groove structure include gate dielectric layer 6, polycrystalline gate electrode 7, are located at gate dielectric layer 6 and gate electrode 7
The dielectric layer 10 of top；It is characterized in that above the drift region N- 4 have p type buried layer 12, separate gate structures, the separation
Grid structure includes polycrystalline separate gate electrodes 15, gate dielectric layer 14；12 top of p type buried layer has N-type charge storage layer 13；Institute
13 top of N-type charge storage layer is stated with p-type base area 5；5 top of p-type base area has N+ emitter region 8 and the contact zone P+ 9；Institute
10 top of dielectric layer, 8 top of N+ emitter region, 9 top of the contact zone P+, separate gate structures top are stated with emitter metal 11, is divided
It is shorted between gate electrode 15 and emitter metal 11.
Further, a kind of RET IGBT structure with automatic biasing PMOS, half structure cell is as shown in figure 3, it is special
Point is that the Ohmic contact above P+ emitter region is changed to Schottky contacts.
Further, a kind of RET IGBT structure with automatic biasing PMOS, half structure cell is as shown in figure 4, it is special
Point is that super-junction structure is introduced in drift region, and super-junction structure is made of superjunction N column 41, superjunction P column 42；Draw below gate electrode 7
Enter separate gate structures, separate gate structures are made of separate gate electrodes 71 and gate dielectric layer 61, separate gate electrodes 71 and separate gate electricity
Pole 15 is shorted.
Further, a kind of RET IGBT structure with automatic biasing PMOS, half structure cell is as shown in figure 5, it is special
Point is spiled in silicon, and aperture is located at 5 middle part of p-type base area, and a part of silicon is respectively stayed in two sides, and separate gate electrodes 15 are without mistake
Etching.
Further, a kind of RET IGBT structure with automatic biasing PMOS, half structure cell is as shown in fig. 6, it is special
Point is to introduce p-type floating area in separate gate structures side.
Further, multiple duplicate separate gate structures can be introduced in the devices,
IGBT device semiconductor material in the further present invention uses Si, SiC, GaAs or GaN, trench fill material
Material uses polycrystalline Si, SiC, GaAs or GaN, and different materials combination can also be used in each section using identical material.
Further, the device architecture is applicable not only to IGBT device, and the p-type collecting zone 2 at the device back side is changed to N+
Layer, the structure are equally applicable to MOSFET element.
A kind of RET IGBT structure with automatic biasing PMOS, comprises the following steps that:
The present invention is illustrated by taking a kind of RET IGBT structure with automatic biasing PMOS of 1200V voltage class as an example,
The device of different performance parameter can be prepared according to actual needs according to common sense in the field.
Step 1: as shown in fig. 7, N- drift region 4 of the monocrystalline silicon piece as device, selected silicon wafer is lightly doped using using N-type
With a thickness of 300~600um, doping concentration 1013~1014A/cm3；
Step 2: as shown in figure 8, depositing protective layer in silicon chip surface, making window by lithography and carry out groove silicon etching, etch
Gate electrode groove and separate gate electrodes groove；
Step 3: as shown in figure 9,1050 DEG C~1150 DEG C of O2One layer of sacrificial oxide layer is grown in trenched side-wall under atmosphere,
Then sacrificial oxide layer is got rid of again in 1050 DEG C~1150 DEG C of O2One layer of gate oxide is grown in trenched side-wall under atmosphere；
Step 4: as shown in Figure 10, in 750 DEG C~950 DEG C depositing polysilicons on the dielectric layer, then anti-carving eating away
Excess surface polysilicon；
Step 5: as shown in figure 11, growing one layer of pre-oxidation layer in silicon chip surface, P is made by ion implanting p type impurity
Type buried layer 12, ion implantation energy are 200~500keV, ion implantation dosage 1012~1014A/cm2, annealing temperature is
1000 DEG C~1100 DEG C, annealing time is 20~30 minutes；N-type charge storage layer, ion is made by ion implanting N-type impurity
Implantation Energy is 200~400keV, ion implantation dosage 1012~1014A/cm2, annealing temperature is 1000 DEG C~1100 DEG C,
Annealing time is 10~30 minutes；P-type base area, ion implantation dosage 10 is made by ion implanting p type impurity12~1014
A/cm2, annealing temperature is 1000 DEG C~1100 DEG C, and annealing time is 10~30 minutes；N is made by ion implanting N-type impurity
+ emitter region, ion implantation energy are 60~100keV, ion implantation dosage 1014~1015A/cm2；
Step 6: as shown in figure 12, by mask, photoetching, etching and etc. carry out silicon etching, etching depth be greater than N+
The junction depth of emitter region, less than the junction depth of p-type base area；
Step 7: as shown in figure 13, ion implanting p type impurity is made the contact zone P+, ion implantation energy for 50~
100KeV, ion implantation dosage 1014~1015A/cm2；
Step 8: as shown in figure 14, depositing silica and etch away extra medium formation barrier from dielectric layer；
Step 9: as shown in figure 15, device front deposits metal and makes emitter metal；
Step 10: as shown in figure 16, silicon wafer is overturn,；N-type field stop layer 3, ion implanting is made in ion implanting N-type impurity
Energy is 200~500keV；Ion implantation dosage is 1012~1014A/cm2, using laser annealing；Ion implanting p type impurity system
P+ collecting zone is obtained, ion implantation energy is 50~100KeV, ion implantation dosage 1012~1015A/cm2；Deposit made of metal obtains
Metal collector.
Further, the step of making groove structure emits with production p type buried layer, N-type charge storage layer, p-type base area, N+
The step of area, can exchange.
Further, to simplify the description, above-mentioned device architecture and preparation method be by taking N-channel IGBT device as an example for
It is bright, but the present disclosure applies equally to the preparations of P-channel IGBT device.
The working principle of the invention
When high potential, the collector 1 that 7 knot of emitter is higher than device threshold voltage connect high potential, emitter 11 connects low potential
When, device works on state, and P+ emitter region 2 injects hole into the drift region N- 4, and N+ emitter region 8 is infused into the drift region N- 4
Enter electronics, the presence of electron hole pair makes that conductivity modulation effect occurs in drift region, simultaneously because N depositing to charge storage layer
The accumulation for enhancing surface voids improves the Carrier Profile of drift region, reduces the forward conduction voltage drop of device；Work as hair
When emitter-base bandgap grading 7, emitter 11 connect low potential, when collector 1 connects high potential, device work in blocking state, at this time p type buried layer 12 with
Separate gate structures can effectively shield influence of the N-type charge storage layer 13 to device electric breakdown strength, simultaneously because separate gate structures
Additional lead to is provided with the PMOS structure that p-type base area 5, N-type charge storage layer 13, p type buried layer 12 are constituted for the extraction in hole
Road accelerates the extraction speed of carrier, improves the switching speed of device, reduces the turn-off power loss of device, emit simultaneously
The separate gate structures of pole embedded type can satisfy the further constriction of part table come under conditions of improving device forward conduction characteristic
It is easy to the metal contact hole of making devices emitter while the Miller capacitance of device can be further decreased.
Beneficial effects of the present invention are shown:
The present invention is improving the positive guide of device by the way that N-type charge storage layer to be placed between p-type base area and p type buried layer
While logical characteristic, influence of the N-type N-type charge storage layer to the breakdown voltage of device can be shielded, by introducing PMOS structure,
Additional access is provided for the extraction in hole, the extraction speed of carrier is accelerated, improves the switching speed of device, is reduced
The turn-off power loss of device, while the separate gate structures of emitter embedded type can satisfy the further constriction of part table to improve
It is easy to the metal contact hole of making devices emitter under conditions of device forward conduction characteristic while device can be further decreased
Miller capacitance.
Detailed description of the invention
Fig. 1 is the half cellular structural schematic diagram of tradition FS-IGBT, wherein 1 is collector electrode metal, and 2 be P+ collecting zone, and 3 are
N-type field stop layer, 4 be the drift region N-, and 5 be p-type base area, and 6 be gate dielectric layer, and 7 be polycrystalline gate electrode, and 8 be N+ emitter region, and 9 be P
+ contact zone, for 10 barriers from dielectric layer, 11 be emitter metal.
Fig. 2 is a kind of half cellular structural schematic diagram of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 1 provides；
Fig. 3 is a kind of half cellular structural schematic diagram of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 2 provides；
Fig. 4 is a kind of half cellular structural schematic diagram of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 3 provides；
Fig. 5 is a kind of half cellular structural schematic diagram of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 4 provides；
Fig. 6 is a kind of half cellular structural schematic diagram of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 5 provides；
Fig. 7 is after a kind of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 2 provides forms the drift region N- 4
Process schematic representation；
Fig. 8 be the embodiment of the present invention 2 provide a kind of RET IGBT with automatic biasing PMOS etch to be formed gate groove with
Process schematic representation after separating gate groove；
Fig. 9 is a kind of RET IGBT gate dielectric layer 6 and separate gate with automatic biasing PMOS that the embodiment of the present invention 2 provides
Process schematic representation after dielectric layer 14；
Figure 10 is that a kind of RET IGBT deposit polycrystalline with automatic biasing PMOS that the embodiment of the present invention 2 provides forms grid electricity
Process schematic representation behind pole 7 and separate gate electrodes 15；
Figure 11 is that a kind of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 2 provides forms p type buried layer 12, N
Process schematic representation after type charge storage layer 13, p-type base area 5, N+ emitter region 3；
Figure 12 is a kind of RET IGBT etching silicon and separate gate knot with automatic biasing PMOS that the embodiment of the present invention 2 provides
Process schematic representation after structure；
Figure 13 is after a kind of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 2 provides forms the contact zone P+ 9
Process schematic representation；
Figure 14 is that a kind of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 2 provides forms barrier from dielectric layer
Process schematic representation after 10；
Figure 15 is that a kind of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 2 provides forms emitter metal 11
Process schematic representation afterwards；
Figure 16 is that a kind of RET IGBT with automatic biasing PMOS that the embodiment of the present invention 2 provides forms N-type field stop layer
3, the process schematic representation after P+ collecting zone 2, collector electrode metal 1；
Fig. 2 is into Figure 16, and 1 is collector electrode metal, and 2 be collecting zone, and 3 be N-type field stop layer, and 4 be the drift region N-, and 41 be super
N column is tied, 42 be superjunction P column, and 5 be p-type base area, and 6 be gate dielectric layer, and 61 be gate dielectric layer, and 7 be polycrystalline gate electrode, and 71 be polycrystalline
Separate gate electrodes, 8 be N+ emitter region, and 9 be P+ emitter region, and 10 be barrier from dielectric layer, and 11 be emitter metal, and 12 bury for p-type
Layer, 13 be N-type charge storage layer, and 14 is separate gate dielectric layer, and 15 be polycrystalline separate gate electrodes, and 16 be Schottky contact metal,
17 be p-type floating area, and 18 be dielectric layer.
Specific embodiment
Below in conjunction with attached drawing, the principle of the present invention and characteristic are described further, illustrated embodiment is served only for explaining
The present invention is not intended to limit the scope of the present invention.
Embodiment 1
A kind of RET IGBT device embodiment with automatic biasing PMOS, as shown in Figure 2, comprising: successively layer from bottom to up
Back collector electrode metal 1, p-type collecting zone 2, N-type field stop layer 3 and the drift region N- 4 of folded setting are located at 4 top of the drift region N-
With trench gate structure, the groove structure includes gate dielectric layer 6, and gate electrode 7 is located at gate dielectric layer 6,7 top of gate electrode
Dielectric layer 10；It is characterized by: above the drift region N- 4 have p type buried layer 12, separate gate structures, the separate gate structures
Including polycrystalline separate gate electrodes 15, gate dielectric layer 14；12 top of p type buried layer has N-type charge storage layer 13；The N-type
13 top of charge storage layer has p-type base area 5；5 top of p-type base area has N+ emitter region 8 and the contact zone P+ 9；It is given an account of
10 top of matter layer, 8 top of N+ emitter region, 9 top of the contact zone P+, separate gate structures top have emitter metal 11；The grid
Electrode 7 passes through the drift region gate dielectric layer 6 and N- 4, p type buried layer 12, N-type charge storage layer 13, p-type base area 5,8 phase of N+ emitter region
Even；The separate gate electrodes 15 pass through separation gate dielectric layer 14 and the drift region N- 4, p type buried layer 12, N-type charge storage layer 13, P
Type base area 5, the contact zone P+ 9 are connected；The depth of the separate gate structures and trench gate is greater than the junction depth of p type buried layer 12；The hair
Emitter-base bandgap grading metal a part is embedded into p-type base area；The separate gate electrodes 15 and 11 equipotential of emitter metal；The separate gate
The thickness of dielectric layer 14 is greater than or equal to the thickness of gate dielectric layer 6.
Embodiment 2
A kind of RET IGBT device embodiment with automatic biasing PMOS, as shown in Figure 3, comprising: successively layer from bottom to up
Back collector electrode metal 1, p-type collecting zone 2, N-type field stop layer 3 and the drift region N- 4 of folded setting are located at 4 top of the drift region N-
With trench gate structure, the groove structure includes gate dielectric layer 6, and gate electrode 7 is located at gate dielectric layer 6,7 top of gate electrode
Dielectric layer 10；It is characterized in that having p type buried layer 12, separate gate structures, the separate gate structures packet above the drift region N- 4
Include polycrystalline separate gate electrodes 15, gate dielectric layer 14；12 top of p type buried layer has N-type charge storage layer 13；The N-type electricity
13 top of lotus accumulation layer has p-type base area 5；5 top of p-type base area has N+ emitter region 8 and the contact zone P+ 9；The medium
10 top of layer, 8 top of N+ emitter region, separate gate structures top have emitter metal 11, and 9 top of the contact zone P+ has Xiao
Te Ji contacts metal 16；The gate electrode 7 by gate dielectric layer 6 and the drift region N- 4, p type buried layer 12, N-type charge storage layer 13,
P-type base area 5, N+ emitter region 8 are connected；The separate gate electrodes 15 pass through separation gate dielectric layer 14 and the drift region N- 4, p type buried layer
12, N-type charge storage layer 13, p-type base area 5, the contact zone P+ 9 are connected；The depth of the separate gate structures and trench gate is greater than p-type
The junction depth of buried layer 12；Described emitter metal a part is embedded into p-type base area；The separate gate electrodes 15 and emitter metal
11 equipotentials；The thickness of the separation gate dielectric layer 14 is greater than or equal to the thickness of gate dielectric layer 6；The Xiao Te contacts metal 16
It can be same type metal with emitter metal 11 and be also possible to different type metal.
Embodiment 3
A kind of RET IGBT device embodiment with automatic biasing PMOS, as shown in figure 4, existing on the basis of embodiment 1
The super-junction structure being made of superjunction N column 41 and superjunction P column 42 is introduced in drift region, the junction depth of superjunction P column 42 is less than or equal to superjunction N
The junction depth of column 41, introduces separate gate electrodes 71 below gate electrode 71, and the separate gate electrodes 71 are shorted with separate gate electrodes 15.
The introducing of super-junction structure further reduced the conduction voltage drop of device and improve the breakdown voltage of device, separate gate
The introducing of electrode 71 further reduced the Miller capacitance of device.
Embodiment 4
A kind of RET IGBT device embodiment with automatic biasing PMOS, as shown in figure 4, on the basis of embodiment 2
It spiles in silicon when doing emitter metal, aperture is located in the middle part of p-type base area, and respectively there are silicon, separate gate electrodes 15 for aperture two sides
Without over etching.
Spiling, which facilitates cellular table top, further reduces.
Embodiment 5
A kind of RET IGBT device embodiment with automatic biasing PMOS, as shown in fig. 6, existing on the basis of embodiment 1
Separate gate side introduces p-type floating area 17, and the junction depth in PP type floating area 17 is less than or equal to the depth of separate gate.
The introducing in p-type floating area increases the accumulation of device surface carrier, improves the distribution of drift region carrier, reduces
The conduction voltage drop of device.
Claims (10)
1. a kind of RET IGBT with automatic biasing PMOS, structure cell include: the back being cascading from bottom to up
Collector electrode metal (1), p-type collecting zone (2), N-type field stop layer (3) and the drift region N- (4), the drift region N- (4) upper layer side have
There is trench gate structure, the groove structure includes gate dielectric layer (6) and the gate electrode (7) in gate dielectric layer (6), gate medium
There are dielectric layer (10) above layer (6) and gate electrode (7)；It is characterized by: having p type buried layer above the drift region N- (4)
(12) and separate gate structures, separate gate structures are located at the drift region N- (4) upper layer other side, and p type buried layer (12) is located at trench gate knot
Between structure and separate gate structures；The separate gate structures include gate dielectric layer (14) and the polycrystalline being located in gate dielectric layer (14) point
From gate electrode (15) and it is located at gate dielectric layer (14)；P type buried layer (12) top has N-type charge storage layer (13)；The N
Type charge storage layer (13) top has p-type base area (5)；P-type base area (5) top has N+ close to trench gate structure side
Emitter region (8) has the contact zone P+ (9) close to separate gate structures side, and the junction depth of the contact zone P+ (9) upper surface is sent out less than N+
Penetrate the junction depth of area (8) lower surface；Dielectric layer (10) top, N+ emitter region (8) top, the contact zone P+ (9) top, separate gate
Structure upper has emitter metal (11)；The gate electrode (7) passes through gate dielectric layer (6) and the drift region N- (4), p type buried layer
(12), N-type charge storage layer (13), p-type base area (5), N+ emitter region (8) are connected；The separate gate electrodes (15) pass through separation
Gate dielectric layer (14) and the drift region N- (4), p type buried layer (12), N-type charge storage layer (13), p-type base area (5), the contact zone P+
(9) it is connected；The depth of the separate gate structures and trench gate is greater than the junction depth of p type buried layer (12)；The emitter metal one
Divide and is embedded into p-type base area；The separate gate electrodes (15) and emitter metal (11) equipotential；The separation gate dielectric layer
(14) thickness is greater than or equal to the thickness of gate dielectric layer (6).
2. a kind of RET IGBT with automatic biasing PMOS, structure cell include include: to be cascading from bottom to up
Back collector electrode metal (1), p-type collecting zone (2), N-type field stop layer (3) and the drift region N- (4), the drift region N- (4) upper layer one
Side has trench gate structure, and the groove structure includes gate dielectric layer (6) and the gate electrode (7) in gate dielectric layer (6), grid
There are dielectric layer (10) above dielectric layer (6) and gate electrode (7)；It is characterized by: having p-type above the drift region N- (4)
Buried layer (12) and separate gate structures, separate gate structures are located at the drift region N- (4) upper layer other side, and p type buried layer (12) is located at groove
Between grid structure and separate gate structures；The separate gate structures include gate dielectric layer (14) and are located at more in gate dielectric layer (14)
Brilliant separate gate electrodes (15) and be located at gate dielectric layer (14)；P type buried layer (12) top has N-type charge storage layer (13)；
N-type charge storage layer (13) top has p-type base area (5)；P-type base area (5) top is close to trench gate structure side
There are the contact zone P+ (9) with N+ emitter region (8), close to separate gate structures side, and the junction depth of the contact zone P+ (9) upper surface is small
Junction depth in N+ emitter region (8) lower surface, the contact zone P+ (9) top have Schottky contact metal (16)；The medium
Layer (10) top, N+ emitter region (8) top, separate gate structures top have emitter metal (11)；The gate electrode (7) passes through
Gate dielectric layer (6) and the drift region N- (4), p type buried layer (12), N-type charge storage layer (13), p-type base area (5), N+ emitter region (8)
It is connected；The separate gate electrodes (15) pass through separation gate dielectric layer (14) and the drift region N- (4), p type buried layer (12), N-type charge
Accumulation layer (13), p-type base area (5), the contact zone P+ (9) are connected；The depth of the separate gate structures and trench gate is greater than p type buried layer
(12) junction depth；Described emitter metal a part is embedded into p-type base area；The separate gate electrodes (15) and emitter metal
(11) equipotential；The thickness of separation gate dielectric layer (14) is greater than or equal to the thickness of gate dielectric layer (6).
3. a kind of RET IGBT with automatic biasing PMOS according to claim 1, it is characterised in that introduced in drift region
The junction depth of the super-junction structure being made of superjunction N column (41) and superjunction P column (42), superjunction P column (42) is less than or equal to superjunction N column (41)
Junction depth, introduce separate gate electrodes (71) below the gate electrode (7), the separate gate electrodes (71) and separate gate electrodes (15) it
Between be shorted.
4. a kind of RET IGTBT with automatic biasing PMOS according to claim 2, it is characterised in that doing emitter gold
It spiles in silicon when category, aperture is located in the middle part of p-type base area, and respectively there are silicon for aperture two sides, and separate gate electrodes (15) are without mistake
Etching.
5. a kind of RET IGBT with automatic biasing PMOS according to claim 1, it is characterised in that draw in separate gate side
RuPXing floating area (17), the junction depth in PP type floating area (17) are less than or equal to the depth of separate gate.
6. a kind of RET IGBT with automatic biasing PMOS according to claim 1, feature introduces multiple heavy in the devices
Multiple separate gate structures.
7. a kind of RET IGBT with automatic biasing PMOS according to claim 1, it is characterised in that IGBT device semiconductor
Using Si, SiC, GaAs, perhaps GaN trench fill material uses polycrystalline Si, SiC, GaAs or GaN to material, and each section can
Different materials combination can also be used using identical material.
8. a kind of production method of the RET IGBT with automatic biasing PMOS, which is characterized in that comprise the following steps that:
Step 1: as shown in fig. 6, N- drift region (4) of the monocrystalline silicon piece as device is lightly doped using using N-type, selected silicon wafer is thick
Degree is 300~600um, doping concentration 1013~1014A/cm3；
Step 2: as shown in fig. 7, depositing protective layer in silicon chip surface, making window by lithography and carry out groove silicon etching, etch grid electricity
Pole groove and separate gate electrodes groove；
Step 3: as shown in figure 8,1050 DEG C~1150 DEG C of O2One layer of sacrificial oxide layer is grown in trenched side-wall under atmosphere, then
Sacrificial oxide layer is got rid of again in 1050 DEG C~1150 DEG C of O2One layer of gate oxide is grown in trenched side-wall under atmosphere；
Step 4: as shown in figure 9, it is more then to anti-carve eating away surface in 750 DEG C~950 DEG C depositing polysilicons on the dielectric layer
Remaining polysilicon；
Step 5: as shown in Figure 10, growing one layer of pre-oxidation layer in silicon chip surface, p-type is made by ion implanting p type impurity and is buried
Layer (12), ion implantation energy are 200~500keV, ion implantation dosage 1012~1014A/cm2, annealing temperature 1000
DEG C~1100 DEG C, annealing time is 20~30 minutes；N-type charge storage layer, ion implanting is made by ion implanting N-type impurity
Energy is 200~400keV, ion implantation dosage 1012~1014A/cm2, annealing temperature is 1000 DEG C~1100 DEG C, annealing
Time is 10~30 minutes；P-type base area, ion implantation dosage 10 is made by ion implanting p type impurity12~1014A/cm2,
Annealing temperature is 1000 DEG C~1100 DEG C, and annealing time is 10~30 minutes；N+ transmitting is made by ion implanting N-type impurity
Area, ion implantation energy are 60~100keV, ion implantation dosage 1014~1015A/cm2；
Step 6: as shown in figure 11, by mask, photoetching, etching and etc. carry out silicon etching, etching depth be greater than N+ transmitting
The junction depth in area, less than the junction depth of p-type base area；
Step 7: as shown in figure 12, the contact zone P+ is made in ion implanting p type impurity, and ion implantation energy is 50~100KeV, from
Sub- implantation dosage is 1014~1015A/cm2；
Step 8: as shown in figure 13, depositing silica and etch away extra medium formation barrier from dielectric layer；
Step 9: as shown in figure 14, device front deposits metal and makes emitter metal；
Step 10: as shown in figure 15, silicon wafer is overturn,；N-type field stop layer (3) are made in ion implanting N-type impurity, ion implanting energy
Amount is 200~500keV；Ion implantation dosage is 1012~1014A/cm2, using laser annealing；Ion implanting p type impurity is made
P+ collecting zone, ion implantation energy are 50~100KeV, ion implantation dosage 1012~1015A/cm2；Deposit made of metal obtains golden
Belong to collector.
9. the production method of RET IGBT with automatic biasing PMOS according to claim 8 a kind of, which is characterized in that system
The step of making groove structure can exchange with the step of production p type buried layer, N-type charge storage layer, p-type base area, N+ emitter region.
10. the production method of RET IGBT with automatic biasing PMOS according to claim 8 a kind of, which is characterized in that
The preparation method is equally applicable to the preparation of P-channel IGBT device.
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