CN105742346B - Double division trench gate charge storage type RC-IGBT and its manufacturing method - Google Patents
Double division trench gate charge storage type RC-IGBT and its manufacturing method Download PDFInfo
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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Abstract
The invention belongs to power semiconductor device technology fields, and in particular to inverse conductivity type trench gate charge storage type insulated gate bipolar transistor.The present invention passes through the dielectric layer between the bottom of gate electrode in RC IGBT device grooves and the equipotential double Split Electrodes of lateral leadin and emitter and double Split Electrodes and gate electrode, the switching speed of device is improved in IGBT operating modes, the carrier concentration profile of entire N-type drift region is improved, reduces the switching loss of device；The saturation current density of device is reduced, the short-circuit safety operation area of device is improved, improves reliability；Make reversed fly-wheel diode that there is low diode conduction voltage drop in reversed fly-wheel diode operating mode, and improve the reverse recovery characteristic of fly-wheel diode；Double division trench gate charge storage type IGBT production methods proposed by the invention simultaneously need not increase additional processing step, compatible with traditional RC IGBT production methods.
Description
Technical field
The invention belongs to power semiconductor device technology fields, are related to insulated gate bipolar transistor (IGBT), specifically relate to
And inverse conductivity type trench gate charge storage type insulated gate bipolar transistor (RC-CSTBT).
Background technology
Insulated gate bipolar transistor (IGBT) be a kind of MOS field-effects and bipolar transistor it is compound novel electric power electricity
Sub- device.Its existing MOSFET is easy to drive, and controls the advantages of simple, and has that power transistor turns pressure drop is low, on state current
Greatly, the advantages of small is lost, it has also become one of core electron component in modern power electronic circuit is widely used in such as
The every field of the national economy such as communication, the energy, traffic, industry, medicine, household electrical appliance and aerospace.The application pair of IGBT
The promotion of power electronic system performance plays particularly important effect.Since IGBT inventions, people have been devoted to improve
The performance of IGBT.By the development of twenties years, 6 generation IGBT device structures were proposed in succession, device performance is made to have obtained steadily
Promotion.The trench gate charge storage type insulated gate bipolar transistor (CSTBT) in the 6th generation is as a result of higher-doped concentration
With certain thickness N-type charge storage layer structure, IGBT device is made to have obtained pole close to the carrier concentration profile of emitter terminal
Big improvement improves the conductance modulation of N-type drift region, improves the carrier concentration profile of entire N-type drift region, makes IGBT
Obtain the compromise of the forward conduction voltage drop and turn-off power loss of low forward conduction voltage drop and improvement.
In power electronic system, IGBT usually requires collocation fly-wheel diode (Free Wheeling Diode, FWD)
It is used to ensure that the safety and stability of system.Therefore in traditional IGBT module or single tube device, it will usually have FWD with it reversely simultaneously
Connection, the program not only increase the number of device, the volume and production cost of module, and in encapsulation process solder joint number increase
The reliability of device can be influenced, ghost effect caused by metal connecting line has an effect on the overall performance of device.In order to solve this
Problem realizes the integration of product, and with reference to CSTBT device architectures, industry proposes inverse conductivity type trench gate charge storage type insulated gate
Fly-wheel diode, is successfully integrated in inside CSTBT, structure is as shown in Figure 1 by bipolar transistor (RC-CSTBT).It compares
In CSTBT of the tradition without afterflow ability, which has made at its back connects with metal collector 13 and N-type electric field trapping layer 10
The N-type collecting zone 12 connect, the region form parasitism two with p-type base 7, N-type charge storage layer 8 and N- drift regions 9 in device
Pole pipe structure, the parasitic diode conducting offer current path under freewheeling mode.
However, for traditional RC-CSTBT device architectures, in positive IGBT operating modes, due to higher-doped concentration
With the presence of certain thickness N-type charge storage layer, the breakdown voltage of device significantly reduces, and is deposited to effectively shield N-type charge
The adverse effect of reservoir obtain certain device it is pressure-resistant, it is necessary to using：1) deep trench gate depth, is more than the depth of trench gate
The junction depth of N-type charge storage layer, but deep trench gate depth not only increases gate-emitter capacitance, also increases grid-collection
Electrode capacitance, thus, reduce the switching speed of device, increase the switching loss of device, affect device conduction voltage drop and
The compromise characteristic of switching loss；2) small cellular width, makes the spacing between trench gate reduce as far as possible, however, highdensity
Trench MOS structure not only increases the grid capacitance of device, reduces the switching speed of device, increases the switch damage of device
Consumption, affects the conduction voltage drop of device and the compromise characteristic of switching loss, moreover, adding the saturation current density of device, makes
The short-circuit safety operation area of device is deteriorated.In backward dioded afterflow operating mode, due to p-type base 7 and N-type charge storage
The presence of the built-in potential for the PN junction that layer 8/N- drift regions 9 are formed, forward conduction voltage drop is larger, simultaneously because being led in fly-wheel diode
A large amount of carriers are injected into N- drift regions 9 when logical, and the presence of excessive carrier so that the Reverse recovery of fly-wheel diode is special
Property is poor, such as reverse recovery time is long, reverse recovery charge is big.
The content of the invention
The purpose of the invention is to optimize the positive IGBT characteristics of traditional RC-CSTBT, while improve backward dioded spy
Property, the reliability of device is improved, on the basis of traditional RC-CSTBT device architectures (as shown in Figure 1), the present invention provides a kind of
Double division trench gate charge storage type RC-IGBT (as shown in Figure 2) and preparation method thereof, the RC-IGBT devices are in forward direction
During IGBT operating modes, in the case of certain device trench depth and trench MOS structure density, by device trenches
The bottom of gate electrode and lateral leadin and the equipotential double Split Electrodes of emitter, pass through double Split Electrodes and double Split Electrodes
The shielding action of thick dielectric layer between gate electrode reduces the grid capacitance of device, particularly grid-collector capacitance, carries
The high switching speed of device, reduces switching loss, further improves the compromise of forward conduction voltage drop and switching loss, together
When, the introducing of side Split Electrode reduces the density of MOS raceway grooves, improves the short-circuit safety operation area of IGBT, improves device
The Performance And Reliability of part；In addition, the carrier that the wide bottom Split Electrode of channel bottom further enhances emitter terminal increases
It is potent to answer, the carrier concentration profile of entire N-type drift region is further improved, forward conduction voltage drop is further improved and opens
The compromise of loss is closed, improves the performance of device；Meanwhile existed by thick dielectric layer and wide width around the Split Electrode of bottom
Further effectively shielded in the case of certain device trench depth and trench MOS structure density N-type charge storage layer with
And the thin dielectric layer influence pressure-resistant to device at gate electrode and side Split Electrode, the breakdown voltage of device is improved, is improved
The concentration of channel bottom electric field further improves the reliability of device.In backward dioded afterflow operating mode, pass through
The effect for the side Split Electrode being connected with emitter opens the MOS raceway grooves at the Split Electrode of side, makes reversed two pole of afterflow
Pipe works in how sub- device model, has low backward dioded conduction voltage drop and excellent reverse recovery characteristic.The present invention carries
The production method of confession need not increase additional processing step, with traditional trench gate charge storage type RC-IGBT production methods
It is compatible.
The technical scheme is that：Double division trench gate charge storage type RC-IGBT, including stacking gradually from bottom to up
Collector electrode metal 13, p-type collector area 11, N-type electric field trapping layer 10, N-type drift region 9 and the emitter metal 1 of setting；Also wrap
Include the N-type collector area 12 being set up in parallel with p-type collector area 11；There is N+ launch sites 5, P+ to emit in the N-type drift region 9
Area 6, p-type base 7, N-type charge storage layer 8 and trench gate structure；The trench gate structure vertically sequentially passes through N+ hairs
It is extended to after penetrating area 5, p-type base 7 and N-type charge storage layer 8 in N-type drift region；The p-type base 7 is located at N-type charge storage
8 upper surface of layer, N+ launch sites 5 and P+ launch sites 6 are located at 7 upper surface of p-type base side by side；N+ launch sites 5 and P+ launch sites 6 it is upper
Surface is connected with emitter metal 1；It is characterized in that, the trench gate structure includes bottom Split Electrode 31, gate electrode 32, side
Face Split Electrode 33, gate dielectric layer 41, second dielectric layer 42, the 3rd dielectric layer 43, the 4th dielectric layer 44 and the 5th dielectric layer 45；
It is connected between the gate electrode 32 and side Split Electrode 33 by the 3rd dielectric layer 43；The gate electrode 32 passes through gate dielectric layer
41 are connected with the N+ launch sites 5 of trench gate structure one side and p-type base 7；The side Split Electrode 33 passes through second dielectric layer
42 are connected with the N+ launch sites 5 of trench gate structure opposite side and p-type base 7；The bottom Split Electrode 31 is located at gate electrode 32
With the lower section of side Split Electrode 33, and the upper surface depth of bottom Split Electrode 31 be less than N-type charge storage layer 8 junction depth,
The lower surface depth of bottom Split Electrode 31 is more than the junction depth of N-type charge storage layer 8；The upper surface of the bottom Split Electrode 31
With gate electrode 32, side Split Electrode 33 lower surface between be connected by the 4th dielectric layer 44；The bottom Split Electrode 31
Lower surface and side and N-type drift region 9 and N-type charge storage layer 8 between connected by the 5th dielectric layer 45；The bottom point
The width for splitting electrode 31 is more than second dielectric layer 42, side Split Electrode 33, the 3rd dielectric layer 43, gate electrode 32 and gate dielectric layer
The sum of 41 width, it is in inverted " t " font to make trench gate structure；The second dielectric layer 42, side Split Electrode 33 and part
The upper surface of three dielectric layers 43 is connected with emitter metal 1；The 3rd dielectric layer 43 of the gate dielectric layer 41, gate electrode 32 and part
Upper surface have first medium layer 2；The bottom Split Electrode 31, side Split Electrode 33 and 1 equipotential of emitter metal.
Further, the thickness of the 3rd dielectric layer 43, the 4th dielectric layer 44 and the 5th dielectric layer 45 is situated between more than grid
The thickness of matter layer 41 and second dielectric layer 42.
Further, the thickness of the gate dielectric layer 41 is more than the thickness of second dielectric layer 42.
Further, the bottom of the side Split Electrode 33 is extended to is connected with the upper surface of bottom Split Electrode 31.
Further, the both sides of the trench gate structure also have N+ layers 14, and the one side of the N+ layers 14 is deposited with N-type charge
Reservoir 8 connects, and the opposite side of N+ layers 14 and bottom are connected with trench gate structure, the upper surface of N+ layers 14 and the following table of p-type base 7
Face connects.
Further, the drift region structure is NPT structures or FS structures；The IGBT device uses semi-conducting material
Si, SiC, GaAs or GaN make.
The manufacturing method of double division trench gate charge storage type RC-IGBT, which is characterized in that comprise the following steps：
The first step：It chooses N-type and N-type drift region 9 of the monocrystalline silicon piece as device is lightly doped, the silicon wafer thickness of selection is 300
~600um, doping concentration 1013~1014A/cm3；Pass through ion implanting N-type impurity and making devices of annealing in silicon chip back side
N-type field stop layer 10, the thickness of the N-type field stop layer of formation is 15~30 microns, ion implantation energy for 1500keV~
2000keV, implantation dosage 1013~1014A/cm2, annealing temperature is 1200-1250 DEG C, and annealing time is 300~600 points
Clock；
Second step：It overturns and silicon chip is thinned to required thickness, groove is formed by photoetching, etching in silicon chip surface；
3rd step：At 1050 DEG C~1150 DEG C, O2Atmosphere under oxide layer is formed around groove；Then 750 DEG C~
Polysilicon is filled in deposit in the trench at 950 DEG C；Re-oxidation simultaneously etches away extra oxide layer；Form bottom Split Electrode 31
With the 5th dielectric layer 45, the bottom classification electrode 31 is located in the 5th dielectric layer 45；
4th step：2~6 microns of thick n-type doping layers are formed in silicon chip surface by extension；
5th step：One layer thin of pad oxide and silicon nitride layer are deposited in silicon chip surface, after making window by lithography, is carried out again
Groove silicon etching, etches groove above bottom electrode 31, and polysilicon surface, which aoxidizes the oxide layer to be formed, in the 3rd step to make
For the stop layer of this step silicon etching；After the completion of etching groove, by solution by the silicon nitride on surface and pad oxide rinsed clean；
The groove formed in the groove and second step that are formed in the step forms inverted " t " font groove；
6th step：By thermal oxide, wall grows oxide layer in the trench, and the oxidated layer thickness of formation is less than 120nm；
7th step：Using photoetching process, the oxide layer that left side wall is formed in groove in the 6th step is etched；The side on the right side of groove
Wall forms gate dielectric layer 41；The 4th dielectric layer 44 is formed in channel bottom；
8th step：By thermal oxide, wall regrows oxide layer in the trench, and the oxidated layer thickness of formation is less than 40nm；
Side wall forms the second gate dielectric layer 42 on the left of groove
9th step：Polysilicon is filled in deposit in the trench at 750 DEG C~950 DEG C；
Tenth step：Using photoetching process, the partial polysilicon of filling in groove in the 9th step is etched, is distinguished in groove both sides
Form gate electrode 32 and side Split Electrode 33；The gate electrode 32 is connected with gate dielectric layer 41, side Split Electrode 33 and
Second medium layer 42 connects；
11st step：It deposits, is filled out in the groove between the gate electrode 32 and side Split Electrode 33 that are formed in the tenth step
Filling medium forms the 3rd dielectric layer 43；
12nd step：Using photoetching process, the N-type charge storage layer 8 of ion implanting N-type impurity making devices is first passed through,
The N-type charge storage layer 8 is located at groove both sides；The energy of ion implanting be 200~500keV, implantation dosage 1013~
1014A/cm2；Then by ion implanting p type impurity and anneal and make p-type base 7, the energy of ion implanting for 60~
120keV, implantation dosage 1013~1014A/cm2, annealing temperature is 1100-1150 DEG C, and annealing time is 10~30 minutes；Institute
It states p-type base 7 and is located at 8 upper surface of N-type charge storage layer；The junction depth of the N-type charge storage layer 8 of formation is more than the depth of gate electrode 32
It spends and is less than the depth of bottom Split Electrode 31, the junction depth of the p-type base 7 of formation is less than the depth of gate electrode 32；
13rd step：Using photoetching process, pass through the N+ launch sites 5 of ion implanting N-type impurity making devices, ion implanting
Energy for 30~60keV, implantation dosage 1015~1016A/cm2；The N+ launch sites 5 are located at 7 upper surface of p-type base simultaneously
It is connected with groove；
14th step：Using photoetching process, by ion implanting p type impurity and the P+ launch sites 6 for making devices of annealing, from
The energy of son injection is 60~80keV, implantation dosage 1015~1016A/cm2, annealing temperature is 900 DEG C, and the time is 20~30
Minute；The P+ launch sites 6 are located at 7 upper surface of p-type base side by side with N+ launch sites 5；
15th step：In device surface dielectric layer deposited, and photoetching, etching form first medium layer 2；The first medium
Layer 2 is located at the upper surface of the 3rd dielectric layer 43 of part, gate electrode 32 and gate dielectric layer 41；
16th step：Metal is deposited, and photoetching, etching are in N+ launch sites 5 and 6 upper surface of P+ launch sites and second medium
Layer 42, the upper surface of the 3rd dielectric layer 43 of side Split Electrode 33 and part form collector electrode metal 1；
17th step：Silicon chip is overturn, silicon wafer thickness is thinned, p-type collecting zone 11 is formed in silicon chip back side implanting p-type impurity,
The p-type collecting zone 11 is located at 10 lower surface of N-type electric field trapping layer, and Implantation Energy is 40~60keV, implantation dosage 1012~
1013A/cm2；Photoetching again, by the N-type collecting zone 12 of ion implanting N-type impurity making devices, the energy of ion implanting is
40~60keV, implantation dosage 1014~1015A/cm2；Then in H2With N2Back side annealing, temperature are carried out under the atmosphere of mixing
For 400~450 DEG C, the time is 20~30 minutes；The N-type collecting zone 12 is set up in parallel with p-type collecting zone 11；
18th step：Back side deposit metal forms collector electrode metal 13.
Further, in the 3rd step, p-type base 7 can be respectively formed at twice by increasing lithography step, made close
The concentration and junction depth of the p-type base 7 of 32 one side of gate electrode are more than the concentration of the p-type base 7 by 33 one side of proximal side Split Electrode
And junction depth.
The present invention operation principle be：
For traditional RC-CSTBT devices as shown in Figure 1, in positive IGBT operating modes, in order to improve IGBT devices
The performance of part improves its reliability, it is necessary to reduce the switching loss of device under certain blocking voltage ability and reduce forward direction
Conduction voltage drop while the short-circuit safety operation area for improving device.The switching process of IGBT is exactly that grid capacitance is rushed, is discharged
Process, grid capacitance more favourable opposition, discharge time be longer.Thus, in the switching process of IGBT, grid capacitance, particularly grid
Pole-collector capacitance has important influence to the switching loss of device.In traditional trench gate charge storage as shown in Figure 1
In type RC-IGBT structures, in order to effectively shield higher-doped concentration and certain thickness N-type charge storage layer to breakdown voltage
Adverse effect obtain certain device it is pressure-resistant, it is necessary to using：1) deep trench gate depth makes the depth of trench gate be more than N-type electricity
The junction depth of lotus accumulation layer；2) small cellular width, highdensity trench MOS structure make the spacing between trench gate subtract as far as possible
It is small.However, deep trench gate depth and highdensity trench MOS structure both of which not only increases gate-emitter electricity
Hold, also increase grid-collector capacitance.In addition, for traditional trench gate charge memory type IGBT structure, gate oxide is
It is formed in the trench by a thermal oxide, in order to ensure that the thickness of the entire gate oxide of certain threshold voltage is smaller, by
It is inversely proportional in the thickness of mos capacitance size and oxide layer, small gate oxide in conventional trench gate charge memory type IGBT structure
Thickness greatly increases the grid capacitance of device.Simultaneously highdensity trench MOS structure add device saturation current it is close
Degree, makes the short-circuit safety operation area of device be deteriorated；In addition, small gate oxide thickness concentrates the electric field of channel bottom, make device
The reliability of part is poor.
As shown in Fig. 2,3 and 4, the present invention passes through the bottom of gate electrode in device trenches and lateral leadin and emitter etc.
Thick dielectric layer between double Split Electrodes of current potential and double Split Electrodes and gate electrode is not influencing IGBT device threshold voltage
In the case of opening:1) reduce the depth of gate electrode in groove, substantially reduce including grid-collector capacitance, grid-
Grid capacitance including emitter capacity；2) by the shielding action of double Split Electrodes, the coupling of grid and collector is shielded,
Grid-collector capacitance is converted into gate-emitter capacitance, grid-collector capacitance is substantially reduced, while is situated between by thickness
The effect of matter layer 43 and 44 makes to convert from grid-collector capacitance and increased gate-emitter capacitance is far smaller than due to side
The gate-emitter capacitance that face Split Electrode 33 is introduced and reduced, so as to substantially reduce including grid-collector capacitance, grid
Grid capacitance including pole-emitter capacity.Therefore, structure of the present invention substantially reduces the grid capacitance of device, particularly grid
Pole-collector capacitance improves the switching speed of device, reduces the switching loss of device.In addition, in certain groove MOS knot
The introducing of structure density downside Split Electrode 33 reduces the density of MOS raceway grooves, reduces the saturation current density of device, improves
The short-circuit safety operation area of device, improves reliability；In addition, the wide bottom Split Electrode of channel bottom further enhances
The carrier concentration enhancement effect of emitter terminal further improves the carrier concentration profile of entire N-type drift region, further
The compromise of forward conduction voltage drop and switching loss is improved, improves the performance of device；Further, since 33 He of side Split Electrode
Bottom Split Electrode 31 and emitter equipotential in IGBT device opens dynamic process, divide electricity by dielectric layer and side
The semiconductor surface that pole 33 and bottom Split Electrode 31 contact will not form transoid (floating p-type base 72) and electron accumulation (N-type
Charge storage layer 8 and N-type drift region 9), therefore negative differential capacity effect will not be formed, avoid the electricity opened in dynamic process
Stream, voltage oscillation and EMI problems, improve reliability；Meanwhile pass through the thick dielectric layer around the Split Electrode of bottom and wide width
Degree further effectively shields N-type charge storage in the case of certain device trench depth and trench MOS structure density
The thin dielectric layer influence pressure-resistant to device at layer and gate electrode and side Split Electrode, particularly effectively shield in order to
The dielectric layer shadow pressure-resistant to device at the very thin side Split Electrode for obtaining small parasitic MOS structure threshold voltage and setting
It rings, improves the breakdown voltage of device, improve the concentration of channel bottom electric field, further improve the reliability of device.This
The Composite Double division groove structure that invention provides, the depth of trench gate electrode 32 are more than the depth and trench gate electricity of p-type base 7
The depth of pole 32 be less than N-type charge storage layer 8 depth, this aspect in the case where not influencing IGBT device and opening as far as possible
Reduce grid capacitance, particularly grid-collector capacitance, on the other hand certain thickness high concentration N-type charge storage layer 8
Presence compensate for since the introducing with the equipotential bottom Split Electrode of emitter causes carrier near the Split Electrode of bottom
The decline of concentration avoids device caused by increased dramatically the forward conduction voltage drop of device due to the introducing of bottom Split Electrode
Part characteristic is deteriorated.In backward dioded afterflow operating mode, by adjusting the concentration and thickness and dielectric layer of p-type base 7
42 thickness and material makes at the Split Electrode of side the threshold voltage of parasitic MOS structure be less than 0.1V, by with emitter phase
The effect of side Split Electrode even, makes the MOS raceway grooves at the Split Electrode of side be opened less than 0.1V, makes reversed two pole of afterflow
Pipe works in the how sub- device model of MOS control diodes, shields by p-type base 7 and N-type charge storage layer 8/N- drift regions
The influence of the 9 PN junction built-in potentials formed, makes reversed fly-wheel diode have low diode conduction voltage drop；It is simultaneously because mostly sub
Conduction need not extract the excess carriers in N- drift regions 9 in reversely restoring process, improve fly-wheel diode
Reverse recovery characteristic, such as reverse recovery time is short, reverse recovery charge is small.In addition, production method provided by the invention is not
It needs to increase additional processing step, it is compatible with traditional trench gate charge storage type RC-IGBT production methods.
Beneficial effects of the present invention are to be greatly reduced to exist including grid-collector capacitance, gate-emitter capacitance
Interior grid capacitance；Improve the carrier concentration profile of entire N-type drift region；The switching speed of device is improved, reduces device
The switching loss of part reduces the saturation current density of device, improves the short-circuit safety operation area of device, improves reliable
Property, the concentration of channel bottom electric field is improved, is avoided since the introducing of bottom Split Electrode makes the forward conduction voltage drop of device
Poor device properties caused by increased dramatically make reversed fly-wheel diode have low diode conduction voltage drop, improve continuous
The reverse recovery characteristic of diode is flowed, such as reverse recovery time is short, reverse recovery charge is small；In addition, system provided by the invention
Additional processing step need not be increased by making method, compatible with traditional trench gate charge storage type RC-IGBT production methods.
Description of the drawings
Fig. 1 is traditional RC-CSTBT device cellular structure diagrams；
In Fig. 1,1 is emitter metal, and 2 be dielectric layer, and 3 be gate electrode, and 4 be gate dielectric layer, and 5 be N+ launch sites, and 6 be P+
Launch site, 7 be p-type base, and 8 be N-type charge storage layer, and 9 be N- drift regions, and 10 be N-type electric field trapping layer, and 11 be p-type current collection
Area, 12 be N-type collecting zone, and 13 be collector electrode metal；
Fig. 2 is double division trench gate charge storage type RC-IGBT device cellular structure diagrams of embodiment 1；
Fig. 3 is double division trench gate charge storage type RC-IGBT device cellular structure diagrams of embodiment 2；
Fig. 4 is double division trench gate charge storage type RC-IGBT device cellular structure diagrams of embodiment 3；
Fig. 2 is into Fig. 3, and 1 is emitter metal, and 2 be dielectric layer, and 31 be bottom Split Electrode, and 32 be gate electrode, and 33 be side
Face Split Electrode, 41 be gate dielectric layer, and 42 be dielectric layer, and 43 be dielectric layer, and 44 be dielectric layer, and 45 be dielectric layer, and 5 emit for N+
Area, 6 be P+ launch sites, and 7 be p-type base, and 8 be N-type charge storage layer, and 9 be N- drift regions, and 10 be N-type electric field trapping layer, and 11 are
P-type collecting zone, 12 be N-type collecting zone, and 13 be collector electrode metal, and 14 be N+ layers；
Fig. 5 is that etching forms the device architecture schematic diagram after groove for the first time in the manufacturing method of the present invention；
Fig. 6 is that the device architecture schematic diagram after the Split Electrode of bottom is formed in the manufacturing method of the present invention；
Fig. 7 is the device architecture schematic diagram after extension N- layers in the manufacturing method of the present invention；
Fig. 8 is that second of etching forms the device architecture schematic diagram after groove in the manufacturing method of the present invention；
Fig. 9 is that the device architecture schematic diagram after gate dielectric layer is formed in the manufacturing method of the present invention；
Figure 10 is that the device architecture schematic diagram after gate electrode and side Split Electrode is formed in the manufacturing method of the present invention；
Figure 11 is the device architecture schematic diagram after complete Overall Steps in the manufacturing method of the present invention.
Specific embodiment
With reference to the accompanying drawings and examples, detailed description of the present invention technical solution：
Embodiment 1
The double division trench gate charge storage type RC-IGBT of one kind of this example, structure cell as shown in Fig. 2, including：Back
Collector electrode metal 13, on back collector electrode metal 13 and coupled p-type collecting zone 11 and N-type collecting zone 12, position
On p-type collecting zone 11 and N-type collecting zone 12 and coupled N-type field stop layer 10, on N-type field stop layer 10
And coupled N- drift regions 9；Among 9 top of N- drift regions and coupled Composite Double divides groove structure；Position
In 9 top both sides of N- drift regions and coupled N-type charge storage layer 8, the side wall of the N-type charge storage layer 8 with it is compound
The side wall of double division groove structures is connected, positioned at 8 top of N-type charge storage layer and in its connected p-type base 7, the p-type base
The side wall in area 7 is connected with the side wall of Composite Double division groove structure；Positioned at 7 top of p-type base and coupled independent of one another
N+ launch sites and P+ launch sites, the side walls of the N+ launch sites be connected with the side wall of Composite Double division groove structure；Positioned at N+
Launch site and the emitter metal 1 of P+ launch sites upper surface；Dielectric layer 2 positioned at Composite Double division groove structure top；It is special
Sign is：The Composite Double division groove structure includes understructure and superstructure；The understructure includes thick dielectric layer
45 and the bottom Split Electrode 31 that is arranged in thick dielectric layer 45；The superstructure includes trench gate electrode 32, side division
Electrode 33, dielectric layer 41, dielectric layer 42, dielectric layer 43 and dielectric layer 44, between the gate electrode 32 and side Split Electrode 33
It is dielectric layer 43, is dielectric layer 44 between the gate electrode 32 and side Split Electrode 33 and bottom Split Electrode 31, the ditch
Slot gate electrode 32 is connected by dielectric layer 41 with N+ launch sites 5 and p-type base 7, and the side Split Electrode 33 passes through dielectric layer
42 are connected with N+ launch sites 5 and p-type base 7；The width of the understructure is more than the width of the superstructure；The groove
The depth of gate electrode 32 is more than the junction depth of p-type base 7, and the depth of the trench gate electrode 32 is less than the knot of N-type charge storage layer 8
Deep, the width of the trench gate electrode 32 and side Split Electrode 33 is more than the thickness of dielectric layer 45 and dielectric layer 44；The side
The depth of face Split Electrode 33 is more than the junction depth of p-type base 7, and the depth of the side Split Electrode 33 is not less than trench gate electrode
32 depth；The depth of 31 upper surface of bottom Split Electrode is less than the junction depth of N-type charge storage layer 8, the bottom division
The depth of 31 lower surface of electrode is more than the junction depth of N-type charge storage layer 8；The thickness of the dielectric layer 45,43 and 44 is more than medium
The thickness of layer 41 and 42, the thickness of the dielectric layer 42 are less than the thickness of dielectric layer 41；The side Split Electrode 33 and transmitting
Pole metal 1 is connected on surface, the bottom Split Electrode 31 and 1 equipotential of emitter metal.The trench gate electrode formed
32 depth is more than 0.1~0.2 micron of the junction depth of p-type base 7, and the thickness of the N-type charge storage layer 8 of formation is micro- for 1~2
Rice；The depth of 31 upper surface of bottom Split Electrode formed is less than 0.5~1.5 micron of the junction depth of N-type charge storage layer 8,
The depth of lower surface is more than 0.5~1 micron of the junction depth of N-type charge storage layer 8；The thickness of the dielectric layer 41 formed is less than
120 nanometers, the thickness of the dielectric layer 42 of formation is less than 40 nanometers, and the width of the dielectric layer 43 of formation is micro- for 0.5~1
Rice, the thickness of the dielectric layer 44 and 45 of formation is 0.2~0.5 micron, the Composite Double division groove structure of formation
Understructure is each 0.2~1 micron wider in the right and left than superstructure；By adjusting the concentration and thickness of p-type base 7 and Jie
The thickness and material of matter layer 42 make the threshold voltage of MOS structure parasitic at the Split Electrode of side be less than 0.1V.
Embodiment 2
The double division trench gate charge storage type RC-IGBT of one kind of this example, structure cell as shown in figure 3, with embodiment 1
Unlike, the lower part of side Split Electrode 33 extends directly into the upper surface of bottom Split Electrode 31, makes side Split Electrode
33 are connected directly the grid capacitance for further reducing device with bottom Split Electrode 31.
Embodiment 3
The double division trench gate charge storage type RC-IGBT of one kind of this example, structure cell as shown in figure 3, with embodiment 1
Unlike, the subregion between the understructure of the composite trench structure and p-type base 7 also has one layer N+ layers
14, the concentration of the N+ layers 14 is more than the concentration of N-type charge storage layer 8 and its side wall is connected with composite trench structure, is formed
The N+ layers 14 further reduce the resistance in region between the composite trench structure bottom structure and p-type base 7, into one
Step improves the carrier injection enhancement effect of emitter terminal, can obtain better device forward conduction voltage drop and switching loss
Compromise.
The specific embodiment of present invention process production method is with double division trench gate charge storages of 600V voltage class
It is illustrated exemplified by type RC-IGBT, concrete technology production method is as follows：
The first step：It is 2 × 10 to choose doping concentration14A/cm3, thickness be 300~600 microns be lightly doped FZ silicon chips use
To form the N- drift regions 9 of device；It is prevented in silicon chip back side by the N-type field of ion implanting N-type impurity and making devices of annealing
Layer 10, the thickness of the N-type field stop layer of formation is 15~20 microns, and ion implantation energy is 1500keV~2000keV, is injected
Dosage is 5 × 1013A/cm2, annealing temperature is 1200 DEG C, and annealing time is 400 minutes；
Second step：It overturns and the thickness of silicon chip to 90~95 microns is thinned, formed by photoetching, etching in silicon chip surface
The groove of even distribution, gash depth are 0.5~2 micron, and width is 2~3 microns, and the spacing between groove is micro- for 0.5~1.5
Rice；
3rd step：At 1050 DEG C~1150 DEG C, O2Atmosphere under thickness is formed around groove is 0.2~0.5 micron
Thick oxide layer；Then accumulation fills polysilicon in the trench at 850 DEG C；Re-oxidation simultaneously etches away extra oxide layer,
Polysilicon surface forms 0.2~0.3 micron of thick oxide layer；
4th step：It is 3~5 microns to form thickness in silicon chip surface by extension, and doping concentration is 2 × 1014A/cm3N
Type doped layer；
5th step：One layer thin of pad oxide and silicon nitride layer are deposited in silicon chip surface, after making window by lithography, is carried out again
Groove (trench) silicon etching etches groove, and the 3rd step polysilicon surface, which aoxidizes the oxide layer to be formed, this step silicon to be used as to carve
The stop layer of erosion；After the completion of etching groove, by solution by the silicon nitride on surface and pad oxide rinsed clean；What this step was formed
Groove center line is overlapped with the groove center line that second step is formed, and the groove width of formation is 0.6~1.5 micron；
6th step：By thermal oxide, wall grows the thin oxide layer of high quality in the trench, and the oxidated layer thickness of formation is less than
60nm；
7th step：Photoetching etches the oxide layer that left side wall is formed in groove in the 6th step；
8th step：By thermal oxide, wall regrows the thin oxide layer of high quality, the oxidated layer thickness of formation in the trench
Less than 20nm；
9th step：Polysilicon is filled in deposit in the trench at 850 DEG C；
Tenth step：Photoetching etches the partial polysilicon of filling in groove in the 9th step, forms gate electrode 32 and side division
Electrode 33；
11st step：Deposit is filled in groove between the gate electrode 32 and side Split Electrode 33 that are formed in the tenth step and is situated between
Matter forms dielectric layer 43；
12nd step：Photoetching first passes through the N-type charge storage layer 8 of ion implanting N-type impurity making devices, ion implanting
Energy for 500keV, implantation dosage is 5 × 1013A/cm2；Then ion implanting p type impurity and making devices of annealing are passed through
P-type base 7, the energy of ion implanting is 120keV, and implantation dosage is 1 × 1014A/cm2, annealing temperature is 1100-1150 DEG C,
Annealing time is 15~30 minutes；The junction depth of the p-type base 7 of formation is formed than 0.1~0.2 micron of the depth as shallow of gate electrode 32
The N-type charge storage layer 8 junction depth be more than gate electrode 32 depth and less than bottom Split Electrode 31 depth, formation
The thickness of N-type charge storage layer 8 is 1~2 micron；
13rd step：Photoetching, by the N+ launch sites of ion implanting N-type impurity making devices, the energy of ion implanting is
40keV, implantation dosage are 1 × 1015A/cm2；
14th step：Photoetching, by ion implanting p type impurity and the P+ launch sites for making devices of annealing, ion implanting
Energy is 60keV, and implantation dosage is 5 × 1015A/cm2, annealing temperature is 900 DEG C, and the time is 30 minutes；
15th step：Dielectric layer deposited, and photoetching, etching form dielectric layer 2；
16th step：Metal is deposited, and photoetching, etching form metal collector 1；
17th step：Silicon chip is overturn, silicon wafer thickness, photoetching and in the P of silicon chip back side implanting p-type impurity making devices is thinned
Type collecting zone 11, Implantation Energy 60keV, implantation dosage are 5 × 1012A/cm2；Photoetching again, it is miscellaneous by ion implanting N-type
The N-type collecting zone 12 of matter making devices, the energy of ion implanting is 60keV, and implantation dosage is 2 × 1014A/cm2；Then in H2
With N2Back side annealing is carried out under the atmosphere of mixing, temperature is 450 DEG C, and the time is 30 minutes；
18th step：Back side deposit metal forms metal collector 13.
It is prepared into double division trench gate charge storage type RC-IGBT.
Further, the preparation of first step N-type field stop layer 10 can be in the Facad structure system of device in the processing step
It is standby to complete to carry out afterwards；Or the two-layer epitaxial material with N-type field stop layer 10 and N- drift regions 9 can be directly selected as technique
The silicon sheet material of starting；
Further, the preparation of first step N-type field stop layer 10 can omit in the processing step；
Further, a step etching technics, etching removal side Split Electrode 33 can be increased before the 9th step polycrystalline silicon deposit
Under oxide layer, that is, form device architecture as shown in Figure 3；
Further, formed before the 6th step oxidation technology by the ion implanting N-type impurity with angle highly doped dense
N+ layers 14 of degree or in the forming process of the 12nd step N-type charge storage layer 8, passing through increases a step photoetching and ion implanting work
Skill forms the N+ layers 14 of high-dopant concentration, that is, forms device architecture as shown in Figure 4；
Further, the 12nd step in the processing step, can be by increasing lithography step at twice in groove both sides point
Not Xing Cheng p-type base 7, concentration and junction depth close to the p-type base 7 of 32 one side of gate electrode is made to be more than by proximal side Split Electrode 33
The concentration and junction depth of the p-type base 7 of one side；
Further, the material of the dielectric layer 41,42,43,44 and 45 can be the same or different.
Claims (5)
1. pair division trench gate charge storage type RC-IGBT, including be cascading from bottom to up collector electrode metal (13),
P-type collector area (11), N-type electric field trapping layer (10), N-type drift region (9) and emitter metal (1)；It further includes and p-type current collection
The N-type collector area (12) that polar region (11) is set up in parallel；There is N+ launch sites (5), P+ launch sites in the N-type drift region (9)
(6), p-type base (7), N-type charge storage layer (8) and trench gate structure；The trench gate structure vertically sequentially passes through N
It is extended to after+launch site (5), p-type base (7) and N-type charge storage layer (8) in N-type drift region；The p-type base (7) is located at
N-type charge storage layer (8) upper surface, N+ launch sites (5) and P+ launch sites (6) are located at p-type base (7) upper surface side by side；N+ is sent out
The upper surface for penetrating area (5) and P+ launch sites (6) is connected with emitter metal (1)；It is characterized in that, the trench gate structure includes
Bottom Split Electrode (31), gate electrode (32), side Split Electrode (33), gate dielectric layer (41), second dielectric layer (42), the 3rd
Dielectric layer (43), the 4th dielectric layer (44) and the 5th dielectric layer (45)；The gate electrode (32) and side Split Electrode (33) it
Between pass through the 3rd dielectric layer (43) connect；The gate electrode (32) is sent out by gate dielectric layer (41) and the N+ of trench gate structure one side
Penetrate area (5) and p-type base (7) connection；The side Split Electrode (33) is another by second dielectric layer (42) and trench gate structure
The N+ launch sites (5) of one side and p-type base (7) connection；The bottom Split Electrode (31) is located at gate electrode (32) and side point
The lower section of electrode (33) is split, and the upper surface depth of bottom Split Electrode (31) is less than the junction depth of N-type charge storage layer (8), bottom
The lower surface depth of portion's Split Electrode (31) is more than the junction depth of N-type charge storage layer (8)；The bottom Split Electrode (31) it is upper
Surface and gate electrode (32), side Split Electrode (33) lower surface between be connected by the 4th dielectric layer (44)；The bottom
Pass through the 5th dielectric layer between the lower surface and side of Split Electrode (31) and N-type drift region (9) and N-type charge storage layer (8)
(45) connect；The width of the bottom Split Electrode (31) is more than second dielectric layer (42), side Split Electrode (33), the 3rd Jie
The sum of width of matter layer (43), gate electrode (32) and gate dielectric layer (41), it is in inverted " t " font to make trench gate structure；Described second
The upper surface of the 3rd dielectric layer (43) of dielectric layer (42), side Split Electrode (33) and part is connected with emitter metal (1)；Institute
The upper surface for stating the 3rd dielectric layer (43) of gate dielectric layer (41), gate electrode (32) and part has first medium layer (2)；The bottom
Portion's Split Electrode (31), side Split Electrode (33) and emitter metal (1) equipotential.
2. double division trench gate charge storage type RC-IGBT according to claim 1, which is characterized in that the described 3rd is situated between
The thickness of matter layer (43), the 4th dielectric layer (44) and the 5th dielectric layer (45) is all higher than the thickness of gate dielectric layer (41)；It is described
The thickness of 3rd dielectric layer (43), the 4th dielectric layer (44) and the 5th dielectric layer (45) is all higher than the thickness of second dielectric layer (42)
Degree；The thickness of the gate dielectric layer (41) is more than the thickness of second dielectric layer (42).
3. double division trench gate charge storage type RC-IGBT according to claim 1, which is characterized in that the trench gate
The both sides of structure also have N+ layers (14), and the one side of N+ layers described (14) is connected with N-type charge storage layer (8), N+ layers (14)
Opposite side and bottom are connected with trench gate structure, and the upper surface of N+ layers (14) is connected with the lower surface of p-type base (7).
4. the manufacturing method of couple division trench gate charge storage type RC-IGBT, which is characterized in that comprise the following steps：
The first step：It chooses N-type and is lightly doped N-type drift region (9) of the monocrystalline silicon piece as device, the silicon wafer thickness of selection is 300~
600um, doping concentration 1013~1014A/cm3；Pass through the N of ion implanting N-type impurity and making devices of annealing in silicon chip back side
Type field stop layer (10), the thickness of the N-type field stop layer of formation are 15~30 microns, ion implantation energy for 1500keV~
2000keV, implantation dosage 1013~1014A/cm2, annealing temperature is 1200-1250 DEG C, and annealing time is 300~600 points
Clock；
Second step：It overturns and silicon chip is thinned to required thickness, groove is formed by photoetching, etching in silicon chip surface；
3rd step：At 1050 DEG C~1150 DEG C, O2Atmosphere under oxide layer is formed around groove；Then at 750 DEG C~950 DEG C
Under in the trench deposit filling polysilicon；Re-oxidation simultaneously etches away extra oxide layer；Formed bottom Split Electrode (31) and
5th dielectric layer (45), the bottom Split Electrode (31) are located in the 5th dielectric layer (45)；
4th step：2~6 microns of thick n-type doping layers are formed in silicon chip surface by extension；
5th step：One layer thin of pad oxide and silicon nitride layer are deposited in silicon chip surface, after making window by lithography, carries out groove again
Silicon etching, etches groove above Split Electrode (31) in bottom, in the 3rd step polysilicon surface aoxidize the oxide layer to be formed can
Stop layer as this step silicon etching；After the completion of etching groove, the silicon nitride on surface and pad oxide are rinsed by solution and done
Only；The groove formed in the groove and second step that are formed in the step forms inverted " t " font groove；
6th step：By thermal oxide, wall grows oxide layer in the trench, and the oxidated layer thickness of formation is less than 120nm；
7th step：Using photoetching process, the oxide layer that left side wall is formed in groove in the 6th step is etched；In groove right sidewall shape
Into gate dielectric layer (41)；The 4th dielectric layer (44) is formed in channel bottom；
8th step：By thermal oxide, wall regrows oxide layer in the trench, and the oxidated layer thickness of formation is less than 40nm；In groove
Left side side wall forms second dielectric layer (42)；
9th step：Polysilicon is filled in deposit in the trench at 750 DEG C~950 DEG C；
Tenth step：Using photoetching process, the partial polysilicon of filling in groove in the 9th step is etched, is respectively formed in groove both sides
Gate electrode (32) and side Split Electrode (33)；The gate electrode (32) is connected with gate dielectric layer (41), side Split Electrode
(33) it is connected with second dielectric layer (42)；
11st step：It deposits, is filled out in the groove between the gate electrode (32) and side Split Electrode (33) that are formed in the tenth step
Filling medium forms the 3rd dielectric layer (43)；
12nd step：Using photoetching process, the N-type charge storage layer (8) of ion implanting N-type impurity making devices, institute are first passed through
It states N-type charge storage layer (8) and is located at groove both sides；The energy of ion implanting be 200~500keV, implantation dosage 1013~
1014A/cm2；Then by ion implanting p type impurity and anneal and make p-type base (7), the energy of ion implanting for 60~
120keV, implantation dosage 1013~1014A/cm2, annealing temperature is 1100-1150 DEG C, and annealing time is 10~30 minutes；Institute
It states p-type base (7) and is located at N-type charge storage layer (8) upper surface；The junction depth of the N-type charge storage layer (8) of formation is more than gate electrode
(32) depth and less than the depth of bottom Split Electrode (31), the junction depth of the p-type base (7) of formation is less than gate electrode (32)
Depth；
13rd step：Using photoetching process, by the N+ launch sites (5) of ion implanting N-type impurity making devices, ion implanting
Energy be 30~60keV, implantation dosage 1015~1016A/cm2；The N+ launch sites (5) are located at p-type base (7) upper surface
And it is connected with groove；
14th step：Using photoetching process, pass through ion implanting p type impurity and the P+ launch sites (6) for making devices of annealing, ion
The energy of injection be 60~80keV, implantation dosage 1015~1016A/cm2, annealing temperature is 900 DEG C, and the time is 20~30 points
Clock；The P+ launch sites (6) are located at p-type base (7) upper surface side by side with N+ launch sites (5)；
15th step：In device surface dielectric layer deposited, and photoetching, etching form first medium layer (2)；The first medium layer
(2) it is located at the upper surface of the 3rd dielectric layer (43) of part, gate electrode (32) and gate dielectric layer (41)；
16th step：Metal is deposited, and photoetching, etching are in N+ launch sites (5) and P+ launch sites (6) upper surface and second medium
Layer (42), the upper surface of the 3rd dielectric layer (43) of side Split Electrode (33) and part form collector electrode metal (1)；
17th step：Silicon chip is overturn, silicon wafer thickness is thinned, p-type collecting zone (11), institute are formed in silicon chip back side implanting p-type impurity
It states p-type collecting zone (11) and is located at N-type electric field trapping layer (10) lower surface, Implantation Energy is 40~60keV, implantation dosage 1012
~1013A/cm2；Photoetching again passes through the N-type collecting zone (12) of ion implanting N-type impurity making devices, the energy of ion implanting
It measures as 40~60keV, implantation dosage 1014~1015A/cm2；Then in H2With N2Back side annealing is carried out under the atmosphere of mixing,
Temperature is 400~450 DEG C, and the time is 20~30 minutes；The N-type collecting zone (12) is set up in parallel with p-type collecting zone (11)；
18th step：Back side deposit metal forms collector electrode metal (13).
5. the manufacturing method of double division trench gate charge storage type RC-IGBT according to claim 4, which is characterized in that
In 3rd step, p-type base (7) can be respectively formed at twice by increasing lithography step, make close to gate electrode (32) one side
P-type base (7) concentration and junction depth be more than by proximal side Split Electrode (33) one side p-type base (7) concentration and junction depth.
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| JP7204544B2 (en) * | 2019-03-14 | 2023-01-16 | 株式会社東芝 | semiconductor equipment |
| CN110504260B (en) * | 2019-08-29 | 2022-11-04 | 电子科技大学 | Transverse groove type IGBT with self-bias PMOS and preparation method thereof |
| CN112331716B (en) * | 2020-09-27 | 2022-10-28 | 广东美的白色家电技术创新中心有限公司 | Semiconductor device, manufacturing method thereof and household appliance |
| CN113451400A (en) * | 2021-06-28 | 2021-09-28 | 宁波达新半导体有限公司 | Trench gate reverse conducting type IGBT device |
| CN113838916B (en) * | 2021-09-23 | 2023-05-26 | 电子科技大学 | Separation gate CSTBT with PMOS current clamping function and manufacturing method thereof |
| JP2024044260A (en) * | 2022-09-21 | 2024-04-02 | 株式会社東芝 | semiconductor equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840919A (en) * | 2008-12-23 | 2010-09-22 | 电力集成公司 | Vts insulated gate bipolar transistor |
| CN103972287A (en) * | 2013-01-28 | 2014-08-06 | 株式会社东芝 | Semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2013115225A (en) * | 2011-11-29 | 2013-06-10 | Toshiba Corp | Power semiconductor device and method of manufacturing the same |
| JP2014027182A (en) * | 2012-07-27 | 2014-02-06 | Toshiba Corp | Semiconductor device |
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