CN107768435A - A kind of two-way IGBT and its manufacture method - Google Patents
A kind of two-way IGBT and its manufacture method Download PDFInfo
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
A kind of two-way IGBT and its manufacture method, belong to power semiconductor device technology field.The present invention in conventional trench gate structure by introducing and the equipotential Split Electrode of surface metal and the thick dielectric layer positioned at Split Electrode the week side of boss, and introduce floating PXing Ti areas in the side of division trench gate structure, in the case where not influenceing IGBT device threshold voltage and opening, IGBT structure symmetrically forward and reverse conducting and turn-off characteristic are realized；The adverse effect that Miller effect is brought is improved, reduces driving power consumption；Avoid electric current, voltage oscillation and the EMI problems in device unlatching dynamic process；Improve the short-circuit safety operation area of device；Grid capacitance is reduced, improves the switching speed of device, reduces the switching loss of device；The concentration of channel bottom electric field is improved, improves the breakdown voltage of device；The carrier enhancement effect of emitter terminal is improved, improves the carrier concentration profile of whole N-type drift region, improves the compromise between forward conduction voltage drop and turn-off power loss.
Description
Technical field
The invention belongs to power semiconductor device technology field, is related to insulated gate bipolar transistor (IGBT), specifically relates to
And a kind of two-way IGBT and its manufacture method.
Background technology
Insulated gate bipolar transistor (IGBT) insulated type FET (MOSFET) and bipolar junction transistor (BJT) are multiple
The novel power transistor formed is closed, the MOSFET of bipolar junction transistor driving can be equivalent to.IGBT is mixed with MOSFET
The working mechanism of structure and bipolar junction transistor, both with MOSFET is easy to driving, that input impedance is low, switching speed is fast is excellent
Point, there is the advantages of BJT on state current density is big, conduction voltage drop is low, loss is small, stability is good again, so, compare IGCT etc.
For current control device, have in terms of the simplification of controllability, safety operation area, switching loss and drive circuit obvious excellent
Gesture, it is set to be significantly improved in the application to the performance of power electronic system.At present, IGBT has turned into modern power electronic electricity
One of core electron component in road, it is widely used in the every field such as traffic, communication, household electrical appliance and Aero-Space.
Transformation of electrical energy is a basic step of many applied power electronics, is one of basic function of electric device, root
According to the difference of load request, electric device can complete AC-to DC (AC-DC), and direct current to exchange (DC-AC), direct current is to directly
Flow the conversion of (DC-DC) and AC to AC (AC-AC).AC-AC conversion can be AC-DC-AC modes using indirect conversion,
Can also be by the way of directly conversion be AC-AC., it is necessary to there is big capacitance in traditional AC-DC-AC indirect conversion systems
Electric capacity (voltage-type conversion) or the connection inductance (current mode conversion) of inductance value greatly are connected by the relatively independent transformation system of two parts
It is connected, this kind of system bulk is big, and cost is high.In addition, the service life of electric capacity and inductance is far below power device, this has a strong impact on
The reliability of system and service life.AC-AC direct converting systems avoid in traditional AC-DC-AC systems connect electric capacity or
The use of inductance, but require that power switch has two-way switch ability.Thus, the exploitation of two-way switch is always that alternating electromotive force becomes
The study hotspot of changing device, the two-way switch of early stage is using the IGCT for being equipped with external forced converter circuit.Two-way opened at present
Close using most commonly used semiconductor devices is IGBT, because traditional IGBT only has one-way conduction and the work(that unidirectionally blocks
Can, the constituted mode for having the IGBT two-way switch of two-way admittance two-way blocking-up function main has：Diode bridge, common collector
Formula and common emitter formula.Later reverse blocking IGBT (RB-IGBT) occurs, and such devices have the larger energy for bearing backward voltage
Power so that two-way switch can be simplified to simple inverse parallel structure, eliminate two fast recovery diodes.But open above
Pass scheme belongs to packet type switch, it is necessary to which a large amount of power chips, add system cost, and each chip chamber of internal system needs in addition
Want a large amount of lines, more complicated combination to enhance the ghost effect of internal system, influence system reliability.
In this context, in order to solve the above problems and realize the integrated of product, industry by using bonding techniques or
The method of person's dual surface lithography carries out the development of two-way igbt chip.With silicon-silicon bond close technology development, in recent years it has been proposed that
Back-to-back be bonded together of two identical trench MOS structures successfully realized into tool as shown in Figure 1 in one chip
There are two-way admittance and the two-way IGBT of two-way blocking-up function (Bi-directional IGBT), two-way IGBT generation is greatly
The cost of device is reduced, reduces the stray parameter of circuit.IGBT unidirectional compared to tradition, by controlling front and back grid electricity
Pressure, the two-way IGBT can realize symmetrical forward and reverse IGBT conductings and turn-off characteristic.In addition, the structure is in p-type base 5 and N-
Between drift region 9 and p-type base 25 and N-One layer is symmetrically employed between drift region 9 and compares N-The doping concentration of drift region 9 is high
Positive N-type layer 6 and back side N-type layer 26, are on the one hand thinned N- drift region thickness compared with the two-way IGBT structure of NPT types, reduce
Drift zone resistance, and then reduce forward conduction voltage drop and improve switching speed, on the other hand should when either direction works
Two-way IGBT is the IGBT structure for storing layer and electric field trapping layer with carrier, significantly improves the performance of device.For
Structure shown in Fig. 1, when IGBT forward or backwards works, positive N-type layer 6 and back side N-type layer 26 store layer as carrier,
So that IGBT device is greatly improved close to the carrier concentration profile of emitter terminal, the electricity of N-type drift region is improved
Modulation is led, improves the carrier concentration profile of whole N-type drift region, IGBT is obtained low forward conduction voltage drop and improvement
Forward conduction voltage drop and turn-off power loss compromise.However, for this two-way IGBT structure, due to the positive He of N-type layer 6
The presence of back side N-type layer 26, the breakdown voltage of device can be significantly reduced when IGBT forward or backwards works.In order to effectively shield
The adverse effect of N-type charge storage layer, the higher device of acquisition is pressure-resistant, mainly uses the following two kinds mode：
(1) trench gate depth deep, the depth of trench gate is generally made to be more than the junction depth of N-type charge storage layer；
(2) cellular width small, that is, improving MOS structure gully density makes trench gate spacing as small as possible；
Mode (1) can increase gate-emitter electric capacity and grid-collector capacitance while implementation, and IGBT switch
It is exactly the process that charge/discharge is carried out to grid capacitance on process nature, so, when the increase of grid capacitance can cause charge/discharge
Between increase, in turn result in switching speed reduction.Thus, deep trench gate depth will reduce devices switch speed, increase device
Switching loss, have influence on the compromise characteristic of break-over of device pressure drop and switching loss；And the implementation of mode (2) is on the one hand by enhancer
The grid capacitance of part, cause devices switch speed to reduce, switching loss increase, influence the folding of break-over of device pressure drop and switching loss
Middle characteristic, the big gully density of another aspect will also increase the saturation current density of device, and become shorted devices safety operation area
Difference.In addition, for two-way IGBT structure as shown in Figure 1, gate oxide is formed in the trench by a thermal oxide, in order to
Ensure that the thickness of the whole gate oxide of certain threshold voltage is smaller, because the thickness of mos capacitance size and oxide layer is into anti-
Than small gate oxide thickness greatly increases the grid capacitance of device in the two-way IGBT structure of tradition.In addition, small grid oxygen
Changing thickness degree concentrates the electric field of channel bottom, makes the reliability of device poor.
The content of the invention
The technical problems to be solved by the invention are：There is provided a kind of excellent combination property, reliability high two-way IGBT
Device and its manufacture method.
To achieve these goals, technical scheme is specific as follows：
On the one hand the present invention provides a kind of two-way IGBT, and its structure cell includes：It is symmetricly set on the front of N-type drift region 10
With the N-channel MOS structure at the back side；Positive MOS structure includes：Front side emitter pole metal 1, the first front dielectric layer 22, second are just
Face dielectric layer 20, front division trench gate structure, positive P+ launch sites 3, positive N+ launch sites 4, positive p-type base 5 and positive N
Type charge storage layer 6 and positive PXing Ti areas 9；Back side MOS structure includes：Back side emitter pole metal 21, the first back side dielectric layer
222nd, the second back side dielectric layer 220, back side division trench gate structure, back side P+ launch sites 23, back side N+ launch sites 24, back side P
Type base 25 and back side N-type charge storage layer 26 and back side PXing Ti areas 29；It is characterized in that：
Front division trench gate structure is located at the upper surface centre position of N-type drift region 10, front division trench gate structure
There is positive N+ launch sites 3, positive P+ launch sites 4, positive p-type base 5 and positive N-type electric charge in the N-type drift region 10 of side
Accumulation layer 6；Positive N+ launch sites 3 and positive P+ launch sites 4 contact with each other and are located side by side at the lower section of front side emitter pole metal 1 simultaneously
It is connected with front side emitter pole metal 1；Positive p-type base 5 be located at the lower section of positive N+ launch sites 3 and positive P+ launch sites 4 and with
The two is connected, and positive N-type charge storage layer 6 is between positive p-type base 5 and positive N-type drift region 10；The front division
Trench gate structure includes：Positive gate electrode 81, the first front gate dielectric layer 82, the second front gate dielectric layer 83, front division electricity
Pole 71, the first front Split Electrode dielectric layer 72 and the second front Split Electrode dielectric layer 73, front division trench gate structure to
Under extended into through positive N+ launch sites 3, positive p-type base 5 and positive N-type charge storage layer 6 in N-type drift region 10；Grid
The depth of electrode 81 is more than the junction depth of positive p-type base 5 and less than the junction depth of positive N-type charge storage layer 6；Positive gate electrode 81
Upper surface is connected by the first front dielectric layer 22 with front side emitter pole metal 1, and positive gate electrode 81 is situated between by the first front grid
Matter layer 82 is in contact with positive N+ launch sites 3, positive p-type base 5 and positive N-type charge storage layer 6 respectively；Front Split Electrode
71 L-shaped semi-surrounding positive gate electrodes 81 set and are passed down through positive N+ launch sites 3, positive p-type base 5 and positive N-type
Charge storage layer 6 is simultaneously extended into N-type drift region 10, and the upper surface of front Split Electrode 71 is connected with front side emitter pole metal 1,
By being connected between the second front gate dielectric layer 83 and positive gate electrode 81, front Split Electrode 71 passes through front Split Electrode 71
First front Split Electrode dielectric layer 73 is in contact with N-type drift region 10；The thickness of front gate dielectric layer 82,83 is no more than front
The thickness of Split Electrode dielectric layer 72,73；Front division trench gate structure opposite side the top layer of N-type drift region 10 in also have with
Connected positive floating PXing Ti areas 9, positive floating PXing Ti areas 9 pass through the second front Split Electrode with front Split Electrode 71
For dielectric layer 72 with being connected, the upper surface of the positive front Split Electrode dielectric layer 72 of floating PXing Ti areas 9 and second has the second front
Dielectric layer 20, the second front dielectric layer 20 are connected with front side emitter pole metal 1；Back side MOS structure is identical with positive MOS structure.
Further, front N-channel MOS structure and back side N-channel MOS structure can be along N-type drift regions 10 in the present invention
Transversal centerline up and down specular, can also along N-type drift region 10 transversal centerline top-bottom cross symmetrically i.e. in device
Heart dot center is symmetrical.
Further, Split Electrode 71 and the equipotential of emitter metal 1 in the present invention.
Further, the junction depth in floating PXing Ti areas 9 is not less than the depth of division trench gate structure in the present invention.
When meeting that the junction depth in floating PXing Ti areas is more than the depth of division trench gate structure, floating PXing Ti areas 9 are horizontal to side
To extending in the N-type drift region 10 of the lower section of N-type charge storage layer 6, now, floating PXing Ti area 9P extend laterally to N-type electric charge
Distance in the N-type drift region 10 of the lower section of accumulation layer 6 is no more than P+ launch sites 4 and the width sum both N+ launch sites 3.
Further, the Split Electrode of the lower section of N-type charge storage layer 6 and close N-type charge storage layer side is situated between in the present invention
The thickness of the side wall of matter layer is more than the Split Electrode dielectric layer of the lower section of N-type charge storage layer 6 and remote N-type charge storage layer side
The thickness of side wall.
Meet the thickness of the lower section of N-type charge storage layer 6 and the side wall of the Split Electrode dielectric layer of close N-type charge storage layer side
When degree is more than the lower section of N-type charge storage layer 6 and the thickness of the side wall of the Split Electrode dielectric layer away from N-type charge storage layer side, N
The shape of the Split Electrode 71 of the lower section of type charge storage layer 6 is usually stepped.
Further, in the present invention further, the semi-conducting material of IGBT device uses Si, SiC, GaAs in the present invention
Or GaN, trench fill material can use same material also to adopt using polycrystalline Si, SiC, GaAs or GaN, and each several part
With combination of materials not of the same race.
On the other hand the present invention also provides a kind of two-way IGBT manufacture method, it is characterised in that comprises the following steps：
Step 1：Using two panels specification and parameter identical n type single crystal silicon piece, N-type drift region 10 is prepared；
Step 2：One layer of field oxygen is grown in two panels silicon chip surface respectively using same process, makes active area, regrowth by lithography
Pass through ion implanting N-type impurity and preparation N-type charge storage layer 6 of annealing after one layer of pre- oxygen；The N-type charge storage layer 6 is located at N
The side of the top layer of type drift region 10；Then ion implanting p type impurity and anneal preparation p-type base 5 and the first floating p-type body are passed through
Area 9, the junction depth in the first floating PXing Ti areas 9 are more than the junction depth of N-type charge storage layer 6, and p-type base 5 is located at N-type charge storage layer 6
Upper surface；
Step 3：Protective layer is deposited in two panels silicon chip surface respectively using same process, window is made by lithography and carries out groove silicon quarter
Erosion, is made the groove between the floating PXing Ti areas 9 of N-type charge storage layer 6 and first, and the depth of the groove is more than N-type electricity
The junction depth of lotus accumulation layer 6；
Step 4：Gate dielectric layer is formed in the trench wall of two panels silicon chip using same process respectively；
Step 5：Form depositing polysilicon in the groove of gate dielectric layer on two panels silicon chip respectively using same process, formed
Gate electrode 81；
Step 6：N+ transmittings are made by photoetching, ion implanting N-type impurity on two panels silicon chip using same process respectively
Area 3, N+ launch sites 3 are located at the upper surface of p-type base 5 and are connected by the dielectric layer of trench wall with gate electrode 81, pass through light
Carve, ion implanting p type impurity making P+ launch sites 4, P+ launch sites 4 and N+ launch sites 3 contact with each other and be arranged side by side；
Step 7：Using same process respectively in the positive dielectric layer deposited of two panels silicon chip, and photoetching, etching formation are located at
The surface media 2 of the upper surface in the first floating PXing Ti areas 9, gate electrode 81 and gate dielectric layer；
Step 8：Using same process respectively in the positive deposited metal of two panels silicon chip, formed positioned at P+ launch sites 4, N+
Launch site 3 and the emitter metal 1 of the upper surface of Split Electrode 71；
Step 9：Two panels silicon chip is overturn, silicon wafer thickness is thinned using same process, is then subtracted this two panels is identical
Both are bonded together to form two-way IGBT device by the silicon chip back side after thin to the back side using bonding technology.
Further, in step 2 of the present invention p-type base 5 and floating p-type body can be formed at twice by increasing lithography step
Area 9.
Further, can be stair-stepping by controlling technological parameter to be formed in trench etch process in step 4 of the present invention
Split Electrode 71.
Technological improvement of the present invention compared to prior art and corresponding effect are as described below：
The present invention by conventional trench gate structure introduce with the equipotential Split Electrode of surface emitting pole metal and
Floating PXing Ti areas are introduced positioned at the thick dielectric layer of Split Electrode the week side of boss, and in the side of division trench gate structure, based on above-mentioned
Technological means is not in the case where influenceing IGBT device threshold voltage and opening：
(1) introducing of divisions trench gate structure can change grid-collector capacitance for gate-emitter electric capacity,
Miller capacitance is greatly reduced, the adverse effect that Miller effect is brought is improved, reduces driving power consumption.
(2) in device opens dynamic process, the semiconductor surface contacted with Split Electrode dielectric layer will not form accumulation
Or inversion layer, therefore device is not in negative differential capacity effect, avoid the electric current opened in dynamic process, voltage oscillation and
EMI problems, improve device reliability.
(3) MOS gully densitys at Split Electrode reduce, and reduce the saturation current density of device, improve device
Short-circuit safety operation area, further increase the reliability of device.
(4) depth of gate electrodes is less than the junction depth of N-type charge storage layer, reduce gate-emitter electric capacity and grid-
Collector capacitance, so as to improve the switching speed of device, the switching loss of device is reduced, while it is more preferable to obtain device
Compromise characteristic between conduction voltage drop and switching loss.
(5) Split Electrode dielectric layer thick improves the concentration of channel bottom electric field, improves the breakdown voltage of device.
(6) introducing in floatings PXing Ti areas, the extraction area in hole is reduced, improves the carrier enhancing of emitter terminal
Effect, improve the carrier concentration profile of whole N-type drift region, further improve between forward conduction voltage drop and turn-off power loss
Compromise.
(7) presence of the certain thickness high concentration N-type layers 6 of compensate for due to Split Electrode 8 equipotential with emitter stage
The decline for causing carrier concentration near Split Electrode is introduced, is avoided because the introducing of Split Electrode 8 makes the positive guide of device
Poor device properties caused by logical pressure drop increased dramatically.
In summary, beneficial effects of the present invention are as follows：
The present invention realizes IGBT structure symmetrically forward and reverse conducting and turn-off characteristic, is ensureing certain device trenches
On the premise of depth and trench MOS structure density, when device works in either direction work, reduce grid-collector capacitance, change
The adverse effect that kind Miller effect is brought, reduce driving power consumption；Overall grid capacitance is reduced, improves the switching speed of device, is dropped
The switching loss of low device, improve the compromise between forward conduction voltage drop and turn-off power loss；Device is avoided to open in dynamic process
Electric current, voltage oscillation and EMI problems, improve device reliability；The saturation current density of device is reduced, improves device
Short-circuit safety operation area, further increase the reliability of device；Improve channel bottom electric field concentration effect, improve device breakdown
Voltage, further improve device reliability；The carrier enhancement effect of device emitter terminal is improved, improves the carrier of drift region
Concentration distribution, further improve the compromise of forward conduction voltage drop and turn-off power loss.Further it is proposed that two-way IGBT system
The method of making need not increase extra processing step, compatible with the two-way IGBT of tradition preparation method.
Brief description of the drawings
Fig. 1 is the structure cell schematic diagram of traditional NPT IGBT devices；
Fig. 2 is the structure cell schematic diagram of traditional FS-CSTBT devices；
Fig. 3 is the structure cell schematic diagram that the present embodiment 1 provides；
Fig. 4 is the structure cell schematic diagram that the present embodiment 2 provides；
Fig. 5 is the structure cell schematic diagram that the present embodiment 3 provides；
Fig. 1 to Fig. 5：
1 is front metal, and 22 be the first front dielectric layer, and 20 be the second front dielectric layer, and 3 be positive N+ launch sites, and 4 are
Positive P+ launch sites, 5 be positive p-type base, and 6 be positive N-type charge storage layer, and 71 be front Split Electrode, and 72 be second just
Face Split Electrode dielectric layer, 73 be the first front Split Electrode dielectric layer, and 81 be positive gate electrode, and 82 be the first front gate medium
Layer, 83 be the second front gate dielectric layer, and 9 be positive floating PXing Ti areas, and 10 be N-type drift region, and 21 be back metal, and 222 be the
One back side dielectric layer, 220 be back side second dielectric layer, and 23 be back side N+ launch sites, and 24 be back side P+ launch sites, and 25 be back side P
Type base, 26 be back side N-type charge storage layer, and 271 be back side Split Electrode, and 272 be the first back side Split Electrode dielectric layer,
273 be the second back side Split Electrode dielectric layer, and 281 be back side gate electrode, and 282 be the first back side gate dielectric layer, and 283 be second back of the body
Face gate dielectric layer, 29 be back side floating PXing Ti areas.
Fig. 6 is that the device architecture schematic diagram formed after groove is etched in the embodiment of the present invention 4；
Fig. 7 is the device architecture schematic diagram formed in the embodiment of the present invention 4 after Split Electrode dielectric layer；
Fig. 8 is the device architecture schematic diagram formed in the embodiment of the present invention 4 after Split Electrode；
Fig. 9 is the device after thick oxide layer and polysilicon formation gate trench in the embodiment of the present invention 4 in etching groove
Structural representation；
Figure 10 is the device architecture schematic diagram formed in the embodiment of the present invention 4 after gate dielectric layer；
Figure 11 is the device architecture schematic diagram formed in the embodiment of the present invention 4 after gate electrode；
Figure 12 is the device architecture schematic diagram formed in the embodiment of the present invention 4 behind N+ launch sites and P+ launch sites；
Figure 13 is the device architecture formed in the embodiment of the present invention 4 after first medium layer, second dielectric layer and metal electrode
Schematic diagram；
Figure 14 is the device architecture schematic diagram ultimately formed in the embodiment of the present invention 4 after wafer bonding；
Figure 15 is the device architecture schematic diagram formed in the embodiment of the present invention 5 after first division electrode；
Figure 16 is the device architecture schematic diagram formed in the embodiment of the present invention 5 after second Split Electrode dielectric layer；
Figure 17 is the device architecture schematic diagram formed in the embodiment of the present invention 5 after second Split Electrode；
Figure 18 is the device after thick oxide layer and polysilicon formation gate trench in the embodiment of the present invention 5 in etching groove
Structural representation；
Figure 19 is the device architecture schematic diagram formed in the embodiment of the present invention 5 after gate dielectric layer；
Figure 20 is the device architecture schematic diagram formed in the embodiment of the present invention 5 after gate electrode.
Embodiment
On the basis of traditional two-way IGBT device structure as illustrated in fig. 1 and 2, the present invention carries out rational modification, there is provided
A kind of new two-way IGBT device and preparation method thereof, in order to simplify description, specific embodiment of the invention is only two-way with N-channel
Illustrated exemplified by IGBT device, but can root the present disclosure applies equally to the two-way IGBT device of P-channel, those skilled in the art
The two-way IGBT device of P-channel is realized according to general knowledge known in this field.
The principle and characteristic of the present invention are described in detail with reference to specific embodiment and Figure of description：
Embodiment 1：
The present embodiment provides a kind of two-way IGBT, and its structure cell is as shown in figure 3, including being symmetricly set in N-type drift region
The N-channel MOS structure of 10 tow sides；Positive MOS structure includes：Front side emitter pole metal 1, the first front dielectric layer 22,
Two front dielectric layers 20, front division trench gate structure, positive P+ launch sites 3, positive N+ launch sites 4, the positive and of p-type base 5
Positive N-type charge storage layer 6 and positive PXing Ti areas 9；Back side MOS structure includes：Back side emitter pole metal 21, first back side are situated between
Matter layer 222, the second back side dielectric layer 220, back side division trench gate structure, back side P+ launch sites 23, back side N+ launch sites 24, the back of the body
Face p-type base 25 and back side N-type charge storage layer 26 and back side PXing Ti areas 29；It is characterized in that：
Front division trench gate structure is located at the upper surface centre position of N-type drift region 10, front division trench gate structure
There is positive N+ launch sites 3, positive P+ launch sites 4, positive p-type base 5 and positive N-type electric charge in the N-type drift region 10 of side
Accumulation layer 6；Positive N+ launch sites 3 and positive P+ launch sites 4 contact with each other and are located side by side at the lower section of front side emitter pole metal 1 simultaneously
It is connected with front side emitter pole metal 1；Positive p-type base 5 be located at the lower section of positive N+ launch sites 3 and positive P+ launch sites 4 and with
The two is connected, and positive N-type charge storage layer 6 is between positive p-type base 5 and positive N-type drift region 10；The front division
Trench gate structure includes：Positive gate electrode 81, the first front gate dielectric layer 82, the second front gate dielectric layer 83, front division electricity
Pole 71, the first front Split Electrode dielectric layer 72 and the second front Split Electrode dielectric layer 73, front division trench gate structure to
Under extended into through positive N+ launch sites 3, positive p-type base 5 and positive N-type charge storage layer 6 in N-type drift region 10；Just
The depth of face gate electrode 81 is more than the depth of positive p-type base 5 and less than the depth of positive N-type charge storage layer 6；Front grid electricity
The upper surface of pole 81 is connected by the first front dielectric layer 22 with front side emitter pole metal 1, and positive gate electrode 81 passes through the first front
Gate dielectric layer 82 is in contact with positive N+ launch sites 3, positive p-type base 5 and positive N-type charge storage layer 6 respectively；Front division
The L-shaped semi-surrounding positive gate electrode 81 of electrode 71 sets and is passed down through positive N+ launch sites 3, positive p-type base 5 and front
N-type charge storage layer 6 is simultaneously extended into N-type drift region 10, the upper surface of front Split Electrode 71 and the phase of front side emitter pole metal 1
Even, front Split Electrode 71 between the second front gate dielectric layer 83 and positive gate electrode 81 by being connected, front Split Electrode 71
It is in contact by the first front Split Electrode dielectric layer 73 with N-type drift region 10；The N-type of front division trench gate structure opposite side
Also there is the positive floating PXing Ti areas 9 being attached thereto, positive floating PXing Ti areas 9 and front Split Electrode in the top layer of drift region 10
71 by the second front Split Electrode dielectric layer 72 with being connected, the positive front Split Electrode dielectric layer of floating PXing Ti areas 9 and second
72 upper surface has the second front dielectric layer 20, and the second front dielectric layer 20 is connected with front side emitter pole metal 1；Back side MOS
Structure is identical with positive MOS structure and the two is symmetrical on device center.
The two-way IGBT device that the present embodiment provides may also be operated in bi-directional MOS pattern：By controlling back side gate electrode 281
Open the raceway groove of back side MOS structure, such back side MOS structure work is similar to the drain electrode of the unidirectional MOS device of tradition；It is and positive
MOS structure work is similar to the source electrode of the unidirectional MOS device of tradition, by controlling positive gate electrode 81 to realize MOS unlatching and pass
It is disconnected.When working in bi-directional MOS pattern, the present invention also has the operation principle and beneficial effect during similar to two-way IGBT mode of operations
Fruit.
Embodiment 2：
The present embodiment provides a kind of two-way IGBT, and its structure cell is as shown in figure 4, the present embodiment compares embodiment 1 not
It is same to be：The thickness of the lower section of N-type charge storage layer 6 and the side wall close to the Split Electrode dielectric layer of N-type charge storage layer side is big
In the lower section of N-type charge storage layer 6 and the thickness of the side wall of the Split Electrode dielectric layer of remote N-type charge storage layer side, the back side point
Dehiscence furrow slot grid structure and transversal centerline symmetrical above and below setting of the front division trench gate structure along N-type drift region 10.
The present embodiment causes the thickness of channel bottom dielectric layer to increase, and can further improve channel bottom electric field collection
In, improve the breakdown voltage of device.
Embodiment 3：
The present embodiment provides a kind of two-way IGBT, and its structure cell is as shown in figure 5, the present embodiment compares embodiment 1 not
It is same to be：Complete specular is set positive MOS structure up and down with transversal centerline of the back side MOS structure along N-type drift region 10.
Embodiment 4：
The manufacturing process of the present invention is specifically illustrated by taking the two-way IGBT device of 1200V voltage class as an example, is made
The concrete operations for making method are as follows：
Step 1：Using two panels specification and parameter identical n type single crystal silicon piece, the silicon wafer thickness of selection is 300~600um,
Doping concentration is 1013~1014Individual/cm3, prepare N-type drift region；
Step 2：One layer of field oxygen is grown in two panels silicon chip surface respectively using same process, makes active area, regrowth by lithography
By ion implanting N-type impurity and anneal after one layer of pre- oxygen and prepare N-type charge storage layer, the energy of ion implanting for 200~
500keV, implantation dosage 1013~1014Individual/cm2；The N-type charge storage layer is located at the side of N-type drift region top layer；Then
By ion implanting p type impurity and anneal preparation p-type base and floating PXing Ti areas, the energy of ion implanting is 60~120keV,
Implantation dosage is 1013~1014Individual/cm2, annealing temperature is 1100~1150 DEG C, and annealing time is 10~30 minutes；Floating p-type
The junction depth in body area is more than the junction depth of N-type charge storage layer, and p-type base is located at the upper surface of N-type charge storage layer；
Step 3：One layer of TEOS is deposited in two panels silicon chip surface using same process respectively, the thickness of TEOS layers for 700~
1000nm, make window by lithography and carry out groove silicon etching, then corroded after flute surfaces are carried out with oxidation processes using HF, obtained clean
Flute surfaces, groove between N-type charge storage layer and floating PXing Ti areas is made, the depth of the groove is more than N-type
The junction depth of charge storage layer；
Step 4：In 1050 DEG C~1150 DEG C, O2Atmosphere under using same process parameter respectively in the groove of two panels silicon chip
Inwall forms Split Electrode dielectric layer；
Step 5：Gate dielectric layer is formed on two panels silicon chip using same process parameter respectively at 750 DEG C~950 DEG C
Depositing polysilicon in groove, form Split Electrode；
Step 6：Adjusting process parameter simultaneously repeats the 3rd to 5 step, and silicon chip surface is exposed and etches to obtain groove, then
Corroded after flute surfaces are carried out with oxidation processes using HF, obtain clean flute surfaces, the depth of the groove is more than P-type layer
6 junction depth, the junction depth less than N-type charge storage layer 7；Then aoxidized, prepare gate oxide, the thickness of the gate oxide
Less than the thickness of Split Electrode dielectric layer；Then the depositing polysilicon in groove, gate electrode is formed；
Step 7：N+ transmittings are made by photoetching, ion implanting N-type impurity on two panels silicon chip using same process respectively
Area, the energy of ion implanting are 30~60keV, implantation dosage 1015~1016Individual/cm2, N+ launch sites are located at the upper of p-type base
Surface is simultaneously connected by the dielectric layer of trench wall with gate electrode；P+ launch sites are made by photoetching, ion implanting p type impurity,
The energy of ion implanting is 60~80keV, implantation dosage 1015~1016Individual/cm2, annealing temperature be 900 DEG C, the time be 20~
30 minutes, P+ launch sites and N+ launch sites contacted with each other and are arranged side by side；
Step 8：Using same process respectively in the positive dielectric layer deposited of two panels silicon chip, and photoetching, etching formation are located at
The first medium floor of gate electrode and gate oxide upper surface and positioned at floating PXing Ti areas and first division electrode dielectric upper surface
Second dielectric layer；
Step 9：P+ launch sites and N+ are located in the positive deposited metal of two panels silicon chip, formation using same process respectively
The metal level of launch site upper surface；
Step 10：Two panels silicon chip is overturn, silicon wafer thickness is thinned using same process, is then subtracted this two panels is identical
Both are bonded together to form two-way IGBT device by the silicon chip back side after thin to the back side using bonding technology.
Embodiment 5：
The present embodiment provides a kind of two-way IGBT manufacture method, and the present embodiment is compared to the difference of embodiment 4：This hair
Can be by controlling below technological parameter N-type charge storage layer 6 and close to N-type electricity in trench etch process in bright step 4
The thickness of the side wall of the Split Electrode dielectric layer of lotus accumulation layer side is more than the lower section of N-type charge storage layer 6 and away from the storage of N-type electric charge
The thickness of the side wall of the Split Electrode dielectric layer of layer side, so as to form stair-stepping Split Electrode 71.
It can be seen from common sense in the field, the material of two-way IGBT device can use silicon (Si), carborundum in the present invention
(SiC), any suitable semi-conducting material such as GaAs (GaAs), gallium nitride (GaN) is achieved；Dielectric layer of the present invention
Material can use silica (SiO2), hafnium oxide (HfO2) or silicon nitride (Si3N4) etc. be achieved；Manufacture method
Processing step can be also adjusted according to being actually needed.
Above-described embodiment only provides two specific implementations based on present inventive concept, those skilled in the art according to
General knowledge known in this field should be known that the scope of the present invention is not limited to the content disclosed in specific embodiment, above-mentioned specific
Embodiment is only schematical, rather than restricted, one of ordinary skill in the art the present invention enlightenment under,
In the case of not departing from present inventive concept and scope of the claimed protection, many forms can be also made, these belong to this hair
Within bright protection.
Claims (7)
1. a kind of two-way IGBT, its structure cell include：It is symmetricly set on the N-channel MOS of N-type drift region (10) front and back
Structure；Positive MOS structure includes：Front side emitter pole metal (1), the first front dielectric layer (22), the second front dielectric layer (20),
Front division trench gate structure, positive P+ launch sites (3), positive N+ launch sites (4), positive p-type base (5) and positive N-type electricity
Lotus accumulation layer (6) and positive PXing Ti areas (9)；Back side MOS structure includes：Back side emitter pole metal (21), the first back side dielectric layer
(222), the second back side dielectric layer (220), back side division trench gate structure, back side P+ launch sites (23), back side N+ launch sites
(24), back side p-type base (25) and back side N-type charge storage layer (26) and back side PXing Ti areas (29)；It is characterized in that：
Front division trench gate structure is located at the upper surface centre position of N-type drift region (10), front division trench gate structure one
There is positive N+ launch sites (3), positive P+ launch sites (4), positive p-type base (5) and positive N in the N-type drift region (10) of side
Type charge storage layer (6)；Positive N+ launch sites (3) and positive P+ launch sites (4) contact with each other and are located side by side at front side emitter pole
The lower section of metal (1) is simultaneously connected with front side emitter pole metal (1)；Positive p-type base (5) is located at positive N+ launch sites (3) and just
The lower section of face P+ launch sites (4) and it is connected with the two, positive N-type charge storage layer (6) is located at positive p-type base (5) and positive N
Between type drift region (10)；The front division trench gate structure includes：Positive gate electrode (81), the first front gate dielectric layer
(82), the second front gate dielectric layer (83), front Split Electrode (71), the first front Split Electrode dielectric layer (72) and second be just
Face Split Electrode dielectric layer (73), front division trench gate structure are passed down through positive N+ launch sites (3), positive p-type base (5)
With positive N-type charge storage layer (6) and extend into N-type drift region (10)；The depth of positive gate electrode (81) is more than positive P
The junction depth of type base (5) and the junction depth for being less than positive N-type charge storage layer (6)；Positive gate electrode (81) upper surface passes through first
Front dielectric layer (22) is connected with front side emitter pole metal (1), and positive gate electrode (81) passes through the first front gate dielectric layer (82)
It is in contact respectively with positive N+ launch sites (3), positive p-type base (5) and positive N-type charge storage layer (6)；Front Split Electrode
(71) L-shaped semi-surrounding positive gate electrode (81) set and be passed down through positive N+ launch sites (3), positive p-type base (5) and
Positive N-type charge storage layer (6) is simultaneously extended into N-type drift region (10), and Split Electrode (71) upper surface in front is sent out with front
Emitter-base bandgap grading metal (1) is connected, and front Split Electrode (71) passes through between the second front gate dielectric layer (83) and positive gate electrode (81)
It is connected, front Split Electrode (71) is in contact by the first front Split Electrode dielectric layer (73) with N-type drift region (10)；Front
The thickness of gate dielectric layer (82,83) is not more than the thickness of front Split Electrode dielectric layer (72,73)；Front division trench gate structure
Also there is the positive floating PXing Ti areas (9) being attached thereto, positive floating PXing Ti areas in N-type drift region (10) top layer of opposite side
(9) with front Split Electrode (71) by the second front Split Electrode dielectric layer (72) with being connected, positive floating PXing Ti areas (9)
And second the upper surface of front Split Electrode dielectric layer (72) there is the second front dielectric layer (20), the second front dielectric layer (20)
It is connected with front side emitter pole metal (1)；Back side MOS structure it is identical with positive MOS structure and the two on device center it is symmetrical or
Person is symmetrical above and below along the transversal centerline of N-type drift region.
A kind of 2. two-way IGBT according to claim 1, it is characterised in that：Split Electrode (71) and emitter metal (1)
Equipotential.
A kind of 3. two-way IGBT according to claim 1, it is characterised in that：The junction depth in floating PXing Ti areas (9), which is not less than, to be divided
The depth of dehiscence furrow slot grid structure.
A kind of 4. two-way IGBT according to claim 3, it is characterised in that：Floating PXing Ti areas (9) extend laterally to side
In N-type drift region (10) below to N-type charge storage layer (6), floating PXing Ti areas (9) P extends laterally to the storage of N-type electric charge
The distance in N-type drift region (10) below layer (6) is no more than P+ launch sites (4) and N+ launch sites (3) width sum of the two.
A kind of 5. two-way IGBT according to claim 1, it is characterised in that：Below N-type charge storage layer (6) and close to N
The thickness of the side wall of the Split Electrode dielectric layer of type charge storage layer side is more than below N-type charge storage layer (6) and away from N-type electricity
The thickness of the side wall of the Split Electrode dielectric layer of lotus accumulation layer side.
6. a kind of two-way IGBT manufacture method, it is characterised in that comprise the following steps：
Step 1：Using two panels specification and parameter identical n type single crystal silicon piece, N-type drift region (10) is prepared；
Step 2：One layer of field oxygen is grown in two panels silicon chip surface respectively using same process, makes active area, one layer of regrowth by lithography
Pass through ion implanting N-type impurity and preparation N-type charge storage layer of annealing after pre- oxygen；The N-type charge storage layer is located at N-type drift
The side of area's top layer；Then by ion implanting p type impurity and anneal preparation p-type base and the first floating PXing Ti areas, first is floating
The junction depth in KongPXing Ti areas is more than the junction depth of N-type charge storage layer, and p-type base is located at the upper surface of N-type charge storage layer (6)；
Step 3：Protective layer is deposited in two panels silicon chip surface respectively using same process, window is made by lithography and carries out groove silicon etching,
Be made positioned at N-type charge storage layer and the first floating PXing Ti areas) between groove, the depth of the groove deposits more than N-type electric charge
The junction depth of reservoir；
Step 4：Gate dielectric layer is formed in the trench wall of two panels silicon chip using same process respectively；
Step 5：Form depositing polysilicon in the groove of gate dielectric layer on two panels silicon chip respectively using same process, form grid electricity
Pole；
Step 6：N+ launch sites, N+ are made by photoetching, ion implanting N-type impurity on two panels silicon chip using same process respectively
Launch site is located at the upper surface of p-type base and is connected by the dielectric layer of trench wall with gate electrode, passes through photoetching, ion implanting
P type impurity makes P+ launch sites, and P+ launch sites and N+ launch sites contact with each other and be arranged side by side；
Step 7：Using same process respectively in the positive dielectric layer deposited of two panels silicon chip, and photoetching, etching form and be located at first
The surface media of the upper surface in floating PXing Ti areas, gate electrode and gate dielectric layer；
Step 8：Using same process respectively in the positive deposited metal of two panels silicon chip, formed and launched positioned at P+ launch sites, N+
Area and the emitter metal of the upper surface of Split Electrode；
Step 9：Overturn two panels silicon chip, silicon wafer thickness is thinned using same process, then by this two panels it is identical be thinned after
Silicon chip back side to the back side, both are bonded together to form into two-way IGBT device using bonding technology.
A kind of 7. two-way IGBT according to claim 1 manufacture method, it is characterised in that：Pass through in step 2 of the present invention
Increase lithography step forms p-type base and floating PXing Ti areas at twice.
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| CN112510086A (en) * | 2020-11-27 | 2021-03-16 | 广东美的白色家电技术创新中心有限公司 | IGBT device and intelligent power module |
| CN113659010A (en) * | 2021-09-09 | 2021-11-16 | 捷捷微电(无锡)科技有限公司 | MOSFET device integrated with RC absorption structure and manufacturing method |
| CN117276329A (en) * | 2023-11-20 | 2023-12-22 | 深圳天狼芯半导体有限公司 | LDMOS with trench gate and preparation method |
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Application publication date: 20180306 |