CN107768434A - A kind of two-way IGBT and its manufacture method - Google Patents
A kind of two-way IGBT and its manufacture method Download PDFInfo
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
A kind of two-way IGBT device and its manufacture method, belong to power semiconductor device technology field.The present invention in device front and back by being symmetrically introduced trench emitter structure and PXing Ti areas, it is achieved thereby that symmetrical forward and reverse conducting, blocking and switching characteristic.The two-way IGBT structure of the present invention reduces the width and depth of gate electrode, reduces driving power consumption；Avoid electric current, voltage oscillation and the EMI problems in device unlatching dynamic process；Grid capacitance is reduced, improves the switching speed of device, reduces the switching loss of device；The concentration of channel bottom electric field is improved, improves the breakdown voltage of device；The carrier enhancement effect of emitter terminal is improved, improves the carrier concentration profile of whole N-type drift region, improves the compromise between forward conduction voltage drop and turn-off power loss.Further it is proposed that two-way IGBT manufacture need not increase extra processing step, it is compatible with the two-way IGBT of tradition preparation method.
Description
Technical field
The invention belongs to power semiconductor device technology field, is related to insulated gate bipolar transistor (IGBT), specifically relates to
And a kind of two-way trench gate insulated gate bipolar transistor (Bi-directional trench IGBT) and its manufacture method.
Background technology
Insulated gate bipolar transistor (IGBT) insulated type FET (MOSFET) and bipolar junction transistor (BJT) are multiple
The novel power transistor formed is closed, the MOSFET of bipolar junction transistor driving can be equivalent to.IGBT is mixed with MOSFET
The working mechanism of structure and bipolar junction transistor, both with MOSFET is easy to driving, that input impedance is low, switching speed is fast is excellent
Point, there is the advantages of BJT on state current density is big, conduction voltage drop is low, loss is small, stability is good again, so, compare IGCT etc.
For current control device, have in terms of the simplification of controllability, safety operation area, switching loss and drive circuit obvious excellent
Gesture, it is set to be significantly improved in the application to the performance of power electronic system.At present, IGBT has turned into modern power electronic electricity
One of core electron component in road, it is widely used in the every field such as traffic, communication, household electrical appliance and Aero-Space.
Transformation of electrical energy is a basic step of many applied power electronics, is one of basic function of electric device, root
According to the difference of load request, electric device can complete AC-to DC (AC-DC), and direct current to exchange (DC-AC), direct current is to directly
Flow the conversion of (DC-DC) and AC to AC (AC-AC).AC-AC conversion can be AC-DC-AC modes using indirect conversion,
Can also be by the way of directly conversion be AC-AC., it is necessary to there is big capacitance in traditional AC-DC-AC indirect conversion systems
Electric capacity (voltage-type conversion) or the connection inductance (current mode conversion) of inductance value greatly are connected by the relatively independent transformation system of two parts
It is connected, this kind of system bulk is big, and cost is high.In addition, the service life of electric capacity and inductance is far below power device, this has a strong impact on
The reliability of system and service life.AC-AC direct converting systems avoid in traditional AC-DC-AC systems connect electric capacity or
The use of inductance, but require that power switch has two-way switch ability.Thus, the exploitation of two-way switch is always that alternating electromotive force becomes
The study hotspot of changing device, the two-way switch of early stage is using the IGCT for being equipped with external forced converter circuit.Two-way opened at present
Close using most commonly used semiconductor devices is IGBT, because traditional IGBT only has one-way conduction and the work(that unidirectionally blocks
Can, the constituted mode for having the IGBT two-way switch of two-way admittance two-way blocking-up function main has：Diode bridge, common collector
Formula and common emitter formula.Later reverse blocking IGBT (RB-IGBT) occurs, and such devices have the larger energy for bearing backward voltage
Power so that two-way switch can be simplified to simple inverse parallel structure, eliminate two fast recovery diodes.But open above
Pass scheme belongs to packet type switch, it is necessary to which a large amount of power chips, add system cost, and each chip chamber of internal system needs in addition
Want a large amount of lines, more complicated combination to enhance the ghost effect of internal system, influence system reliability.
In this context, in order to solve the above problems and realize the integrated of product, industry by using bonding techniques or
The method of person's dual surface lithography carries out the development of two-way igbt chip.With silicon-silicon bond close technology development, in recent years it has been proposed that
Back-to-back be bonded together of two identical trench MOS structures successfully realized into tool as shown in Figure 1 in one chip
There are two-way admittance and the two-way IGBT of two-way blocking-up function (Bi-directional IGBT), two-way IGBT generation is greatly
The cost of device is reduced, reduces the stray parameter of circuit.IGBT unidirectional compared to tradition, by controlling front and back grid electricity
Pressure, the two-way IGBT can realize symmetrical forward and reverse IGBT conductings and turn-off characteristic.In addition, the structure is in p-type base 5 and N-
Between drift region 9 and p-type base 25 and N-One layer is symmetrically employed between drift region 9 and compares N-The doping concentration of drift region 9 is high
Positive N-type layer 6 and back side N-type layer 26, are on the one hand thinned N compared with the two-way IGBT structure of NPT types-Drift region thickness, reduce
Drift zone resistance, and then reduce forward conduction voltage drop and improve switching speed, on the other hand should when either direction works
Two-way IGBT is the IGBT structure for storing layer and electric field trapping layer with carrier, significantly improves the performance of device.For
Structure shown in Fig. 1, when IGBT forward or backwards works, because positive N-type layer 6 and back side N-type layer 26 are deposited as carrier
Storage layer causes IGBT device to be greatly improved close to the carrier concentration profile of emitter terminal, improve N-type drift region
Conductance modulation, improve the carrier concentration profile of whole N-type drift region, make IGBT obtain low forward conduction voltage drop and
The compromise of improved forward conduction voltage drop and turn-off power loss.However, for this two-way IGBT structure, due to positive N-type
The presence of layer 6 and back side N-type layer 26, the breakdown voltage of device can be significantly reduced when IGBT forward or backwards works.In order to have
The adverse effect of effect shielding N-type charge storage layer, the higher device of acquisition is pressure-resistant, mainly uses the following two kinds mode：
(1) trench gate depth deep, the depth of trench gate is generally made to be more than the junction depth of N-type charge storage layer；
(2) cellular width small, that is, improving MOS structure gully density makes trench gate spacing as small as possible；
Mode (1) can increase gate-emitter electric capacity and grid-collector capacitance while implementation, and IGBT switch
It is exactly the process that charge/discharge is carried out to grid capacitance on process nature, so, when the increase of grid capacitance can cause charge/discharge
Between increase, in turn result in switching speed reduction.Thus, deep trench gate depth will reduce devices switch speed, increase device
Switching loss, have influence on the compromise characteristic of break-over of device pressure drop and switching loss；And the implementation of mode (2) is on the one hand by enhancer
The grid capacitance of part, cause devices switch speed to reduce, switching loss increase, influence the folding of break-over of device pressure drop and switching loss
Middle characteristic, the big gully density of another aspect will also increase the saturation current density of device, and become shorted devices safety operation area
Difference.In addition, for two-way IGBT structure as shown in Figure 1, gate oxide is formed in the trench by a thermal oxide, in order to
Ensure that the thickness of the whole gate oxide of certain threshold voltage is smaller, because the thickness of mos capacitance size and oxide layer is into anti-
Than small gate oxide thickness greatly increases the grid capacitance of device in the two-way IGBT structure of tradition.In addition, small grid oxygen
Changing thickness degree concentrates the electric field of channel bottom, makes the reliability of device poor.
The content of the invention
The present invention is directed to above-mentioned technical problem existing for existing two-way IGBT device, in order in certain device trench depth
In the case of trench MOS structure density, when two-way IGBT device either direction works, overall gate capacitance is reduced, improves device
The switching speed of part, reduces the switching loss and driving power consumption of device, improve the two-way IGBT structure forward conduction voltage drop of tradition with
Compromise between turn-off power loss；Electric current, voltage oscillation and the EMI problems in device opens dynamic process are avoided, improves device
Reliability；Improve channel bottom electric field concentration effect, improve device forward break down voltage, further improve device reliability；Enter
One step improves the carrier enhancement effect of device emitter terminal, improves the carrier concentration profile of drift region, further improves just
Compromise to conduction voltage drop and turn-off power loss, on the basis of the two-way IGBT device structure of tradition, the present invention provides a kind of two-way
IGBT device as shown in Figure 2 and its manufacture method.In order to simplify description, below only by taking the two-way IGBT device of N-channel as an example for
It is bright, but the present disclosure applies equally to the two-way IGBT device of P-channel.The technical scheme is that：
A kind of two-way IGBT, its structure cell include：It is symmetricly set on the N-channel MOS of the front and back of N-type drift region 9
Structure；Front N-channel MOS structure includes front side emitter pole metal 1, the first front dielectric layer 20, the second front dielectric layer 22, just
Face trench emitter structure, front trench gate structure, positive P+ launch sites 3, positive N+ launch sites 4, positive p-type base 5 and just
Face N-type charge storage layer 6 and positive PXing Ti areas 11；Back side N-channel MOS structure includes back side emitter pole metal 21, first back side
Dielectric layer 220, the second back side dielectric layer 222, backside trench emitter structure, backside trench grid structure, back side P+ launch sites 23,
Back side N+ launch sites 24, back side p-type base 25 and back side N-type charge storage layer 26 and back side PXing Ti areas 211；It is characterized in that：
Positive trench emitter structure is located among the upper surface of N-type drift region 9, and front trench gate structure is located at N-type drift
The side of the upper surface of area 9, have between positive trench emitter structure and front trench gate structure and contact with each other and be arranged side by side
Positive P+ launch sites 3 and positive N+ launch sites 4, the lower section of positive P+ launch sites 3 and positive N+ launch sites 4, which has, to be attached thereto
Positive p-type base 5, there is positive N-type charge storage layer 6 between positive p-type base 5 and N-type drift region 9；Positive P+ transmittings
The upper surface of area 3 and positive N+ launch sites 4 is connected with front side emitter pole metal 1, positive PXing Ti areas 11 and positive trench emitter
Structure is connected and positioned at the opposite side of the upper surface of N-type drift region 9, the positive upper surface of PXing Ti areas 11 and the first front dielectric layer 20
Connection, the first front dielectric layer 20 are connected with front side emitter pole metal 1；The positive trench emitter structure includes：Front ditch
The front side emitter pole dielectric layer 72 of groove emitter electrode 71 and first and the second front side emitter pole dielectric layer 73；Positive trench emitter
Electrode 71 is connected by the first front side emitter pole dielectric layer 72 with PXing Ti areas 11, and positive trench emitter electrode 71 passes through second
Front side emitter pole dielectric layer 73 is connected with positive P+ launch sites 3, positive p-type base 5 and positive N-type charge storage layer 7；It is described just
Face trench gate structure includes：The front gate dielectric layer 83 of positive gate electrode 81 and first and the second front gate dielectric layer 82, gate electrode
81 are connected by the first front gate dielectric layer 83 with positive N-type charge storage layer 6, and gate electrode 81 passes through the second front gate dielectric layer
82 are connected with positive N+ launch sites 4, positive p-type base 5 and positive N-type charge storage layer 7；The depth of the front trench gate structure
Junction depth of the degree more than positive p-type base 6 and the junction depth less than positive N-type charge storage layer 7；The front gate dielectric layer 82,83
Thickness be not more than front side emitter pole dielectric layer 72,73 thickness；The back side N-channel MOS structure and front N-channel MOS knot
Structure is identical.
Further, front N-channel MOS structure can be along the transversal centerline of N-type drift region 9 with back side N-channel MOS structure
Specular, can also be front N-channel MOS structure and back side N-channel MOS along the transversal centerline crossed-symmetrical of N-type drift region 9
Structure is symmetrical on device center dot center.
Further, the junction depth in PXing Ti areas of positive PXing Ti areas 11 or the back side 211 is more than trench emitter in the present invention
The depth of structure, beyond the part of trench emitter structure to side extend laterally to the lower section of positive N-type charge storage layer 6 or
In the N-type drift region 9 of the top of back side N-type charge storage layer 6.
Further, also there is the second P-type layer 13 being attached thereto, the 2nd P in the present invention below the trench gate structure of front
Type layer 13 is extended laterally to side in the N-type drift region 9 of the positive lower section of N-type charge storage layer 6；Backside trench grid structure with just
The setting symmetrical above and below of transversal centerline of the face trench gate structure along N-type drift region 9.
Further, front trench gate structure also includes front Split Electrode 84 and front Split Electrode medium in the present invention
Layer 85, front Split Electrode 84 is located at the lower section of positive gate electrode 81 and the two is connected by the first front gate dielectric layer 83, front
Pass through the phase of front Split Electrode dielectric layer 85 between Split Electrode 84 and positive N-type charge storage layer 6 and positive N-type drift region 9
Even；Backside trench grid structure and the setting symmetrical above and below of transversal centerline of the front trench gate structure along N-type drift region 9.
According to embodiments of the present invention, front Split Electrode 84 and front side emitter pole metal equipotential, back side Split Electrode 284
With back side emitter pole metal equipotential.
Further, the positive trench emitter electrode 71 of the present invention and back side emitter pole electrode 271 are wide at the top and narrow at the bottom
Step structure.
Further, front Split Electrode 84 and back side Split Electrode 284 of the present invention are up-narrow and down-wide stepped knot
Structure.
Further, the junction depth of positive N-type charge storage layer 6 is less than the depth of positive trench emitter electrode 71 in the present invention
Degree, the junction depth of back side N-type charge storage layer 26 are less than the depth of backside trench emitter electrode 271.
Further, the width of trench gate structure is less than the width of trench emitter structure in the present invention.
Further, the width of the gate electrode is less than the width of trench emitter electrode.
Further, the depth of trench emitter structure is less than or equal to the junction depth in PXing Ti areas in the present invention.
It is further that the semi-conducting material of IGBT device uses Si, SiC, GaAs or GaN in the present invention, and groove is filled out
Filling material can use same material also to use not same material group using polycrystalline Si, SiC, GaAs or GaN, and each several part
Close.
On the other hand, present invention also offers a kind of two-way IGBT manufacture method, it is characterised in that including following step
Suddenly：
Step 1：N-type drift region of the monocrystalline silicon piece as device is lightly doped using two parameters and specification identical N-type,
Silicon chip surface deposits protective layer, makes window by lithography and carries out groove silicon etching, and then etching is formed independently of each other in N-type drift region
Emitter trench and gate trench, the depth of emitter trench be more than the depth of gate trench；
Step 2：One layer of field oxidation is being grown through the two panels silicon chip surface obtained by step 1 processing using same process respectively
Layer, is lithographically derived active area, then one layer of pre-oxidation layer of regrowth, by emitter trench and positioned at emitter trench side
Gate trench between and the gate trench bottom injection N-type impurity N-type charge storage layer is made；Stored again in N-type electric charge
Layer top and the top layer implanting p-type impurity positioned at emitter trench opposite side simultaneously make annealing treatment obtained p-type base and p-type body respectively
Area；
Step 3：Using same process, the trench wall on two panels silicon chip forms dielectric layer respectively, using same process point
Depositing polysilicon in groove not on two panels silicon chip, polysilicon and its dielectric layer of the week side of boss form groove hair in emitter trench
Emitter structure, polysilicon and its dielectric layer in outside form trench gate structure in gate trench；
Step 4：Using same process, photoetching, ion implanting N-type impurity form N+ launch sites, institute on two panels silicon chip respectively
N+ launch sites are stated to be located at p-type base upper surface and with the dielectric layer of gate trench inwall be connected；Using same process respectively two
Photoetching, ion implanting p type impurity form P+ launch sites on piece silicon chip, and P+ launch sites are arranged side by side with N+ launch sites and phase mutual connection
Touch；
Step 5：Using same process, in two panels silicon chip surface dielectric layer deposited, and it is lithographically formed positioned at PXing Ti areas upper table
The first medium layer and second Jie positioned at trench gate structure upper surface of face and its mutually close emitter stage dielectric layer upper surface
Matter layer；
Step 6：Using same process, metal is deposited in two panels silicon chip surface, and formed and be located at using photoetching, etching technics
Trench gate structure, P+ launch sites, N+ launch sites and trench emitter electrode and its mutually close emitter stage dielectric layer upper surface
Emitter metal；
Step 7：Two panels silicon chip is overturn, silicon wafer thickness is thinned using same process, is then subtracted this two panels is identical
Both are bonded together to form two-way IGBT device by the silicon chip back side after thin to the back side using bonding technology.
Further, in the present invention p-type base and PXing Ti areas can be formed at twice by increasing lithography step.
Further, in the present invention emitter trench and grid ditch can be formed at twice by increasing photoetching, etch step
Groove.
Further, in the present invention trench emitter structure and ditch can be formed at twice by increasing oxidation and depositing step
Groove grid structure.
Further, the control of etch process parameters can be passed through in trench etch process in the present invention so that channel bottom
The thickness of the thickness ratio trench top medium layer of dielectric layer is bigger.
Further, can be by increasing ion implanting step in groove before N-type charge storage layer is formed in the present invention
P-type layer is formed on bottom.
Beneficial effects of the present invention are as follows：
The present invention provides a kind of two-way IGBT device, realizes IGBT structure symmetrically forward and reverse conducting and turn-off characteristic；
Reduce driving power consumption；Avoid electric current, voltage oscillation and the EMI problems in device unlatching dynamic process；Improve device
Short-circuit safety operation area；Grid capacitance is reduced, improves the switching speed of device, reduces the switching loss of device；Improve
The concentration of channel bottom electric field, improve the breakdown voltage of device；The carrier enhancement effect of emitter terminal is improved, is improved
The carrier concentration profile of whole N-type drift region, improves the compromise between forward conduction voltage drop and turn-off power loss.The present invention carries
The two-way IGBT gone out manufacture method need not increase extra processing step, compatible with the two-way IGBT of tradition preparation method.
Brief description of the drawings
Fig. 1 is traditional groove-shaped two-way IGBT device structure cell schematic diagram；
Fig. 2 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 1；
Fig. 3 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 2；
Fig. 4 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 3；
Fig. 5 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 4；
Fig. 6 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 5；
Fig. 7 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 6；
Fig. 8 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 7；
Fig. 9 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 8；
Fig. 1 is into Fig. 9：
1 is front side emitter pole metal, and 20 be the first front dielectric layer, and 22 be the second front dielectric layer, and 3 be that positive N+ launches
Area, 4 be positive P+ launch sites, and 5 be positive p-type base, and 6 be positive N-type charge storage layer, and 71 be positive trench emitter electricity
Pole, 72 be the first front side emitter pole dielectric layer, and 73 be the second front side emitter pole dielectric layer, and 81 be positive gate electrode, and 82 be second
Front gate dielectric layer, 83 be the first front gate dielectric layer, and 84 be front Split Electrode, and 85 be front Split Electrode dielectric layer, and 9 are
N-type drift region, 11 be positive PXing Ti areas, and 12 be the first positive P-type layer, and 13 be the second positive P-type layer, and 21 be back side emitter pole
Metal, 220 be back side first medium layer, and 222 be back side second dielectric layer, and 23 be back side N+ launch sites, and 24 be that back side P+ launches
Area, 25 be back side p-type base, and 26 be back side N-type charge storage layer, and 271 be backside trench emitter electrode, and 272 be first back of the body
Surface launching pole dielectric layer, 273 be the second back side emitter pole dielectric layer, and 281 be back side gate electrode, and 282 be the first back side gate medium
Layer, 283 be the second back side gate dielectric layer, and 284 be back side Split Electrode, and 285 be back side Split Electrode dielectric layer, and 29 be that N-type is floated
Area is moved, 211 be back side PXing Ti areas, and 212 be the first back side P-type layer, and 213 be the second back side P-type layer.
Figure 10 is to etch the device architecture schematic diagram formed after groove in the manufacture method of embodiment 1；
Figure 11 is the device architecture schematic diagram formed in the manufacture method of embodiment 1 after groove internal oxidation layer；
Figure 12 be embodiment 1 manufacture method in the trench depositing polysilicon form trench emitter electrode and gate electrode
Device architecture schematic diagram afterwards；
Figure 13 is the device architecture schematic diagram formed in the manufacture method of embodiment 1 behind N+ launch sites and P+ launch sites；
Figure 14 is the device architecture after forming first medium layer and second dielectric layer on surface in the manufacture method of embodiment 1
Schematic diagram；
Figure 15 is the device architecture schematic diagram after forming metal electrode on surface in the manufacture method of embodiment 1；
Figure 16 is the device architecture schematic diagram ultimately formed in the manufacture method of embodiment 1 after wafer bonding；
Figure 17 is the device architecture schematic diagram formed in the manufacture method of embodiment 2 after groove；
Figure 18 is the device architecture schematic diagram formed in the manufacture method of embodiment 3 after groove；
Figure 19 is the device architecture schematic diagram formed in the manufacture method of embodiment 4 after trench dielectric layer；
Figure 20 be embodiment 4 manufacture method in device architecture schematic diagram in groove after depositing polysilicon；
Figure 21 be embodiment 4 manufacture method in etching groove grid structure unnecessary oxide layer and polysilicon form division electricity
Device architecture schematic diagram after extremely；
Figure 22 is the device architecture schematic diagram formed in the manufacture method of embodiment 4 after gate dielectric layer；
Figure 23 is the device architecture schematic diagram formed in the manufacture method of embodiment 4 after gate electrode.
Embodiment
The operation principle and characteristic of device of the present invention are carried out specifically with reference to Figure of description and specific embodiment
It is bright：
Embodiment 1：
Present embodiments provide a kind of two-way IGBT device, its structure cell as shown in figure 3, including：It is symmetricly set in N-type
The N-channel MOS structure of the tow sides of drift region 9；
The front N-channel MOS structure includes front side emitter pole metal 1, the first front dielectric layer 20, the second front medium
Layer 22, positive trench emitter structure, front trench gate structure, positive P+ launch sites 3, positive N+ launch sites 4, positive p-type base
Area 5 and positive N-type charge storage layer 6 and positive PXing Ti areas 11；The back side N-channel MOS structure includes back side emitter pole metal
21st, the first back side dielectric layer 220, the second back side dielectric layer 222, backside trench emitter structure, backside trench grid structure, the back side
P+ launch sites 23, back side N+ launch sites 24, back side p-type base 25 and back side N-type charge storage layer 26 and back side PXing Ti areas 211；
It is characterized in that：
Positive trench emitter structure is located among the upper surface of N-type drift region 9, and front trench gate structure is located at N-type drift
The side of the upper surface of area 9, have between positive trench emitter structure and front trench gate structure and contact with each other and be arranged side by side
Positive P+ launch sites 3 and positive N+ launch sites 4, the lower section of positive P+ launch sites 3 and positive N+ launch sites 4, which has, to be attached thereto
Positive p-type base 5, there is positive N-type charge storage layer 6 between positive p-type base 5 and N-type drift region 9；Positive P+ transmittings
The upper surface of area 3 and positive N+ launch sites 4 is connected with front side emitter pole metal 1, positive PXing Ti areas 11 and positive trench emitter
Structure is connected and positioned at the opposite side of the upper surface of N-type drift region 9, the positive upper surface of PXing Ti areas 11 and the first front dielectric layer 20
Connection, the first front dielectric layer 20 are connected with front side emitter pole metal 1；The positive trench emitter structure includes：Front ditch
The front side emitter pole dielectric layer 73 of groove emitter electrode 71 and first and the second front side emitter pole dielectric layer 73；Positive trench emitter
Electrode 71 is connected by the first front side emitter pole dielectric layer 72 with PXing Ti areas 11, and positive trench emitter electrode 71 passes through second
Front side emitter pole dielectric layer 73 is connected with positive P+ launch sites 3, positive p-type base 5 and positive N-type charge storage layer 7；It is described just
Face trench gate structure includes：The front gate dielectric layer 83 of positive gate electrode 81 and first and the second front gate dielectric layer 82, gate electrode
81 are connected by the first front gate dielectric layer 83 with positive N-type charge storage layer 6, and gate electrode 81 passes through the second front gate dielectric layer
82 are connected with positive N+ launch sites 4, positive p-type base 5 and positive N-type charge storage layer 7；The depth of the front trench gate structure
Junction depth of the degree more than positive p-type base 6 and the junction depth less than positive N-type charge storage layer 7；The front gate dielectric layer 82,83
Thickness be not more than front side emitter pole dielectric layer 72,73 thickness；The back side N-channel MOS structure and front N-channel MOS knot
The setting symmetrical above and below of transversal centerline of the structure along N-type drift region 9.
The following detailed description of its operation principle of explanation：
The two-way IGBT device of the present invention by controlling the grids of two symmetrical N-channel MOSs, i.e. positive gate electrode 81 respectively
With back side gate electrode 281, you can work in the full symmetric two-way IGBT patterns of characteristic.Therefore, in order to simplicity describe, below under
Mainly illustrated with electric current in Fig. 2 by back side emitter pole metal 21 to the direction that front side emitter pole metal 1 flows, other direction
Operation principle is identical, and those skilled in the art can be interchangeable according to general knowledge to corresponding content in explanation.
By controlling back side gate electrode 281 to make the channel cutoff of back side N-channel MOS structure, such back side N-channel MOS knot
Structure work is similar to the colelctor electrode of the unidirectional IGBT device of tradition；And front N-channel MOS arrangement works are similar to the unidirectional IGBT of tradition
The emitter stage of device, by controlling positive gate electrode 81 to realize being switched on and off for IGBT.
By introducing trench emitter structure and PXing Ti areas in the present invention, the emitter stage in the trench emitter structure
Electrode and metal electrode equipotential, the thickness of the emitter stage dielectric layer sum are more than the thickness of gate dielectric layer, are not influenceing IGBT
Device threshold voltage and in the case of opening：
1) reduces the width of gate electrode so that the width of gate electrode is less than the width of trench emitter electrode, reduces drive
Dynamic power consumption；
2) in device opens dynamic process, the semiconductor surface contacted with trench emitter dielectric layer will not form product
Tired or inversion layer, therefore device is not in negative differential capacity effect, avoids electric current, the voltage oscillation opened in dynamic process
With EMI problems, device reliability is improved；
3) reduces the depth of gate electrode, the depth of gate electrode is less than the junction depth of N-type charge storage layer, reduces grid
Pole-emitter capacity and grid-collector capacitance, so as to improve the switching speed of device, the switching loss of device is reduced,
Device is set to obtain the compromise characteristic between more preferable conduction voltage drop and switching loss simultaneously；
4) presence of thick dielectric layer improves the concentration of channel bottom electric field, improves the breakdown voltage of device；
5) presence in PXing Ti areas further reduces the extraction area in hole, improves the carrier enhancing of emitter terminal
Effect, improve the carrier concentration profile of whole N-type drift region, further improve between forward conduction voltage drop and turn-off power loss
Compromise.
In addition, the present invention may also be operated in bi-directional MOS pattern：By controlling back side gate electrode 281 to make back side N-channel MOS
The raceway groove of structure is opened, and such back side N-channel MOS arrangement works are similar to the drain electrode of the unidirectional MOS device of tradition；And positive N ditches
MOS structure work in road is similar to the source electrode of the unidirectional MOS device of tradition, by control positive gate electrode 81 realize MOS unlatching and
Shut-off.When working in bi-directional MOS pattern, the present invention also has operation principle during similar to two-way IGBT mode of operations and beneficial
Effect.
Embodiment 2：
Present embodiments provide a kind of two-way IGBT device, its structure cell as shown in figure 3, the present embodiment except positive P
The junction depth in Xing Ti areas 11 or back side PXing Ti areas 211 is more than the depth of trench emitter structure so that beyond trench emitter knot
The part of structure extends laterally to the N-type of the positive lower section of N-type charge storage layer 6 or the top of back side N-type charge storage layer 6 to side
Beyond in drift region 9, remaining structure is same as Example 1.
The present embodiment can further reduce the extraction area in hole, and the carrier injection for further improving emitter terminal increases
It is potent to answer, the compromise of more preferable device forward conduction voltage drop and switching loss can be obtained, and can further shield N-type layer to device
The adverse effect of part breakdown voltage, obtain higher device electric breakdown strength and reliability.
Embodiment 3：
Present embodiments provide a kind of two-way IGBT device, its structure cell as shown in figure 4, the present embodiment except front ditch
There is the second positive P-type layer 13 being attached thereto, backside trench grid structure and front trench gate structure along N-type below slot grid structure
The transversal centerline setting symmetrical above and below of drift region 9, remaining structure are same as Example 2.
Specifically, the positive back side P-type layer 213 of P-type layer 13 or second of the present embodiment second extends laterally to just to side
In the N-type drift region 9 of the lower section of face N-type charge storage layer 6 or the top of back side N-type charge storage layer 6.
The present embodiment introduces the second P-type layer 13 and the second back side P-type layer 213, can further shield grid-colelctor electrode
Between coupling, reduce grid-collector capacitance, improve the switching speed of device, reduce switching loss.
Embodiment 4：
A kind of two-way IGBT device is present embodiments provided, as figure 5 illustrates, the present embodiment compares embodiment 1 to its structure cell
Difference be：Also include front Split Electrode 84 and front Split Electrode dielectric layer 85, front point in the trench gate structure of front
Split that electrode 84 is located at the lower section of positive gate electrode 81 and the two is connected by the first front gate dielectric layer 82, front Split Electrode 84 with
It is connected between positive N-type charge storage layer 6 and positive N-type drift region 9 by front Split Electrode dielectric layer 85；Backside trench grid
Structure and the setting symmetrical above and below of transversal centerline of the front trench gate structure along N-type drift region 9.
On the one hand the presence of Split Electrode structure reduces grid-collector capacitance, improve switching speed, the drop of device
Low switching loss, channel bottom electric field concentration is on the other hand improved, improve the breakdown voltage of device.
Embodiment 5：
Present embodiments provide a kind of two-way IGBT device, its structure cell as shown in fig. 6, the present embodiment except positive P
The junction depth in Xing Ti areas 11 or back side PXing Ti areas 211 is more than the depth of trench emitter structure so that beyond trench emitter knot
The part of structure extends laterally to the N-type of the positive lower section of N-type charge storage layer 6 or the top of back side N-type charge storage layer 6 to side
Formed respectively in drift region 9 beyond the first positive back side P-type layer 212 of P-type layer 12 and first, remaining structure with the phase of embodiment 4
Together.
Embodiment 6：
Present embodiments provide a kind of two-way IGBT device, its structure cell as shown in fig. 7, the present embodiment except front ditch
There is the second positive P-type layer 13 being attached thereto, backside trench grid structure and front trench gate structure along N-type below slot grid structure
The transversal centerline setting symmetrical above and below of drift region 9, remaining structure are same as Example 4.
Embodiment 7：
A kind of two-way IGBT device is present embodiments provided, its structure cell is as shown in figure 8, the present embodiment compares embodiment
6 difference is：Positive trench emitter electrode 71 and front Split Electrode 84 are done into a ladder, the backside trench transmitting
Pole electrode 271 and back side Split Electrode 272 are done into a ladder, and the back side N-channel MOS structure has and front N-channel MOS
Structure is along the center line of N-type drift region 14 connection and setting symmetrical above and below；The present embodiment sets stepped electrode further to increase
The thickness of channel bottom dielectric layer, further reduces electric field, improves the breakdown voltage of device.
Embodiment 8：
A kind of two-way IGBT device is present embodiments provided, its structure cell is as shown in figure 9, the present embodiment compares embodiment
7 difference is：Positioned at the back side PXing Ti areas 211 of backside trench emitter structure both sides and backside trench grid structure and back side N
+ launch site 23, back side P+ launch sites 24, back side p-type base 25, back side N-type charge storage layer 26 exchange position, i.e., positive back side N
Transversal centerline specular of the channel MOS structure on N-type drift region 9.
Embodiment 9：
The present embodiment illustrates by taking the two-way IGBT of 1200V voltage class as an example, can be according to reality according to common sense in the field
Border demand prepares the device of different performance parameter.
Step 1：N-type drift region of the monocrystalline silicon piece as device, institute are lightly doped using two panels parameter and specification identical N-type
The thickness for selecting silicon chip is 300~600um, doping concentration 1013~1014Individual/cm3；Silicon chip surface deposition thickness be 700~
1000 nanometers of TEOS protective layers, make window by lithography and carry out groove silicon etching, and then etching formation is mutually only in N-type drift region
Vertical emitter trench and gate trench, the depth of emitter trench are more than the depth of gate trench；
Step 2：One layer of field oxide is grown in two panels silicon chip surface respectively using same process, is lithographically derived active area,
Then one layer of regrowth pre-oxidation layer, by emitter trench and between the gate trench of emitter trench side and institute
State gate trench bottom injection N-type impurity and be made N-type charge storage layer, the energy of ion implanting is 200~500keV, injectant
Measure as 1013~1014Individual/cm2；It is miscellaneous above N-type charge storage layer and positioned at the top layer implanting p-type of emitter trench opposite side again
Matter simultaneously makes annealing treatment is made p-type base and PXing Ti areas respectively, and the energy of ion implanting is 60~120keV, implantation dosage 1013
~1014Individual/cm2, annealing temperature is 1100~1150 DEG C, and annealing time is 10~30 minutes；
Step 3：In 1050 DEG C~1150 DEG C of O2Trench wall under atmosphere respectively in two panels silicon chip forms dielectric layer, and
After the depositing polysilicon in the groove of two panels silicon chip respectively at 750 DEG C~950 DEG C；Polysilicon and its week side of boss in emitter trench
Dielectric layer form trench emitter structure, polysilicon and its dielectric layer in outside form trench gate structure in gate trench；
Step 4：N+ transmittings are formed by photoetching, ion implanting N-type impurity on two panels silicon chip using same process respectively
Area, the N+ launch sites are located at p-type base upper surface and are connected with the dielectric layer of gate trench inwall；Distinguished using same process
Photoetching, ion implanting p type impurity form P+ launch sites on two panels silicon chip, and P+ launch sites are arranged side by side and mutually with N+ launch sites
Contact；The energy of ion implanting N-type impurity is 30~60keV, implantation dosage 1015~1016Individual/cm2, ion implanting p-type is miscellaneous
The energy of matter is 60~80keV, implantation dosage 1015~1016Individual/cm2, annealing temperature is 900 DEG C, and the time is 20~30 points
Clock；,
Step 5：Deposited respectively in two panels silicon chip surface using same process, and formed using photoetching, etching technics and be located at P
The first medium floor of Xing Ti areas upper surface and its mutually close emitter stage dielectric layer upper surface and positioned at trench gate structure upper table
The second dielectric layer in face；
Step 6：Metal is deposited in two panels silicon chip surface respectively using same process, and distinguished using photoetching, etching technics
The upper surface of trench gate structure, P+ launch sites, N+ launch sites and trench emitter electrode and its mutually close emitter stage dielectric layer
Form emitter metal；
Step 7：Two panels silicon chip is overturn, silicon wafer thickness is thinned using same process, is then subtracted this two panels is identical
Both are bonded together to form two-way IGBT device by the silicon chip back side after thin to the back side using bonding technology.
Further, in step 1 of the present invention can by increasing photoetching, etch step forms emitter trench and grid at twice
Pole groove.
Further, in step 2 of the present invention p-type base and PXing Ti areas can be formed at twice by increasing lithography step.
Further, in step 3 of the present invention trench emitter knot can be formed at twice by increasing oxidation and depositing step
Structure and trench gate structure.
Further, the control of etch process parameters can be passed through in trench etch process in the present invention so that channel bottom
The thickness of the thickness ratio trench top medium layer of dielectric layer is bigger.
Further, can be existed in step 4 of the present invention before N-type charge storage layer is formed by increasing ion implanting step
P-type layer is formed on emitter trench bottom, you can structure as shown in Figure 3 is made.
Further, can be existed in step 4 of the present invention before N-type charge storage layer is formed by increasing ion implanting step
P-type layer is formed respectively on emitter trench bottom and gate trench bottom, you can structure as shown in Figure 4 is made.
Further, can be by increasing etching, oxidation and depositing technics, inside trench gate structure in step 3 of the present invention
Introduce Split Electrode and Split Electrode dielectric layer, you can structure as shown in Figure 5 is made.
Further, can be by increasing etching, oxidation and depositing technics, inside trench gate structure in step 3 of the present invention
Split Electrode and Split Electrode dielectric layer are introduced, and can be noted before step 4 forms N-type charge storage layer by increasing ion
Enter step and form P-type layer in emitter trench bottom, you can structure as shown in Figure 6 is made.
Further, can be by increasing etching, oxidation and depositing technics, inside trench gate structure in step 3 of the present invention
Split Electrode and Split Electrode dielectric layer are introduced, and can be noted before step 4 forms N-type charge storage layer by increasing ion
Enter step and form P-type layer respectively in emitter trench bottom and gate trench bottom, you can structure as shown in Figure 7 is made.
Further, stepped groove transmitting can be formed by increasing etching, oxidation and depositing step in step 3 of the present invention
Pole electrode and steplike-gate electrode, you can structure as shown in Figure 8 is made.
Further, the first front dielectric layer 20, the second front dielectric layer 22, the first back side dielectric layer the 220, the 2nd 1 back of the body
Face dielectric layer 222, the first front gate dielectric layer 82, the second front gate dielectric layer 83, first back of the body front gate dielectric layer 282, second
Back side gate dielectric layer 283, the first front side emitter pole medium 72, the second front side emitter pole dielectric layer 73, the first back side emitter pole are situated between
Matter 272, the material of the second back side emitter pole dielectric layer 273 can be the same or different, and each several part material can use
Same material can also use combination of materials not of the same race,
Fig. 2 to Fig. 9 only provides several specific implementations based on core thinking of the present invention, those skilled in the art according to
General knowledge known in this field should be known that in two-way IGBT device provided by the invention that semi-conducting material used in device can use silicon
(Si), carborundum (SiC), GaAs (GaAs) or gallium nitride (GaN) etc. are achieved, and dielectric material used can use two
Silica (SiO2), hafnium oxide (HfO2) or silicon nitride (Si3N4) etc. be achieved, manufacturing technology steps also can be according to reality
Border needs to be adjusted.
Claims (10)
1. a kind of two-way IGBT, its structure cell include：It is symmetricly set on the N-channel MOS of N-type drift region (9) front and back
Structure；Front N-channel MOS structure includes front side emitter pole metal (1), the first front dielectric layer (20), the second front dielectric layer
(22), positive trench emitter structure, front trench gate structure, positive P+ launch sites (3), positive N+ launch sites (4), positive P
Type base (5) and positive N-type charge storage layer (6) and positive PXing Ti areas (11)；Back side N-channel MOS structure includes back side emitter
Pole metal (21), the first back side dielectric layer (220), the second back side dielectric layer (222), backside trench emitter structure, back side ditch
Slot grid structure, back side P+ launch sites (23), back side N+ launch sites (24), back side p-type base (25) and back side N-type charge storage layer
And back side PXing Ti areas (211) (26)；It is characterized in that：
Positive trench emitter structure is located among N-type drift region (9) upper surface, and front trench gate structure is located at N-type drift region
(9) side of upper surface, have between positive trench emitter structure and front trench gate structure and contact with each other and be arranged side by side
Positive P+ launch sites (3) and positive N+ launch sites (4), the lower section of positive P+ launch sites (3) and positive N+ launch sites (4) have
The positive p-type base (5) being attached thereto, there is the storage of positive N-type electric charge between positive p-type base (5) and N-type drift region (9)
Layer (6)；The upper surface of positive P+ launch sites (3) and positive N+ launch sites (4) is connected with front side emitter pole metal (1), positive p-type
Body area (11) is connected with positive trench emitter structure and positioned at the opposite side of N-type drift region (9) upper surface, positive PXing Ti area
(11) upper surface is connected with the first front dielectric layer (20), and the first front dielectric layer (20) is connected with front side emitter pole metal (1)；
The positive trench emitter structure includes：Positive trench emitter electrode (71) and the first front side emitter pole dielectric layer (72) and
Second front side emitter pole dielectric layer (73)；Positive trench emitter electrode (71) by the first front side emitter pole dielectric layer (72) with
PXing Ti areas (11) are connected, and positive trench emitter electrode (71) is sent out by the second front side emitter pole dielectric layer (73) and positive P+
Area (3), positive p-type base (5) and positive N-type charge storage layer (7) is penetrated to be connected；The front trench gate structure includes：Front
Gate electrode (81) and the first front gate dielectric layer (83) and the second front gate dielectric layer (82), gate electrode (81) pass through the first front
Gate dielectric layer (83) is connected with positive N-type charge storage layer (6), and gate electrode (81) is by the second front gate dielectric layer (82) and just
Face N+ launch sites (4), positive p-type base (5) and positive N-type charge storage layer (7) are connected；The depth of the front trench gate structure
Junction depth of the degree more than positive p-type base (6) and the junction depth less than positive N-type charge storage layer (7)；The front gate dielectric layer
The thickness of (82,83) is not more than the thickness of front side emitter pole dielectric layer (72,73)；The back side N-channel MOS structure and positive N
Channel MOS structure is identical.
A kind of 2. two-way IGBT according to claim 1, it is characterised in that：Positive PXing Ti areas (11) or back side p-type body
The junction depth in area (211) is more than the depth of trench emitter structure, is extended laterally beyond the part of trench emitter structure to side
In N-type drift region (9) below to positive N-type charge storage layer (6) or above back side N-type charge storage layer (6).
A kind of 3. two-way IGBT according to claim 1, it is characterised in that：Also have therewith below the trench gate structure of front
Connected the second P-type layer (13), the N that the second P-type layer (13) is extended laterally to below positive N-type charge storage layer (6) to side
In type drift region (9)；Backside trench grid structure and transversal centerline of the front trench gate structure along N-type drift region (9) are symmetrical above and below
Set.
A kind of 4. two-way IGBT according to claim 1, it is characterised in that：Front trench gate structure also includes front division
Electrode (84) and front Split Electrode dielectric layer (85), front Split Electrode (84) is located at below positive gate electrode (81) and the two
It is connected by the first front gate dielectric layer (83), front Split Electrode (84) and positive N-type charge storage layer (6) and positive N-type
It is connected between drift region (9) by front Split Electrode dielectric layer (85)；Backside trench grid structure and front trench gate structure are along N
The transversal centerline setting symmetrical above and below of type drift region (9).
A kind of 5. two-way IGBT according to claim 1, it is characterised in that：Positive trench emitter electrode (71) and the back side
Emitter electrode (271) is step structure wide at the top and narrow at the bottom.
A kind of 6. two-way IGBT according to claim 1, it is characterised in that：Front Split Electrode (84) and back side division electricity
Pole is up-narrow and down-wide step structure.
A kind of 7. two-way IGBT according to claim 1, it is characterised in that：The junction depth of positive N-type charge storage layer (6) is small
In the depth of positive trench emitter electrode (71).
A kind of 8. two-way IGBT according to claim 1, it is characterised in that：The depth of trench emitter structure be less than or
Equal to the junction depth in PXing Ti areas.
A kind of 9. two-way IGBT according to claim 1, it is characterised in that：The width of the gate electrode (81) is less than groove
The width of emitter electrode (71).
10. a kind of two-way IGBT manufacture method, it is characterised in that comprise the following steps：
Step 1：N-type drift region of the monocrystalline silicon piece as device is lightly doped using two parameters and specification identical N-type, in silicon chip
Surface deposition protective layer, make window by lithography and carry out groove silicon etching, and then etching forms separate hair in N-type drift region
Emitter-base bandgap grading groove and gate trench, the depth of emitter trench are more than the depth of gate trench；
Step 2：One layer of field oxide is being grown through the two panels silicon chip surface obtained by step 1 processing using same process respectively,
Active area is lithographically derived, then one layer of pre-oxidation layer of regrowth, by emitter trench and positioned at emitter trench side
N-type charge storage layer is made between gate trench and gate trench bottom injection N-type impurity；Again in N-type charge storage layer
Top and top layer implanting p-type impurity positioned at emitter trench opposite side simultaneously make annealing treatment p-type base and p-type body are made respectively
Area；
Step 3：Using same process, the trench wall on two panels silicon chip forms dielectric layer respectively, is existed respectively using same process
Depositing polysilicon in groove on two panels silicon chip, polysilicon and its dielectric layer of the week side of boss form trench emitter in emitter trench
Structure, polysilicon and its dielectric layer in outside form trench gate structure in gate trench；
Step 4：Using same process, photoetching, ion implanting N-type impurity form N+ launch sites, the N+ on two panels silicon chip respectively
Launch site is located at p-type base upper surface and is connected with the dielectric layer of gate trench inwall；Using same process respectively in two panels silicon
Photoetching, ion implanting p type impurity form P+ launch sites on piece, and P+ launch sites are arranged side by side and contacted with each other with N+ launch sites；
Step 5：Using same process, in two panels silicon chip surface dielectric layer deposited, and be lithographically formed positioned at PXing Ti areas upper surface and
The first medium layer of its mutually close emitter stage dielectric layer upper surface and the second dielectric layer positioned at trench gate structure upper surface；
Step 6：Using same process, metal is deposited in two panels silicon chip surface, and formed using photoetching, etching technics and be located at groove
Grid structure, P+ launch sites, N+ launch sites and trench emitter electrode and its transmitting of mutually close emitter stage dielectric layer upper surface
Pole metal；
Step 7：Overturn two panels silicon chip, silicon wafer thickness is thinned using same process, then by this two panels it is identical be thinned after
Silicon chip back side to the back side, both are bonded together to form into two-way IGBT device using bonding technology.
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