CN111211169A - Shielded IGBT structure and manufacturing method thereof - Google Patents

Shielded IGBT structure and manufacturing method thereof Download PDF

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CN111211169A
CN111211169A CN202010120892.4A CN202010120892A CN111211169A CN 111211169 A CN111211169 A CN 111211169A CN 202010120892 A CN202010120892 A CN 202010120892A CN 111211169 A CN111211169 A CN 111211169A
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朱袁正
周锦程
李宗清
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Wuxi NCE Power Co Ltd
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Wuxi NCE Power Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The invention relates to a shielded IGBT structure and a manufacturing method thereof, and the shielded IGBT structure comprises collector metal, a P-type collector region, an N-type buffer layer, an N-type epitaxial layer, an N-type accumulation layer, a P-type body region, a first type groove, a second type groove, first type conductive polycrystalline silicon, second type conductive polycrystalline silicon, a gate oxide layer, an N-type source region, an insulating medium layer and emitter metal; the first type of groove and the second type of groove are arranged at intervals, the first type of groove sequentially penetrates through the P-type body region and the N-type accumulation layer from the upper surface of the N-type source region and finally enters the N-type epitaxial layer, the side surface and the bottom surface of the first type of groove are provided with a gate oxide layer, and the gate oxide layer wraps the first type of conductive polysilicon; the second type of groove penetrates through the P type body region from the upper surface of the N type source region and finally enters the N type accumulation layer, the side surface and the bottom surface of the second type of groove are provided with a gate oxide layer, and the gate oxide layer wraps the second type of conductive polysilicon. The grid capacitance of the device is extremely small, the switching loss is small, and the reliability of the device is greatly improved.

Description

Shielded IGBT structure and manufacturing method thereof
Technical Field
The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a shielding type IGBT structure and a manufacturing method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is used as a Bipolar device controlled by an Insulated Gate, and the higher the concentration of non-equilibrium carriers in the body, the more significant the conductivity modulation effect of the IGBT is, and the higher the current density of the IGBT is. In order to improve the concentration of the unbalanced carriers, a common method is to arrange a high-concentration N-type impurity-doped accumulation layer below a P-type body region, which enhances the conductivity modulation effect of a drift region and reduces the forward voltage drop, but the method can obviously increase the switching loss of the device, and after the concentration of the unbalanced carriers is improved, the unbalanced carriers can influence the grid potential in the short-circuit process of the IGBT, so that the grid potential is severely vibrated, and the reliability of the device is influenced.
The existing IGBT structure is shown in fig. 14, and includes a collector metal 1, a P-type collector region 2, an N-type buffer layer 3, and an N-type epitaxial layer 4 are sequentially disposed on the collector metal 1, gate trenches are disposed on the upper surface of the N-type epitaxial layer 4 at intervals, an N-type accumulation layer 5 is disposed on the upper surface of the N-type epitaxial layer 4, a P-type body region 6 is disposed on the upper surface of the N-type accumulation layer 5, an N-type source region 12 is disposed on the upper surface of the P-type body region 6, and the gate trenches sequentially penetrate through the N-type source region 12, the P-type body region 6, and the N-type accumulation layer 5 from the upper surface of the N-type epitaxial layer 4 and finally enter. An insulating medium layer 13 is arranged on the top of the epitaxial layer and the top of the groove, an emitter metal 14 is arranged above the insulating medium layer 13, and the emitter metal 14 is in ohmic contact with the P-type body region 6 and the N-type source region 12 through a through hole between two adjacent grooves.
In the traditional IGBT structure, the depth of a grid groove is deeper, so that the grid capacitance is larger, the switching loss is increased, and the contact area between the grid groove and the N-type accumulation layer 5 and the contact area between the grid groove and the N-type epitaxial layer 4 are larger, so that the grid potential is easily influenced by carriers, and the reliability of a device is reduced.
Therefore, a new IGBT cell structure is needed to avoid the adverse effect of the carrier storage layer on the IGBT switching loss and short-circuit reliability.
Disclosure of Invention
One of the objectives of the present invention is to overcome the disadvantages of the prior art, and to provide a shielded IGBT structure capable of reducing switching loss and improving reliability in a short circuit process.
Another object of the present invention is to provide a method for manufacturing a shielded IGBT structure.
According to the technical scheme provided by the invention, the shielding type IGBT structure comprises collector metal, a P-type collector region, an N-type buffer layer, an N-type epitaxial layer, an N-type accumulation layer, a P-type body region, a first type groove, a second type groove, first type conductive polycrystalline silicon, second type conductive polycrystalline silicon, a gate oxide layer, an N-type source region, an insulating medium layer and emitter metal;
the collector comprises a collector metal, a collector metal and an emitter metal, wherein a P-type collector region is arranged on the upper surface of the collector metal, an N-type buffer layer is arranged on the upper surface of the P-type collector region, an N-type epitaxial layer is arranged on the upper surface of the N-type buffer layer, an N-type accumulation layer is arranged on the upper surface of the N-type epitaxial layer, a P-type body region is arranged on the upper surface of the N-type accumulation layer, an N-type source region is arranged on the upper surface of the P-type body region, an insulating medium layer is arranged on the upper surface of the N-type source;
the first type of groove and the second type of groove are arranged at intervals, the first type of groove sequentially penetrates through the P-type body region and the N-type accumulation layer from the upper surface of the N-type source region and finally enters the N-type epitaxial layer, the side surface and the bottom surface of the first type of groove are provided with a gate oxide layer, and the gate oxide layer wraps the first type of conductive polysilicon; the second type of groove penetrates through the P type body region from the upper surface of the N type source region and finally enters the N type accumulation layer, a gate oxide layer is arranged on the side surface and the bottom surface of the second type of groove, and the second type of conductive polysilicon is wrapped by the gate oxide layer;
the emitting electrode metal is in ohmic contact with the N-type source region and the P-type body region through a first emitting electrode metal connecting column between two adjacent grooves, and the emitting electrode metal is in ohmic contact with the first type of conductive polycrystalline silicon through a second emitting electrode metal connecting column.
Preferably, at least one first-type groove is arranged between two adjacent second-type grooves.
Preferably, at least one second-type groove is arranged between two adjacent first-type grooves.
Preferably, the second type of conductive polysilicon is connected to a gate potential.
Preferably, the resistivity of the N-type accumulation layer is smaller than that of the N-type epitaxial layer, and the resistivity of the N-type buffer layer is smaller than that of the N-type epitaxial layer.
A manufacturing method of a shielding type IGBT structure comprises the following steps:
the method comprises the following steps: providing an N-type epitaxial layer;
step two: injecting N-type impurities at high energy, and then carrying out thermal annealing to form an N-type accumulation layer;
step three: selectively etching first type grooves on the N-type epitaxial layer and the N-type accumulation layer, and selectively etching second type grooves on the N-type accumulation layer to enable the second type grooves and the first type grooves to be arranged at intervals;
step four: forming a gate oxide layer on the upper surface of the N-type accumulation layer and the side surfaces and the bottom surfaces of the first type groove and the second type groove;
step five: depositing conductive polysilicon on the upper surface of the N-type accumulation layer and in the first-type groove and the second-type groove;
step six: etching off redundant conductive polysilicon, and only reserving the conductive polysilicon in the first type of groove and the second type of groove to form first type of conductive polysilicon and second type of conductive polysilicon;
step seven: injecting P-type impurities into the N-type accumulation layer, then carrying out thermal annealing to form a P-type body region, then injecting N-type impurities into the P-type body region, and activating to form an N-type source region;
step eight: depositing an insulating medium layer on the upper surface of the N-type source region;
step nine: selectively etching the insulating medium layer, the N-type source region and the P-type body region to form a first through hole, and selectively etching the insulating medium layer to form a second through hole;
step ten: forming emitter metal on the upper surface of the insulating medium layer, forming a first emitter metal connecting column by the emitter metal material in the first through hole, and forming a second emitter metal connecting column by the emitter metal material in the second through hole;
step eleven: injecting N-type impurities and P-type impurities into the back surface of the N-type epitaxial layer, and activating to form a P-type collector region and an N-type buffer layer;
step twelve: a collector metal is formed on the lower surface of the P-type collector region.
Compared with the prior art, the invention has the following advantages:
the depth of the second type of groove is shallow, so that the contact area between the gate oxide layer and the N-type accumulation layer is small, the grid capacitance of the device is extremely small, the switching loss is small, and meanwhile, the grid potential is not easily influenced by current carriers, so that the reliability of the device is greatly improved.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of an N-type epitaxial layer provided in the first step of embodiment 1.
Fig. 2 is a schematic cross-sectional structure diagram of the second step of forming the N-type accumulation layer in embodiment 1.
Fig. 3 is a schematic cross-sectional structure diagram of the first-type trench and the second-type trench formed in step three in embodiment 1.
Fig. 4 is a schematic cross-sectional structural diagram of the gate oxide layer formed on the surface of the device in the fourth step in example 1.
Fig. 5 is a schematic cross-sectional structure diagram of the conductive polysilicon deposition in the fifth step in embodiment 1.
Fig. 6 is a schematic cross-sectional structure diagram of the first conductive polysilicon and the second conductive polysilicon formed in step six of embodiment 1.
Fig. 7 is a schematic cross-sectional structure diagram of the P-type body region and the N-type source region formed in step seven of embodiment 1.
FIG. 8 is a schematic cross-sectional view showing the deposition of an insulating dielectric layer in step eight of example 1.
Fig. 9 is a schematic cross-sectional structure diagram of the formation of the through-hole in step nine in example 1.
Fig. 10 is a schematic cross-sectional structure diagram of the ten steps of forming the emitter metal in example 1.
Fig. 11 is a schematic cross-sectional structure diagram of forming a P-type collector region and an N-type buffer layer in step eleven in embodiment 1.
Fig. 12 is a diagram of a finished shielded IGBT structure according to example 1 (i.e., a schematic cross-sectional structure of a collector metal formed in step twelve).
Fig. 13 is a diagram of a finished shielded IGBT structure according to embodiment 2.
Fig. 14 is a schematic diagram of a conventional IGBT structure.
Detailed Description
The present invention will be further described with reference to the following specific examples.
Example 1
A shielding type IGBT structure comprises a collector metal 1, a P type collector region 2, an N type buffer layer 3, an N type epitaxial layer 4, an N type accumulation layer 5, a P type body region 6, a first type groove 7, a second type groove 8, a first type conductive polycrystalline silicon 9, a second type conductive polycrystalline silicon 10, a gate oxide layer 11, an N type source region 12, an insulating medium layer 13 and an emitter metal 14;
a P-type collector region 2 is arranged on the upper surface of a collector metal 1, an N-type buffer layer 3 is arranged on the upper surface of the P-type collector region 2, an N-type epitaxial layer 4 is arranged on the upper surface of the N-type buffer layer 3, an N-type accumulation layer 5 is arranged on the upper surface of the N-type epitaxial layer 4, a P-type body region 6 is arranged on the upper surface of the N-type accumulation layer 5, an N-type source region 12 is arranged on the upper surface of the P-type body region 6, an insulating medium layer 13 is arranged on the upper surface of the N-type source region 12, and an emitter metal 14 is arranged on the upper surface of the insulating medium layer 13;
the first-type grooves 7 and the second-type grooves 8 are arranged at intervals, the first-type grooves 7 sequentially penetrate through the P-type body region 6 and the N-type accumulation layer 5 from the upper surface of the N-type source region 12 and finally enter the N-type epitaxial layer 4, gate oxide layers 11 are arranged on the side surfaces and the bottom surface of the first-type grooves 7, and the first-type conductive polycrystalline silicon 9 is wrapped by the gate oxide layers 11; the second type groove 8 penetrates through the P type body region 6 from the upper surface of the N type source region 12 and finally enters the N type accumulation layer 5, a gate oxide layer 11 is arranged on the side surface and the bottom surface of the second type groove 8, and the second type conductive polysilicon 10 is wrapped by the gate oxide layer 11;
the emitter metal 14 is in ohmic contact with the N-type source region 12 and the P-type body region 6 through a first emitter metal connection column between two adjacent trenches, and the emitter metal 14 is in ohmic contact with the first type of conductive polysilicon 9 through a second emitter metal connection column.
A first groove 7 is arranged between two adjacent second grooves 8.
A second type groove 8 is arranged between two adjacent first type grooves 7.
The second type of conductive polysilicon 10 is connected to the gate potential.
The resistivity of the N-type accumulation layer 5 is smaller than that of the N-type epitaxial layer 4, and the resistivity of the N-type buffer layer 3 is smaller than that of the N-type epitaxial layer 4.
The manufacturing method of the shielding type IGBT structure comprises the following steps:
the method comprises the following steps: providing an N-type epitaxial layer 4;
step two: injecting N-type impurities at high energy, and then carrying out thermal annealing to form an N-type accumulation layer 5;
step three: selectively etching a first type groove 7 on the N-type epitaxial layer 4 and the N-type accumulation layer 5, and selectively etching a second type groove 8 on the N-type accumulation layer 5, so that the second type groove 8 and the first type groove 7 are arranged at intervals;
step four: forming a gate oxide layer 11 on the upper surface of the N-type accumulation layer 5 and the side surfaces and the bottom surfaces of the first-type groove 7 and the second-type groove 8;
step five: depositing conductive polysilicon on the upper surface of the N-type accumulation layer 5 and in the first-type groove 7 and the second-type groove 8;
step six: etching off redundant conductive polysilicon, and only reserving the conductive polysilicon in the first type of groove 7 and the second type of groove 8 to form first type of conductive polysilicon 9 and second type of conductive polysilicon 10;
step seven: injecting P-type impurities into the N-type accumulation layer 5, then performing thermal annealing to form a P-type body region 6, then injecting N-type impurities into the P-type body region 6, and activating to form an N-type source region 12;
step eight: depositing an insulating medium layer 13 on the upper surface of the N-type source region 12;
step nine: selectively etching the insulating medium layer 13, the N-type source region 12 and the P-type body region 6 to form a first through hole, and selectively etching the insulating medium layer 13 to form a second through hole;
step ten: forming emitter metal 14 on the upper surface of the insulating medium layer 13, forming a first emitter metal connecting column by the emitter metal material in the first through hole, and forming a second emitter metal connecting column by the emitter metal material in the second through hole;
step eleven: injecting N-type impurities and P-type impurities into the back surface of the N-type epitaxial layer 4, and activating to form a P-type collector region 2 and an N-type buffer layer 3;
step twelve: a collector metal 1 is formed on the lower surface of the P type collector region 2.
Example 2
The structure of the shielded IGBT in this embodiment is basically the same as that in embodiment 1, and the differences are: three first-type grooves 7 are arranged in the middle of two adjacent second-type grooves 8.
The present invention and its embodiments have been described above, the description is not intended to be limiting, and the embodiments shown in the drawings are only two embodiments of the present invention, and the actual configuration is not limited thereto. In summary, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (6)

1. A shielding type IGBT structure is characterized in that: the collector comprises a collector metal (1), a P-type collector region (2), an N-type buffer layer (3), an N-type epitaxial layer (4), an N-type accumulation layer (5), a P-type body region (6), a first type groove (7), a second type groove (8), a first type conductive polycrystalline silicon (9), a second type conductive polycrystalline silicon (10), a gate oxide layer (11), an N-type source region (12), an insulating dielectric layer (13) and an emitter metal (14);
the collector structure comprises a collector metal (1), a P-type collector region (2) is arranged on the upper surface of the collector metal (1), an N-type buffer layer (3) is arranged on the upper surface of the P-type collector region (2), an N-type epitaxial layer (4) is arranged on the upper surface of the N-type buffer layer (3), an N-type accumulation layer (5) is arranged on the upper surface of the N-type epitaxial layer (4), a P-type body region (6) is arranged on the upper surface of the N-type accumulation layer (5), an N-type source region (12) is arranged on the upper surface of the P-type body region (6), an insulating medium layer (13) is arranged on the upper surface of the N-type source region (12), and an emitter metal (14) is arranged on the;
the first-class grooves (7) and the second-class grooves (8) are arranged at intervals, the first-class grooves (7) sequentially penetrate through the P-type body region (6) and the N-type accumulation layer (5) from the upper surface of the N-type source region (12) and finally enter the N-type epitaxial layer (4), gate oxide layers (11) are arranged on the side surfaces and the bottom surface of the first-class grooves (7), and the first-class conductive polycrystalline silicon (9) is wrapped by the gate oxide layers (11); a second type groove (8) penetrates through the P type body region (6) from the upper surface of the N type source region (12) and finally enters the N type accumulation layer (5), a gate oxide layer (11) is arranged on the side surface and the bottom surface of the second type groove (8), and the second type conductive polycrystalline silicon (10) is wrapped by the gate oxide layer (11);
the emitter metal (14) is in ohmic contact with the N-type source region (12) and the P-type body region (6) through a first emitter metal connecting column between two adjacent grooves, and the emitter metal (14) is in ohmic contact with the first type of conductive polycrystalline silicon (9) through a second emitter metal connecting column.
2. The shielded IGBT structure of claim 1, wherein: at least one first-type groove (7) is arranged between two adjacent second-type grooves (8).
3. The shielded IGBT structure of claim 1, wherein: at least one second groove (8) is arranged between two adjacent first grooves (7).
4. The shielded IGBT structure of claim 1, wherein: the second type of conductive polysilicon (10) is connected to a gate potential.
5. The shielded IGBT structure of claim 1, wherein: the resistivity of the N-type accumulation layer (5) is smaller than that of the N-type epitaxial layer (4), and the resistivity of the N-type buffer layer (3) is smaller than that of the N-type epitaxial layer (4).
6. A manufacturing method of a shielding type IGBT structure comprises the following steps:
the method comprises the following steps: providing an N-type epitaxial layer (4);
step two: injecting N-type impurities at high energy, and then carrying out thermal annealing to form an N-type accumulation layer (5);
step three: selectively etching a first type of groove (7) on the N-type epitaxial layer (4) and the N-type accumulation layer (5), and selectively etching a second type of groove (8) on the N-type accumulation layer (5), so that the second type of groove (8) and the first type of groove (7) are arranged at intervals;
step four: forming a gate oxide layer (11) on the upper surface of the N-type accumulation layer (5) and the side surfaces and the bottom surfaces of the first-type groove (7) and the second-type groove (8);
step five: depositing conductive polysilicon on the upper surface of the N-type accumulation layer (5) and in the first type groove (7) and the second type groove (8);
step six: etching off redundant conductive polysilicon, and only keeping the conductive polysilicon in the first type groove (7) and the second type groove (8) to form first type conductive polysilicon (9) and second type conductive polysilicon (10);
step seven: injecting P-type impurities into the N-type accumulation layer (5), then carrying out thermal annealing to form a P-type body region (6), then injecting N-type impurities into the P-type body region (6), and activating to form an N-type source region (12);
step eight: depositing an insulating medium layer (13) on the upper surface of the N-type source region (12);
step nine: selectively etching the insulating medium layer (13), the N-type source region (12) and the P-type body region (6) to form a first through hole, and selectively etching the insulating medium layer (13) to form a second through hole;
step ten: forming emitter metal (14) on the upper surface of the insulating medium layer (13), forming a first emitter metal connecting column by the emitter metal material in the first through hole, and forming a second emitter metal connecting column by the emitter metal material in the second through hole;
step eleven: injecting N-type impurities and P-type impurities into the back surface of the N-type epitaxial layer (4), and activating to form a P-type collector region (2) and an N-type buffer layer (3);
step twelve: a collector metal (1) is formed on the lower surface of the P-type collector region (2).
CN202010120892.4A 2020-02-26 2020-02-26 Shielded IGBT structure and manufacturing method thereof Withdrawn CN111211169A (en)

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Cited By (4)

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CN112670335A (en) * 2020-12-30 2021-04-16 无锡紫光微电子有限公司 Super-junction shielding gate structure IGBT manufactured through multiple times of epitaxy and manufacturing method
WO2022067618A1 (en) * 2020-09-30 2022-04-07 苏州东微半导体有限公司 Semiconductor power device
CN114335170A (en) * 2020-09-30 2022-04-12 苏州东微半导体股份有限公司 Semiconductor power device
CN117293172A (en) * 2023-11-24 2023-12-26 华羿微电子股份有限公司 Double-groove high-performance MOSFET device and preparation method

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CN109427869A (en) * 2017-08-29 2019-03-05 昆仑芯电子科技(深圳)有限公司 A kind of semiconductor devices
CN107768434A (en) * 2017-10-20 2018-03-06 电子科技大学 A kind of two-way IGBT and its manufacture method
CN108321193A (en) * 2018-02-05 2018-07-24 电子科技大学 A kind of trench gate charge storage type IGBT and preparation method thereof
CN110350023A (en) * 2018-04-05 2019-10-18 三菱电机株式会社 Semiconductor device and power-converting device
CN211265485U (en) * 2020-02-26 2020-08-14 无锡新洁能股份有限公司 Shielding type IGBT structure

Cited By (5)

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WO2022067618A1 (en) * 2020-09-30 2022-04-07 苏州东微半导体有限公司 Semiconductor power device
CN114335170A (en) * 2020-09-30 2022-04-12 苏州东微半导体股份有限公司 Semiconductor power device
CN112670335A (en) * 2020-12-30 2021-04-16 无锡紫光微电子有限公司 Super-junction shielding gate structure IGBT manufactured through multiple times of epitaxy and manufacturing method
CN117293172A (en) * 2023-11-24 2023-12-26 华羿微电子股份有限公司 Double-groove high-performance MOSFET device and preparation method
CN117293172B (en) * 2023-11-24 2024-03-08 华羿微电子股份有限公司 Double-groove high-performance MOSFET device and preparation method

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Application publication date: 20200529