CN114335170A - Semiconductor power device - Google Patents
Semiconductor power device Download PDFInfo
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- CN114335170A CN114335170A CN202011069972.8A CN202011069972A CN114335170A CN 114335170 A CN114335170 A CN 114335170A CN 202011069972 A CN202011069972 A CN 202011069972A CN 114335170 A CN114335170 A CN 114335170A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 210000000746 body region Anatomy 0.000 claims description 7
- 238000003860 storage Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 36
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention belongs to the technical field of semiconductor devices, and particularly discloses a semiconductor power device, which comprises: a cell region and a gate bus region, the cell region including a plurality of periodically arranged cells, the cells including: the n-type epitaxial layer comprises two first grooves and two second grooves, wherein the two first grooves are positioned in the n-type epitaxial layer, the two second grooves are positioned between the two first grooves, and the depth of each second groove is smaller than that of each first groove; the second trench extends into the gate bus region, and the width of the second trench in the gate bus region is greater than that in the cell region. The invention can reduce the risk of failure of the semiconductor power device caused by gate-source leakage.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a semiconductor power device.
Background
The key parameters of the semiconductor power device comprise a starting voltage (Vth), an on-resistance (Rdson), a source-drain breakdown voltage (BVdss), a gate-source leakage (Igss), a source-drain leakage (Idss) and the like, wherein the gate-source leakage is a very important parameter for measuring the performance of the semiconductor power device, the gate-source leakage is required to be less than 100nA in the common semiconductor power device, if the gate-source leakage is larger, the power consumption is increased slightly, the service life of the device is shortened, and if the gate-source leakage is larger, the gate-source short circuit is caused seriously, so that the device cannot work normally. In the failure project of the semiconductor power device, the gate-source leakage is one of the problems which are very difficult to solve.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor power device to reduce the risk of the failure of the semiconductor power device caused by gate-source leakage in the prior art.
To achieve the above object of the present invention, the present invention provides a semiconductor power device comprising: a cell region and a gate bus region, the cell region including a plurality of periodically arranged cells, the cells including:
an n-type epitaxial layer;
two first trenches in the n-type epitaxial layer and two second trenches between the two first trenches, wherein the depth of the second trenches is smaller than that of the first trenches;
the second groove extends into the grid bus area, and the width of the second groove in the grid bus area is larger than that of the second groove in the cell area;
the insulating layer and the conducting layer are positioned in the first groove;
the gate dielectric layer and the gate electrode are positioned in the second groove;
the p-type body region is positioned in the n-type epitaxial layer and is arranged between the two second grooves;
an n-type emitter region within the p-type body region.
Optionally, the first trench is adjacent to the second trench, and the gate is insulated and isolated from the conductive layer.
Optionally, the semiconductor power device further includes a p-type collector region, and the n-type epitaxial layer is located above the p-type collector region.
Optionally, the semiconductor power device further includes an n-type charge storage layer located in the n-type epitaxial layer, and the n-type charge storage layer is located on one side of the second trench close to the p-type collector region.
Optionally, the first trench and the second trench are separated by the n-type epitaxial layer.
Optionally, the device further includes a p-type doped region, where the p-type doped region is located in the n-type epitaxial layer between the first trench and the second trench.
Optionally, the two second trenches are connected in the gate bus region.
Optionally, the conductive layer is externally connected with a source voltage, and the gate is externally connected with a gate voltage.
According to the semiconductor power device, the width of the second groove in the grid bus area is larger than that of the second groove in the cellular area, the grid dielectric layer and the grid are formed in the second groove, the grid can be led out more easily, the thickness of an interlayer isolation layer between a grid lead and an n-type emitting area is increased, and the risk of failure of the semiconductor power device caused by grid source leakage is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments.
Fig. 1 is a schematic top-view structural diagram of a first embodiment of a semiconductor power device provided by the present invention;
fig. 2 is a schematic top view of a semiconductor power device according to a second embodiment of the present invention;
fig. 3 is a schematic top-view structural diagram of a third embodiment of the semiconductor power device provided by the present invention;
FIG. 4 is a schematic cross-sectional view along AA in FIG. 1;
fig. 5 is a schematic cross-sectional view along the BB direction in fig. 2.
Detailed Description
The technical solution of the present invention will be fully described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof. Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic drawings listed in the accompanying drawings enlarge the thickness of the layers and regions of the present invention, and the listed sizes of the figures do not represent actual sizes.
Fig. 1 is a schematic top-view structure diagram of a first embodiment of a semiconductor power device provided by the present invention, fig. 2 is a schematic top-view structure diagram of a second embodiment of the semiconductor power device provided by the present invention, fig. 3 is a schematic top-view structure diagram of a third embodiment of the semiconductor power device provided by the present invention, fig. 4 is a schematic cross-sectional structure diagram of fig. 1 along direction AA, and fig. 5 is a schematic cross-sectional structure diagram of fig. 2 along direction BB. For convenience of illustration, fig. 1 to 5 are schematic top-view structural diagrams illustrating only a part of the region of the semiconductor power device of the present invention. As shown in fig. 1 to 5, the semiconductor power device of the present invention includes a cell region 31 and a gate bus region 32. The cell region 31 includes a plurality of periodically arranged cells 200 (shown in fig. 4 and 5), and only one cell 200 is exemplarily shown in the embodiment of the present invention.
The cell 200 includes an n-type epitaxial layer 22, two first trenches 11 located in the n-type epitaxial layer 22, and two second trenches 12 located between the two first trenches 11, wherein the depth of the second trenches 12 is smaller than the depth of the first trenches 11, and preferably, the depth of the first trenches 11 is greater than the depth of the second trenches 12 by 0.5um, and at this time, the semiconductor power device has the maximum breakdown voltage. The second trench 12 extends into the gate bus region 32, and the width of the second trench 12 in the gate bus region 32 is greater than that in the cell region 31, fig. 3 exemplarily shows the maximum limit of the width of the second trench 12 in the gate bus region 32, and the two second trenches 12 are connected in the gate bus region 32. The first trench 11 may also extend into the gate bus region 32, as shown in fig. 1 to 3.
An insulating layer 23 and a conductive layer 24 are disposed in the first trench 11, and the conductive layer 24 is usually connected to an external source voltage for increasing the breakdown voltage of the semiconductor power device. A gate dielectric layer 25 and a gate 26 are disposed in the second trench 12, and the gate 26 is usually connected to a gate voltage for controlling the on and off of a current channel of the semiconductor power device.
The cell 200 further includes a p-type body region 27 located within the n-type epitaxial layer 22 and between the two second trenches 12, and an n-type emitter region 28 is located within the p-type body region 27. The first trench 11 in the semiconductor power device of the present invention may be adjacent to the second trench 12, and the gate 26 is insulated from the conductive layer 24, as shown in fig. 1 and 4, and in fig. 4, the gate 26 is insulated from the conductive layer 24 by the insulating layer 23.
The first trench 11 and the second trench 12 in the semiconductor power device of the present invention may also be separated by an n-type epitaxial layer 22, as shown in fig. 2, 3 and 5. Separating the first trench 11 from the second trench 12 can reduce misalignment when forming the first trench 11 and the second trench 12. When the first trench 11 and the second trench 12 are separated by the n-type epitaxial layer 22, a p-type doped region 30 may be further formed in the n-type epitaxial layer 22 between the first trench 11 and the second trench 12, as shown in fig. 5, the p-type doped region 30 may be formed in the same step as the p-type body region 27, which may reduce a photolithography process and reduce the manufacturing cost of the semiconductor power device.
The semiconductor power device of the present invention may further include a p-type collector region 21, and the n-type epitaxial layer 22 is located above the p-type collector region 21, whereby the semiconductor power device of the present invention is an IGBT power device. When the semiconductor power device is an IGBT power device, an n-type charge storage layer 29 can be formed in the n-type epitaxial layer 22, the n-type charge storage layer 29 is located on one side, close to the p-type collector region 21, of the second groove 12, and the n-type charge storage layer 29 can improve carrier distribution of a drift region of the device, so that the device can obtain smaller turn-off time, and turn-off loss is reduced.
The n-type epitaxial layer 22 of the semiconductor power device of the present invention may also be formed on an n-type substrate, whereby the semiconductor power device of the present invention is a power MOSFET device of conventional structure, with the n-type emitter region serving as the power MOSFET device and the n-type substrate serving as the n-type drain region of the power MOSFET device.
The above embodiments and examples are specific supports for the technical ideas of the present invention, and the protection scope of the present invention should not be limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical solutions according to the technical ideas proposed by the present invention still belong to the protection scope of the technical solutions of the present invention.
Claims (8)
1. A semiconductor power device, comprising: a cell region and a gate bus region, the cell region including a plurality of periodically arranged cells, the cells including:
an n-type epitaxial layer;
two first trenches in the n-type epitaxial layer and two second trenches between the two first trenches, wherein the depth of the second trenches is smaller than that of the first trenches; the second groove extends into the grid bus area, and the width of the second groove in the grid bus area is larger than that of the second groove in the cell area;
the insulating layer and the conducting layer are positioned in the first groove;
the gate dielectric layer and the gate electrode are positioned in the second groove;
the p-type body region is positioned in the n-type epitaxial layer and is arranged between the two second grooves;
an n-type emitter region within the p-type body region.
2. The semiconductor power device of claim 1, wherein the first trench is adjacent to the second trench, the gate being insulated from the conductive layer.
3. The semiconductor power device of claim 1, further comprising a p-type collector region, the n-type epitaxial layer being located above the p-type collector region.
4. The semiconductor power device of claim 3, further comprising an n-type charge storage layer within the n-type epitaxial layer, the n-type charge storage layer being located on a side of the second trench proximate to the p-type collector region.
5. The semiconductor power device of claim 1, wherein the first trench is separated from the second trench by the n-type epitaxial layer.
6. The semiconductor power device of claim 5, further comprising a p-type doped region located within the n-type epitaxial layer between the first trench and the second trench.
7. The semiconductor power device of claim 1, wherein the two second trenches are connected within the gate bus region.
8. The semiconductor power device of claim 1, wherein the conductive layer is externally connected to a source voltage and the gate is externally connected to a gate voltage.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011069972.8A CN114335170A (en) | 2020-09-30 | 2020-09-30 | Semiconductor power device |
| PCT/CN2020/125751 WO2022067946A1 (en) | 2020-09-30 | 2020-11-02 | Semiconductor power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011069972.8A CN114335170A (en) | 2020-09-30 | 2020-09-30 | Semiconductor power device |
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| Publication Number | Publication Date |
|---|---|
| CN114335170A true CN114335170A (en) | 2022-04-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011069972.8A Pending CN114335170A (en) | 2020-09-30 | 2020-09-30 | Semiconductor power device |
Country Status (2)
| Country | Link |
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| CN (1) | CN114335170A (en) |
| WO (1) | WO2022067946A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117410346B (en) * | 2023-12-14 | 2024-03-26 | 深圳市森国科科技股份有限公司 | Trench gate silicon carbide MOSFET and manufacturing method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009071009A (en) * | 2007-09-13 | 2009-04-02 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| US20110121386A1 (en) * | 2009-11-20 | 2011-05-26 | Force Mos Technology Co., Ltd. | Trench MOSFET with trenched floating gates as termination |
| US20110254071A1 (en) * | 2009-11-20 | 2011-10-20 | Force Mos Technology Co. Ltd. | Shielded trench mosfet with multiple trenched floating gates as termination |
| CN109427869A (en) * | 2017-08-29 | 2019-03-05 | 昆仑芯电子科技(深圳)有限公司 | A kind of semiconductor devices |
| CN111211169A (en) * | 2020-02-26 | 2020-05-29 | 无锡新洁能股份有限公司 | Shielded IGBT structure and manufacturing method thereof |
| CN111316445A (en) * | 2018-02-09 | 2020-06-19 | 苏州东微半导体有限公司 | IGBT power device and manufacturing method thereof |
| CN111725306A (en) * | 2019-03-22 | 2020-09-29 | 中山汉臣电子科技有限公司 | Groove type power semiconductor device and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779847A (en) * | 2012-07-18 | 2012-11-14 | 电子科技大学 | Carrier stored groove bipolar transistor |
| CN103151310B (en) * | 2013-03-11 | 2015-05-13 | 中航（重庆）微电子有限公司 | Deeply-grooved power MOS (Metal Oxide Semiconductor) device and production method thereof |
| CN107527948B (en) * | 2017-07-28 | 2020-04-10 | 上海华虹宏力半导体制造有限公司 | Shielded gate trench MOSFET and method of making same |
| CN110867443B (en) * | 2018-08-27 | 2022-02-22 | 苏州东微半导体股份有限公司 | Semiconductor power device |
-
2020
- 2020-09-30 CN CN202011069972.8A patent/CN114335170A/en active Pending
- 2020-11-02 WO PCT/CN2020/125751 patent/WO2022067946A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009071009A (en) * | 2007-09-13 | 2009-04-02 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| US20110121386A1 (en) * | 2009-11-20 | 2011-05-26 | Force Mos Technology Co., Ltd. | Trench MOSFET with trenched floating gates as termination |
| US20110254071A1 (en) * | 2009-11-20 | 2011-10-20 | Force Mos Technology Co. Ltd. | Shielded trench mosfet with multiple trenched floating gates as termination |
| CN109427869A (en) * | 2017-08-29 | 2019-03-05 | 昆仑芯电子科技(深圳)有限公司 | A kind of semiconductor devices |
| CN111316445A (en) * | 2018-02-09 | 2020-06-19 | 苏州东微半导体有限公司 | IGBT power device and manufacturing method thereof |
| CN111725306A (en) * | 2019-03-22 | 2020-09-29 | 中山汉臣电子科技有限公司 | Groove type power semiconductor device and manufacturing method thereof |
| CN111211169A (en) * | 2020-02-26 | 2020-05-29 | 无锡新洁能股份有限公司 | Shielded IGBT structure and manufacturing method thereof |
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| Publication number | Publication date |
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| WO2022067946A1 (en) | 2022-04-07 |
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