CN103151310B - Deeply-grooved power MOS (Metal Oxide Semiconductor) device and production method thereof - Google Patents
Deeply-grooved power MOS (Metal Oxide Semiconductor) device and production method thereof Download PDFInfo
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Abstract
The invention provides a deeply-grooved power MOS (Metal Oxide Semiconductor) device and a production method thereof. The deeply-grooved power MOS device comprises a cell region, a grid electric contact region and a terminal protection region, wherein a source region and a body region are equipotential in the cell region by a body contact region which is prepared by inversion and is isomorphic to the body. According to the invention, a minimum distance between the cells is 0.76 microns, so that the device has high cell density; the invention adopts blank implantation (Blank Implantation), so that a process is simplified; when the minimum photoresist line width of 0.16 microns is ensured, the problem of glue pouring due to over-small photoresitt width in small line width photolithography technique is avoided; furthermore, the doping concentration of the body contact region is further increased, so that contact resistors between the body contact region and a source body contact metal layer, and between the body contact region and a body contact metal layer are reduced; a regular grid electric contact method is improved, and the technique difficulty is reduced.
Description
Technical Field
The invention belongs to the field of semiconductor devices and manufacturing thereof, relates to a deep trench power MOS device and a manufacturing method thereof, and particularly relates to a deep trench power MOS device with high cell density and a manufacturing method thereof.
Background
At present, in the conventional deep trench power MOS device process preparation, in order to make the source region 1 ″ and the body region 2 ″ have the same potential, the silicon layer needs to be etched to penetrate through the source region 1 ″ and reach the body region 2 ″ when the contact hole 3 ″ is prepared, as shown in fig. 1.
Under the condition of low application frequency, the power consumption is mainly determined by conduction loss, and the conduction loss is mainly influenced by the size of the characteristic conduction resistance, wherein the smaller the characteristic conduction resistance is, the smaller the conduction loss is. The main method for reducing the characteristic on-resistance is to increase the cell density, reduce the distance (pitch) between adjacent cells, and increase the total effective width of a unit area, thereby achieving the purpose of reducing the characteristic on-resistance. As shown in figure 1, in the current domestic power MOS mass production process, the minimum cell groove line width is about 0.25 μm, the groove line width d1 after the sacrificial oxide layer and the insulating gate oxide layer are finally etched and prepared is about 0.4 μm, the minimum cell contact hole line width d2 is about 0.25 μm, the alignment precision of a 248nm DUV photoetching machine is about 60nm, and in order to ensure an enough process window, the distance d3 from the cell contact hole to the final finished insulating gate oxide layer cell groove 4 '' is at least 0.09 μm. Thus, in the prior art, the minimum achievable cell pitch is about 0.83 μm, and the minimum cell pitch for mass production is generally set to about 1.0 μm in the domestic and foreign industries.
As shown in fig. 2, the ultra-high cell density deep trench power MOS device does not require a contact hole process in a cell region, but directly makes ohmic contact with a source region 7 ' and a P well layer (body region) 4 ' by depositing source metal 5 ', and the source metal 5 ' is insulated and isolated from conductive polysilicon 6 ' in a cell trench 11 ' by an insulating dielectric layer 9 '. The patent can improve the cell density and reduce the characteristic on-resistance.
However, the patent has the following disadvantages:
1. obviously, the cell density described in this patent is not "limited only by the minimum line width and spacing of the cell trenches 11', nor by the contact hole line width and hole-to-cell trench alignment accuracy" as it is described. In fact, the cell density of this patent is also limited by the spacing d4 between the source electrodes 7 ' (i.e., N + regions in fig. 2) of the adjacent cells, i.e., the width of the P-well layer (body region) 4 ' where it contacts the source metal 5 ' (which can be as small as 0.16 μm for a 248nm DUV lithography machine), and further, the cell density of this patent is also limited by the alignment accuracy of the source electrodes 7 ' to the cell trenches 11 '. Thus, the cell density of this patent cannot be "at least 2G/inch2, which is an improvement of about 220%" as described, but the minimum achievable cell pitch (pitch) in this patent is about 0.76 μm;
2. when the source 7 'of the unit cell is implanted, a photoresist barrier needs to be formed at the window of the body region 4', the photoresist width is small (generally, for a 248nm DUV photoetching machine, the photoresist width can be as small as 0.16 μm at the minimum), so that the photoresist (peeling) is easily caused, and the product yield is influenced;
3. no solution is given in the patent regarding the electrical contact of the gate in deep trench power MOS devices;
4. the patent makes use of the direct contact of the P-well layer (body region) 4 ' with the source metal 5 ' to make the body region and the source region equipotential, so the concentration of the contact region can only be kept consistent with that of the P-well layer (body region) 4 ', and the doping concentration of the contact region cannot be further adjusted independently to reduce the contact resistance without changing the body region concentration.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a deep trench power MOS device and a manufacturing method thereof, which are used to solve the problem of glue pouring caused by the limitations of the manufacturing process and method in the prior art, and simultaneously solve the problem that the doping concentration of the region where the body region is in contact with metal is not adjustable in the prior art, which is not beneficial to reducing the contact resistance, and further supplement the solution of the gate electrical contact of the device in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a deep trench power MOS device, the method at least comprising the following steps:
1) providing a substrate, wherein the substrate comprises a drain region of a first conductivity type and a first epitaxial layer of the first conductivity type formed on the drain region, and the first epitaxial layer is transversely divided into a cell region, a gate electrical contact region and a terminal protection region;
2) depositing a hard mask on the upper surface of the substrate, and photoetching and etching the hard mask until the upper surface of the substrate is exposed to form a hard mask window;
3) etching the substrate through the hard mask window to form a plurality of regularly arranged and mutually parallel deep grooves in a first epitaxial layer of the substrate, wherein the deep grooves comprise cell grooves, grooves of a grid electrical contact area and grooves of a terminal protection area;
4) forming a gate dielectric layer on the upper surface of the substrate and in the deep groove;
5) depositing a grid electrode material layer on the grid electrode dielectric layer, wherein the deep groove is filled with the grid electrode material layer and covers the upper surface of the grid electrode dielectric layer on the surface of the substrate;
6) etching the grid material layer to enable the cell groove, the grid electrical contact region groove and the terminal protection region groove to be partially filled with the grid material layer to form a grid;
7) forming a third epitaxial layer of the second conductivity type on top of the first epitaxial layer, forming a source region of the first conductivity type on top of the third epitaxial layer, forming body contact regions of the second conductivity type on top of the third epitaxial layer at the cell regions to space the source regions, forming a body contact region contacting with the trench of the termination protection region on top of the third epitaxial layer located in the termination protection region, forming a first insulating medium layer with the upper surface positioned on the same plane with the upper surface of the substrate on the grid of the cellular groove, wherein the third epitaxial layer under the source region or/and the body contact region is a body region, the first epitaxial layer under the third epitaxial layer is a drift region, meanwhile, the depth of the third epitaxial layer is smaller than that of the deep groove, so that the deep groove extends to the top of the drift region and contacts with the adjacent body region or/and source region;
8) depositing an insulating medium layer on the upper surface of the structure obtained after the step 7), and then etching the insulating medium layer by a dry method to form a second insulating medium layer positioned in the grid electrical contact area and a third insulating medium layer positioned in the terminal protection area, wherein a contact hole exposing the upper surface of the grid is formed in the second insulating medium layer, a contact hole exposing the upper surface of the body contact area is formed in the third insulating medium layer, and the insulating medium layer positioned in the cellular area is etched until the upper surface of the substrate is exposed, but the first insulating medium layer positioned in the cellular groove is reserved;
9) depositing metal on the surface of the structure obtained after the step 8), and then forming a source body contact metal layer positioned in the cell area, a grid contact metal layer positioned in the grid electrical contact area, and a body contact metal layer positioned in the terminal protection area by adopting photoetching and etching processes, wherein the source body contact metal layer is in ohmic contact with the source area and the body contact area directly, the source body contact metal layer is insulated and isolated from the grid of the cell groove through a first insulating medium layer, the grid contact metal layer is in ohmic contact with the corresponding grid through a contact hole positioned in the grid electrical contact area, and the body contact metal layer is in ohmic contact with the corresponding body contact area through a contact hole positioned in the terminal protection area.
Optionally, a second epitaxial layer of the first conductivity type is further disposed between the first epitaxial layer and the drain region to serve as a buffer region, that is, the second epitaxial layer is formed on the drain region, and the first epitaxial layer is formed on the second epitaxial layer.
Optionally, the doping concentrations of the drain region, the second epitaxial layer and the first epitaxial layer are sequentially reduced, wherein the drain region is of a heavily doped first conductivity type, and the first epitaxial layer is of a lightly doped first conductivity type.
Optionally, the step 4) further includes, before forming the gate dielectric layer, growing a sacrificial oxide layer on the upper surface of the substrate and in the deep trench and then removing the sacrificial oxide layer, so as to remove defects and impurities on the upper surface of the substrate, on sidewalls of the deep trench and at the bottom of the deep trench.
Optionally, the gate material layer in step 5) is a doped gate material layer, wherein the gate material layer is doped simultaneously during deposition, or the gate material layer is subjected to ion implantation and annealing process after deposition, so as to reduce the resistance of the gate material layer.
Optionally, the specific steps of forming the third epitaxial layer, the source region and the body contact region in step 7) are: forming a third epitaxial layer on the top of the first epitaxial layer by two times of maskless doping injection, and forming a source region on the top of the third epitaxial layer; and then, forming a concentration-adjustable body contact region in the source region of the cell region by adopting photoetching, ion implantation and annealing processes, and simultaneously converting a region of the first conductivity type above the body region in the terminal protection region into a second conductivity type to form the concentration-adjustable body contact region of the terminal protection region.
Optionally, the specific step of forming the first insulating dielectric layer in step 7) is: and depositing an insulating medium layer on the grid electrode and the grid medium layer, and etching the insulating medium layer to ensure that the insulating medium layer is reserved on the surface of the cellular groove to form the first insulating medium layer.
Optionally, in the step 7), forming the first insulating medium layer is performed before forming the third epitaxial layer, the source region and the body contact region.
Optionally, in the step 7), forming the first insulating medium layer is performed after forming the third epitaxial layer, the source region and the body contact region.
The invention also provides a deep trench power MOS device, at least comprising:
the cell area, the grid electrical contact area and the terminal protection area that are used for the grid electricity to connect of a plurality of regular arrangements and parallel arrangement cell each other, wherein, cell area, grid electrical contact area and terminal protection area all include:
a drain region of a heavily doped first conductivity type;
a drift region of a lightly doped first conductivity type formed on the drain region;
the third epitaxial layer is formed on the drift region and at least comprises a body region of the second conductivity type, wherein the body region is positioned at the bottom of the third epitaxial layer and is in contact with the drift region;
a plurality of deep trenches which are concavely arranged on the third epitaxial layer and comprise cell trenches, trenches of electrical contact regions of gates and trenches of terminal protection regions, the deep trenches penetrate through the body region and extend to the top of the drift region, gate dielectric layers are formed on the inner walls and the bottoms of the deep trenches, the deep trenches are also partially filled with the gates which are in contact with the gate dielectric layers, first insulating dielectric layers which are in contact with the gate dielectric layers are formed on the gates, and the upper surfaces of the first insulating dielectric layers, the openings of the deep trenches and the upper surface of the third epitaxial layer are all located in the same plane;
the cell area also comprises a source area, a body contact area and a source body contact metal layer, and each cell of the cell area comprises a cell groove; wherein,
the source region is of a heavily doped first conduction type, is formed at the top of the third epitaxial layer of the cellular region, is positioned above the body region and is contacted with the outer wall of each cellular groove, and a gap is formed between the source regions of the adjacent cells;
the body contact region is of a second conductivity type, is formed at the top of the third epitaxial layer of the cell region, is positioned above the body region, is positioned in the interval between the source regions of the adjacent cells and is in contact with the source regions;
the source body contact metal layer is positioned on the third epitaxial layer of the cellular region and is in ohmic contact with the source region and the body contact region, and meanwhile, the source body contact metal layer is insulated and isolated from the grid electrode of the cellular groove through a first insulating medium layer;
the grid electrode electric contact area also comprises a second insulating medium layer and a grid electrode contact metal layer; wherein,
the second insulating medium layer is formed on the first insulating medium layer, and a contact hole for exposing the upper surface of the grid electrode is formed in the second insulating medium layer;
the grid electrode contact metal layer is formed on the second insulating medium layer and is in contact with the grid electrode through the contact hole of the first insulating medium layer and the contact hole of the second insulating medium layer.
Optionally, a second epitaxial layer of the first conductivity type is further disposed between the drift region and the drain region as a buffer region, that is, the second epitaxial layer is formed on the drain region, and the drift region is formed on the second epitaxial layer.
Optionally, the doping concentrations of the drain region, the second epitaxial layer and the drift region are sequentially reduced, wherein the drain region is of a heavily doped first conductivity type, and the drift region is of a lightly doped first conductivity type.
Optionally, the thickness of the first insulating medium layer is 10-500 angstroms.
As described above, the deep trench power MOS device and the manufacturing method thereof of the present invention have the following beneficial effects: in the cellular region, a body contact region which is prepared in an inversion mode and has the same shape as a body region is utilized to enable a source region and the body region to realize equipotential; when the minimum cell spacing can reach 0.76 mu m and the device is high in cell density, the part of the injection process adopts maskless Implantation (Blank Implantation), the process is simplified, and the process difficulty is reduced, and when the body contact region is injected, the minimum photoresist line width of 0.16 mu m is ensured, and the problem of reverse photoresist caused by the over-small photoresist width in the small line width photoetching process is avoided; in addition, the concentration of the body contact region and the concentration of the body region can be inconsistent, so that the concentration of the body contact region can be adjusted as required, and the doping concentration of the body contact region is further increased while the concentration of the body region is not changed, so that the contact resistance between the body contact region and the source body contact metal layer and between the body contact region and the body contact metal layer is reduced; in addition, the invention makes clear that the grid electrical contact method is a big trench with contact pick-up method, skillfully utilizes the characteristic that the pattern dense area has stronger ion bombardment (ion bombedment) capability than the open area in the dry etching process, and ensures that the source contact metal layer and the grid in the cellular area can still keep insulation while the grid electrical contact area realizes the electrical contact of the metal layer; furthermore, in the grid electrical contact method, only the insulating medium layer is windowed to the upper surface of the grid positioned below the insulating medium layer, so that the process for preparing the contact hole in the conventional grid electrical contact method is improved, the situation that the insulating medium layer is etched and the grid positioned below the insulating medium layer is deeply etched during electrical contact in the conventional process is avoided, and the process difficulty is further reduced.
Drawings
Fig. 1 is a schematic structural diagram of a deep trench power MOS device in the prior art, wherein the device is manufactured by a conventional process, that is, a contact hole extending deep into a body region needs to be etched to make the source region and the body region have the same potential.
Fig. 2 is a schematic diagram of a deep trench power MOS device without a contact hole process in the prior art.
Fig. 3 to 18 are schematic structural diagrams illustrating steps of a manufacturing method of a deep trench power MOS device according to the first embodiment of the present invention, wherein fig. 18 is a schematic structural diagram illustrating the deep trench power MOS device according to the second embodiment of the present invention.
Description of the element reference numerals
I cell region
II grid electric contact area
III terminal protection zone
1 drain region
2 first epitaxial layer
21 third epitaxial layer
211. 7 ', 1 ' ' source region
212 body contact region
213. 2' body region
22 drift region
3 second epitaxial layer
4 hard mask
5 deep trench
51. 11 ', 4 ' ' cell trenches
52 gate electrical contact region trench
53 terminal guard area trench
6 sacrificial oxide layer
7 gate dielectric layer
8 gate material layer
81. Grid electrode
9. 9' insulating dielectric layer
91 first insulating dielectric layer
92 second insulating dielectric layer
93 third insulating dielectric layer
100 photo resist
121 source contact metal layer
122 gate contact metal layer
123 body contact metal layer
4' P well layer (body region)
5' source metal
6' conductive polysilicon
3' contact hole
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 18. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 3 to 18, the present invention provides a method for manufacturing a deep trench power MOS device, the method at least includes the following steps:
firstly, step 1) is executed, as shown in fig. 3, a substrate is provided, the substrate includes a drain region 1 of a first conductivity type and a first epitaxial layer 2 of the first conductivity type formed thereon, wherein the first epitaxial layer 2 is laterally divided into a cell region I, a gate electrical contact region II and a terminal protection region III, and the terminal protection region III surrounds the cell region I and the gate electrical contact region II; a second epitaxial layer 3 of the first conductivity type is further arranged between the first epitaxial layer 2 and the drain region 1 to serve as a buffer region, namely the second epitaxial layer 3 is formed on the drain region 1, the first epitaxial layer 2 is formed on the second epitaxial layer 3, and the upper surface of the substrate is the upper surface of the first epitaxial layer; the doping concentrations of the drain region 1, the second epitaxial layer 3 and the first epitaxial layer 2 are sequentially reduced, wherein the drain region 1 is of a heavily doped first conductivity type, and the first epitaxial layer 2 is of a lightly doped first conductivity type; the first conduction type and the second conduction type are of opposite conduction types. The substrate is a group iv semiconductor material or a group III-V semiconductor material, and at least includes silicon, silicon germanium, gallium nitride, gallium arsenide, or the like, and in the first embodiment, the substrate is preferably silicon.
In the first embodiment, the first conductive type is an N-type conductive type, and the second conductive type is a P-type conductive type, but not limited thereto.
In the first embodiment, the substrate includes a drain region 1 of an N + + type (heavily doped first conductivity type), a second epitaxial layer 3 of an N + type formed thereon, and a first epitaxial layer 2 of an N-type (lightly doped first conductivity type) formed on the second epitaxial layer 3, and the upper surface of the substrate is the upper surface of the first epitaxial layer 2; the N-type doped ions are any one or a combination of P and As, and in the first embodiment, the N-type doped ions are P.
It should be noted that the first epitaxial layer 2 of N-type is present to increase the breakdown voltage of the prefabricated device; further, the N + type second epitaxial layer 3 is also present in this embodiment as a buffer region, so as to avoid the reduction of the breakdown voltage of the prefabricated device caused by the direct transition of the N + + type drain region 1 to the N-type first epitaxial layer 2. Step 2) is then performed.
In step 2), as shown in fig. 4, depositing a hard mask 4 on the upper surface of the substrate (i.e. the upper surface of the first epitaxial layer 2), and performing photolithography and etching on the hard mask 4 until the upper surface of the substrate is exposed to form a hard mask window; the method for depositing the hard mask 4 includes chemical vapor deposition or physical vapor deposition, in the first embodiment, chemical vapor deposition is adopted; performing photolithography and etching on the hard mask 4 means coating a photoresist (not shown) on the hard mask 4, exposing and developing the photoresist, then etching the part of the hard mask 4 not covered by the photoresist to form a hard mask window, and finally removing the photoresist, wherein the photolithography and etching processes are well known by those skilled in the art and are not described herein again; the hard mask 4 is silicon nitride or silicon oxide, and in the first embodiment, the hard mask 4 is silicon nitride. Step 3) is then performed.
In step 3), as shown in fig. 5, the substrate is etched through the hard mask window to form a plurality of regularly arranged and parallel deep trenches 5 in the first epitaxial layer 2 of the substrate, wherein the deep trenches 5 include a cell trench 51 located in the cell region I, a gate electrical contact region trench 52 located in the gate electrical contact region II, and a terminal protection region trench 53 located in the terminal protection region III, and the width of the gate electrical contact region trench 52 is 0.1-100 μm, and in the first embodiment, is preferably 1-20 μm; the etching process is dry etching, wherein the dry etching at least comprises plasma etching or reactive ion etching, and in the first embodiment, the substrate is etched by using the reactive ion etching; the depth range of the deep trench is 1-8.5 μm, and in the first embodiment, 1.3-2 μm is preferred. Step 4) is then performed.
In the step 4), forming a gate dielectric layer 7 on the upper surface of the substrate and in the deep trench 5, wherein the forming of the gate dielectric layer 7 adopts an oxidation growth or deposition method; in addition, before the gate dielectric layer 7 is formed, a step of growing a sacrificial oxide layer 6 on the upper surface of the substrate and in the deep trench 5 and then removing the sacrificial oxide layer 6 is further included to remove defects and impurities on the upper surface of the substrate, the side wall of the deep trench and the bottom of the deep trench.
As shown in fig. 6 and 7, in the first embodiment, the step 4) is: firstly growing a sacrificial oxide layer 6 on the upper surface of the substrate and in the deep groove 5, then removing the sacrificial oxide layer 6, and then carrying out oxidation growth on the upper surface of the substrate with the defects and impurities removed and in the deep groove 5 to form a gate dielectric layer 7. In the first embodiment, the sacrificial oxide layer 6 is silicon oxide, the gate dielectric layer 7 is silicon oxide or silicon oxynitride, the sacrificial oxide layer 6 is silicon oxide, the gate dielectric layer 7 is silicon oxide, and the line width of the deep trench 5 after the sacrificial oxide layer 6 and the gate dielectric layer 7 are prepared is about 0.4 μm. Step 5) is then performed.
In step 5), as shown in fig. 8, depositing a gate material layer 8 on the gate dielectric layer 7, wherein the deep trench is filled with the gate material layer 8 and covers the upper surface of the gate dielectric layer 7 on the surface of the substrate; the grid material layer 8 is polysilicon, titanium, aluminum copper, aluminum silicon copper or copper; further, the gate material layer 8 is a doped gate material layer to reduce the resistance of the gate material layer 8, wherein one doping method is to dope while depositing the gate material layer 8, and the other doping method is to perform an ion implantation and annealing process on the gate material layer 8 after depositing the gate material layer.
In the first embodiment, the gate material layer 8 in the step 5) is doped polysilicon, and preferably, the polysilicon gate material layer 8 is doped while being deposited; the specific doping of the gate material layer 8 depends on the different requirements of the specific pre-fabricated device, and the main purpose of doping is to reduce the resistance of the gate material layer 8. Step 6) is then performed.
In step 6), as shown in fig. 9, the gate material layer 8 is etched to partially fill the gate material layer 8 in the cell trench 51, the gate electrical contact region trench 52 and the terminal protection region trench 53 (i.e., in the deep trench 5) to form a gate 81, wherein the upper surface of the gate 81 in the cell trench 51, the gate electrical contact region trench 52 and the terminal protection region trench 53 is 200 to 2000 angstroms, preferably 500 to 1200 angstroms, lower than the upper surface of the substrate on which the gate dielectric layer 7 is formed; the etching process is dry etching or wet etching, wherein the dry etching at least comprises plasma etching or reactive ion etching, nitric acid or a mixed solution of nitric acid and hydrofluoric acid is adopted during the wet etching, and water or acetic acid can be used for diluting so as to reduce the etching rate during the wet etching, so that the etching thickness can be controlled, and in the first embodiment, the reactive ion etching is adopted for etching the substrate.
It should be noted that how to communicate the cell region I, the gate electrical contact region II, and the terminal protection region III, and how to interconnect the gates 81 located between the deep trenches 5 of the cell region I, the gate electrical contact region II, and the terminal protection region III are well known to those skilled in the art, and are not described herein again. Step 7) is then performed.
In step 7), forming a third epitaxial layer 21 of the second conductivity type on top of the first epitaxial layer 2, forming a source region 211 of the first conductivity type on top of the third epitaxial layer 21, forming a body contact region 212 of the second conductivity type on top of the third epitaxial layer located in the cell region I to separate the source region 211 into two parts, forming a body contact region 212 on top of the third epitaxial layer 21 located in the terminal protection region III to contact with the terminal protection region trench 53, forming a first insulating medium layer 91 on the gate 81 of the cell trench 51, wherein the third epitaxial layer 21 located below the source region 211 or/and the body contact region 212 is a body region 213, the first epitaxial layer 2 located below the third epitaxial layer 21 is a drift region 22, and the depth of the third epitaxial layer 21 is smaller than the depth of the deep trench 5, so that the deep trench 5 extends into the top of the drift region 22, and the deep trenches 5 are all in contact with the body regions 213 or/and the source regions 211 adjacent to the deep trenches, the first epitaxial layer 31 comprises a third epitaxial layer 21 and a drift region 22, in the cell region I, the third epitaxial layer 21 comprises a body region 213, a source region 211 and a body contact region 212, and in the terminal protection region III, the third epitaxial layer 21 comprises a body region 213 and a body contact region 212.
It should be noted that the specific steps of forming the third epitaxial layer 21, the source region 211 and the body contact region 212 in step 7) are as follows: forming a third epitaxial layer 21 on the top of the first epitaxial layer 2 and then forming a source region 212 on the top of the third epitaxial layer 21 by two times of mask-less (blanket Implantation) doping Implantation; then, a photolithography, ion implantation and annealing process is used to form a concentration-adjustable body contact region 212 in the source region 211 of the cell region I, and at the same time, a region of the first conductivity type in the termination protection region III above the body region 213 is transformed into a second conductivity type, so as to form the concentration-adjustable body contact region 212 of the termination protection region III.
It is noted that, when the region of the first conductivity type in the termination protection region III above the body region 213 is converted to the second conductivity type in step 7), the region of the first conductivity type above the body region 213 is also simultaneously converted to the second conductivity type in the gate electrical contact region II.
It should be further noted that, the specific steps of forming the first insulating dielectric layer 91 in the step 7) are as follows: depositing an insulating medium layer 9 on the gate 81 and the gate medium layer 7, and etching the insulating medium layer 9 to leave the insulating medium layer 9 on the surface of the cell trench 51 to form the first insulating medium layer 91, wherein the first insulating medium layer 91 may also be formed on the surfaces of the gate electrical contact region trench 52 and the terminal protection region trench 53; the thickness of the first insulating dielectric layer 91 is 10 to 500 angstroms, preferably 10 to 200 angstroms.
It should be noted that, in the step 7), the first insulating medium layer 91 is formed before the third epitaxial layer 21, the source region 211 and the body contact region 212 are formed, or the first insulating medium layer 91 is formed after the third epitaxial layer 21, the source region 211 and the body contact region 212 are formed.
In the step 7) of the first embodiment, the first insulating medium layer 91 is formed before the third epitaxial layer 21, the source region 211 and the body contact region 212 are formed, the thickness of the first insulating medium layer 91 is preferably 10 to 200 angstroms, the first conductivity type is N-type, the second conductivity type is P-type, the body region 213 is P-type, the source region 211 is N + type, the body contact region 212 is P-type, and the drift region 22 is N-type.
Step 7) in this embodiment one, the specific steps of forming the third epitaxial layer 21, the source region 211 and the body contact region 212 are as follows:
as shown in fig. 10, a P-type third epitaxial layer 21 is formed on top of the N-type first epitaxial layer 2 by a maskless Implantation (Blank Implantation), the N-type first epitaxial layer 2 under the P-type third epitaxial layer 21 is an N-type drift region 22, wherein the depth of the third epitaxial layer 21 is less than the depth of the deep trench 5, so that the deep trench 5 extends into the top of the drift region 22; the doping ions are B, BF when forming the P-type third epitaxial layer 212Or In, In the first embodiment, the doping ion is preferably B when forming the P-type third epitaxial layer 21;
then, As shown in fig. 11, continuing to perform a maskless Implantation (Blank Implantation) doping Implantation, forming an N + -type source region 211 at the top of the P-type third epitaxial layer 21, where the third epitaxial layer 21 located below the source region 211 is a body region 213, where the doping ions are either P or As or a combination thereof when forming the N + -type source region 211, and in the first embodiment, the doping ions are preferably P when forming the N + -type source region 211;
then, as shown in fig. 12 and 13, spin-coating a photoresist 100 on the substrate surface where the gate dielectric layer 7 is formed in the cell region I, exposing and developing the photoresist 100 to form a photoresist window of a pre-implanted body contact region 212, then performing P + + type ion implantation, removing the photoresist 100, and performing high temperature annealing on a region not covered with the photoresist 100, so that a P-type body contact region 212 is formed at the top of the third epitaxial layer 21 corresponding to the photoresist window in the cell region I, and the P-type body contact region 212 separates the source region 211 into two parts, where the concentration of the body contact region 212 can be adjusted by the P + + type ion implantation; meanwhile, the top regions of the third epitaxial layer 21 not covered by the photoresist 100 in the gate electrical contact region II and the terminal protection region III are transformed from N + type to P type, and the regions transformed from P type in the gate electrical contact region II and the terminal protection region III are both located above the body region 213, and a P-type body contact region 212 contacting with the terminal protection region trench 53 is formed on the top of the third epitaxial layer 21 in the terminal protection region III, and the concentration of the body contact region 212 can be adjusted by P + + type ion implantation, wherein the ions implanted in the P + + type are B, BF2Or In, In the first embodiment, the implanted ion is preferably B.
Thus, in the cell region I, the third epitaxial layer 21 located below the source region 211 and the body contact region 212 is the body region 213, and the cell trench 51 is in contact with the adjacent body region 213 and the source region 211; in the termination protection region III, the third epitaxial layer 21 located below the body contact region 212 is a body region 213, and the deep termination protection region trench 53 is in contact with the adjacent body region 213 and the P-type body contact region 212.
It should be noted that, generally, for a 248nm DUV lithography machine, the minimum width of the photoresist window can reach 0.16 μm, and in fig. 12 of this embodiment one, the photoresist window with the width of 0.16 μm is a hollowed-out photoresist window instead of the photoresist itself, so that the invention avoids the problem of photoresist falling caused by the too small photoresist width in the small-line-width lithography process in the prior art while ensuring the minimum photoresist line width of 0.16 μm.
It should be further noted that in the prior art patent (application No. 201110405658.7) that does not require a contact hole process, the body region itself is directly used to make the source region and the body region equipotential, while the present invention uses the body contact region 212 that is formed in an inversion manner and has the same type as the body region 213 to make the source region 211 and the body region 213 equipotential, the concentration of the body contact region 212 and the concentration of the body region 213 may not be the same, so that the concentration of the body contact region 212 may be adjusted as needed without changing the concentration of the body region 213.
In this embodiment, the specific steps of forming the first insulating dielectric layer 91 in the step 7) include: as shown in fig. 14 and 15, depositing an insulating medium layer 9 on the gate 81 and the gate medium layer 7, and etching the insulating medium layer 9, so that the insulating medium layer 9 remains on the surfaces of the cell trench 51, the gate electrical contact region trench 52, and the terminal protection region trench 53 to form the first insulating medium layer 91, and the upper surface of the first insulating medium layer 91 and the upper surface of the substrate are located on the same plane, so as to ensure that the first insulating medium layer 91 realizes the insulating isolation between the gate 81 and the metal when the subsequent metal is electrically connected, wherein the thickness of the first insulating medium layer 91 is preferably 10 to 200 angstroms; at this time, the gate dielectric layer 7 on the upper surface of the substrate is also etched away, so that the source region 211, the body contact region 212, and the first insulating dielectric layer 91 in the cell region I are exposed on the upper surface of the substrate, the body contact region 212 and the first insulating dielectric layer 91 in the terminal protection region III are exposed on the upper surface of the substrate, and the first insulating dielectric layer 91 and the P-type region in the gate electrical contact region II are exposed on the upper surface of the substrate, wherein the insulating dielectric layer 9 (the first insulating dielectric layer 91) is made of silicon oxide, silicon oxynitride, or silicon nitride, and in this embodiment, the insulating dielectric layer 9 is made of silicon oxide. Step 8) is then performed.
In step 8), as shown in fig. 16 and 17, depositing an insulating dielectric layer 9 on the upper surface of the structure obtained after the step 7), and then performing photolithography and dry etching on the insulating dielectric layer 9 to form a second insulating dielectric layer 92 located in the gate electrical contact region II and a third insulating dielectric layer 93 located in the terminal protection region III, wherein a contact hole exposing the upper surface of the gate 81 is formed in the second insulating dielectric layer 92, and a contact hole exposing the upper surface of the body contact region 212 is formed in the third insulating dielectric layer 93, wherein the insulating dielectric layer 9 located in the cell region I is etched until the upper surface of the substrate is exposed but the first insulating dielectric layer 91 located in the cell trench 51 is remained, and at this time, the source region 211, the body contact region 212, and the first insulating dielectric layer 91 in the cell region I are exposed on the upper surface of the substrate; the dry etching at least includes plasma etching or reactive ion etching, and in the first embodiment, the insulating dielectric layer 9 is etched by using plasma etching.
It should be noted that, when the insulating dielectric layer 9 in the step 8) is etched, in the gate electrical contact area II, the first insulating dielectric layer 91 on the gate 81 is also etched and a contact hole is formed, where the contact hole formed in the first insulating dielectric layer 91 corresponds to the contact hole formed in the second insulating dielectric layer 92, and at this time, the gate 81 in the gate electrical contact area II is exposed through the contact holes of the first insulating dielectric layer 91 and the second insulating dielectric layer 92.
It should be further noted that, since the insulating dielectric layer 9 on the surface of the cell region I in step 8) is etched, the cell region I is in full contact during the subsequent metal electrical connection, and is not in electrical contact through the contact hole, so that the cell region I has no contact hole and is a contact hole empty area, and the gate electrical contact region II has a contact hole to achieve the subsequent metal electrical connection, so that the gate electrical contact region II is a contact hole dense area (i.e. a pattern dense area) relative to the cell region I In the meantime, the first insulating medium layer 91 on the gate electrode in the empty area (cell area) of the contact hole is reserved, so that the source contact metal layer and the gate electrode in the cell area can be still kept insulated while the metal layer is electrically contacted in the gate electrode electrical contact area. Step 9) is then performed.
In step 9), as shown in fig. 18, depositing metal on the surface of the structure obtained after step 8), and then performing photolithography and etching processes to form a source contact metal layer 121 located in the cell region I, a gate contact metal layer 122 located in the gate electrical contact region II, and a body contact metal layer 123 located in the terminal protection region III, where the source contact metal layer 121 is in ohmic contact with the source region 211 and the body contact region 212 directly, the source contact metal layer 121 is insulated and isolated from the gate 81 of the cell trench 51 by a first insulating dielectric layer 91, the gate contact metal layer 122 is in ohmic contact with the corresponding gate 81 by a contact hole located in the gate electrical contact region II, and the body contact metal layer 123 is in ohmic contact with the corresponding body contact region 212 by a contact hole located in the terminal protection region III. The material of the source contact metal layer 121, the gate contact metal layer 122 and the body contact metal layer 123 is titanium, aluminum copper, aluminum silicon copper or copper, and in the first embodiment, aluminum copper is preferred.
It should be noted that, in the prior art patent (application No. 201110405658.7) that does not require a contact hole process, the body region itself is directly utilized to make the source region and the body region equipotential, while the body contact region 212 that is prepared in an inversion manner and has the same type as the body region 213 is utilized to make the source region 211 and the body region 213 equipotential, so the concentration of the body contact region 212 of the present invention may not be consistent with the concentration of the body region 213 located thereunder, and the concentration of the body contact region 212 may be adjusted as needed, thereby further increasing the doping concentration of the body contact region 212 without changing the concentration of the body region 213, and further reducing the contact resistance between the body contact region 212 and the source body contact metal layer 122, and between the body contact region 212 and the body contact metal layer 123.
It should be noted that, in the conventional process, the source metal contact is realized by a contact hole process, and a metal connection process on contact hole metal filling and an interlayer dielectric is required, but in the manufacturing method of the source contact metal layer 121 in the cell region I, a process without a contact hole is adopted, and a substrate does not need to be deeply etched to penetrate a source region and reach a body region, so that metal is directly deposited after the insulating medium layer 9 in the cell region I is removed by etching, and a whole piece of source contact metal layer 121 is formed, so that the source contact metal layer 121 is in direct contact with the source region 211 and the body contact region 212 when ohmic contact is carried out, the process steps are greatly simplified, the manufacturing process and the device structure of the invention are simpler, and the process difficulty is reduced.
It should be further noted that, in the manufacturing method of the cell region I, a process without a contact hole is adopted, and a substrate is not required to be deeply etched to penetrate through the source region and reach the body region, so that when the insulating dielectric layer 9 is etched in the step 8), the insulating dielectric layer 9 located in the cell region I is completely etched, and only the upper surface of the substrate is exposed, but the first insulating dielectric layer 91 located in the cell trench 51 is remained, therefore, for the etching of the contact hole (window) located in the gate electrical contact region II of the contact hole, only the insulating dielectric layer 9 and the first insulating dielectric layer 91 located thereunder form a contact hole (window) to the upper surface of the gate 81 located under the first insulating dielectric layer 91, that is, both the second insulating dielectric layer 92 and the first insulating dielectric layer 91 of the gate electrical contact region II are formed with a contact hole exposing the upper surface of the gate 81, therefore, the invention not only defines that the grid electrical contact method is a big trench with contact pick-up (big trench with contact pick-up) method, but also improves the process for preparing the contact hole in the conventional grid electrical contact method, and avoids the situation that the insulating medium layer is etched and the grid below the insulating medium layer is deeply etched during electrical contact in the conventional process, thereby further reducing the process difficulty.
It should be further noted that, in the first embodiment, the line width of the deep trench formed with the gate dielectric layer 7 and the gate 81 is about 0.4 μm; for a 248nm DUV lithography machine, the minimum width of the photoresist window during the body contact region 212 implant can be as small as 0.16 μm, so the minimum line width of the body contact region is 0.16 μm; due to the limitation of the alignment accuracy of the contact hole and the deep trench, the width of the source region 211 contacting the cell trench 51 is at least 0.09 μm, so that the minimum achievable cell pitch (pitch) is about 0.76 μm in the first embodiment.
In the cellular region, a body contact region which is prepared in an inversion mode and has the same shape as a body region is utilized to enable a source region and the body region to realize equipotential; when the minimum cell spacing can reach 0.76 mu m and the device is high in cell density, the part of the injection process adopts maskless Implantation (Blank Implantation), the process is simplified, and the process difficulty is reduced, and when the body contact region is injected, the minimum photoresist line width of 0.16 mu m is ensured, and the problem of reverse photoresist caused by the over-small photoresist width in the small line width photoetching process is avoided; in addition, the concentration of the body contact region and the concentration of the body region can be inconsistent, so that the concentration of the body contact region can be adjusted as required, and the doping concentration of the body contact region is further increased while the concentration of the body region is not changed, so that the contact resistance between the body contact region and the source body contact metal layer and between the body contact region and the body contact metal layer is reduced; in addition, the invention makes clear that the grid electrical contact method is a big trench with contact pick-up method, skillfully utilizes the characteristic that the pattern dense area has stronger ion bombardment (ion bombedment) capability than the open area in the dry etching process, and ensures that the source contact metal layer and the grid in the cellular area can still keep insulation while the grid electrical contact area realizes the electrical contact of the metal layer; furthermore, in the grid electrical contact method, only the insulating medium layer is windowed to the upper surface of the grid positioned below the insulating medium layer, so that the process for preparing the contact hole in the conventional grid electrical contact method is improved, the situation that the insulating medium layer is etched and the grid positioned below the insulating medium layer is deeply etched during electrical contact in the conventional process is avoided, and the process difficulty is further reduced.
Example two
As shown in fig. 18, the present invention further provides a deep trench power MOS device, which at least includes: the cell area I, the grid electrical contact area II and the terminal protection area III are arranged in parallel and are regularly arranged, the grid electrical contact area II is used for electrically connecting the grid, the terminal protection area III surrounds and surrounds the cell area I and the grid electrical contact area II, and the cell area I and the grid electrical contact area II comprise the terminal protection area III: the structure comprises a drain region 1, a drift region 22, a third epitaxial layer, a plurality of deep trenches which are concavely arranged on the third epitaxial layer, gate dielectric layers 7 which are formed on the inner walls and the bottoms of the deep trenches, a gate 81 which is formed in the deep trenches and a first insulating dielectric layer 91, wherein the deep trenches comprise a cell trench 51, a gate electrical contact region trench 52 and a terminal protection region trench 53; the cell region I further includes a source region 211, a body contact region 212, and a source body contact metal layer 121, and each cell of the cell region I includes a cell trench 51; the gate electrical contact region II further includes a gate dielectric layer 7, a gate wiring layer 82, a second insulating dielectric layer 92 and a gate contact metal layer 122.
It should be noted that, in the cell region I, the third epitaxial layer includes a body region 213, a source region 211, and a body contact region 212, and in the termination protection region III, the third epitaxial layer includes a body region 213 and a body contact region 212.
It should be noted that the termination protection region III further includes a body contact region 212, a third insulating dielectric layer 93 and a body contact metal layer 123, and the first insulating dielectric layer 91 in the termination protection region trench 53 is located on the gate 81 and is in contact with the gate dielectric layer 7 and the third insulating dielectric layer 93.
It should be further noted that the materials of the drain region 1, the drift region 22 and the third epitaxial layer are group iv semiconductor materials or group III-v semiconductor materials, and at least include silicon, silicon germanium, gallium nitride or gallium arsenide, and silicon is preferred in the second embodiment.
In the second embodiment, the first conductive type is an N-type conductive type, and the second conductive type is a P-type conductive type, but not limited thereto.
As shown in fig. 18, the cell region I and the terminal protection region III of the gate electrical contact region II each include a drain region 1, a drift region 22, a third epitaxial layer, and a plurality of deep trenches recessed from the third epitaxial layer, and the specific structures of the deep trenches are as follows:
the drain region 1 is of a heavily doped first conductivity type; the drift region 22 is lightly doped with the first conductivity type and is formed on the drain region 1.
It should be noted that a second epitaxial layer 3 of the first conductivity type is further disposed between the drift region 22 and the drain region 1 as a buffer region, that is, the second epitaxial layer 3 is formed on the drain region 1, and the drift region 22 is formed on the second epitaxial layer 3; further, the doping concentrations of the drain region 1, the second epitaxial layer 3 and the drift region 22 are sequentially reduced, wherein the drain region is of a heavily doped first conductivity type, and the drift region is of a lightly doped first conductivity type.
In the second embodiment, the N + -type second epitaxial layer 3 is formed on the N + + (heavily doped first conductivity type) drain region 1, and the N + -type (lightly doped first conductivity type) drift region 22 is formed on the N + -type second epitaxial layer 3; the N-type dopant ions are either P or As or a combination of both, and in the second embodiment, the N-type dopant ions are preferably P.
It is to be noted that the presence of said first epitaxial layer 2 of N-type is intended to increase the breakdown voltage of the prefabricated device; further, the second N + epitaxial layer 3 is also present in the second embodiment as a buffer region, so as to avoid the reduction of the breakdown voltage of the prefabricated device caused by the direct transition of the N + + type drain region 1 to the N + type first epitaxial layer 2.
The third epitaxial layer is formed on the drift region 22 and at least includes a body region 213 of the second conductivity type, wherein the body region 213 is located at the bottom of the third epitaxial layer and contacts the drift region 22. In the second embodiment, in the cell region I, the third epitaxial layer includes a P-type (second conductivity type) body region 213, an N + -type (heavily doped first conductivity type) source region 211, and a P-type (second conductivity type) contact region 212, and in the terminal protection region III, the third epitaxial layer includes a P-type (second conductivity type) body region 213 and a P-type (second conductivity type) body contact region 212; p type doping is B, BF2Or In, In the second embodiment, preferably, the P-type doping is B.
The deep trenches concavely arranged on the third epitaxial layer comprise a cell trench 51, a gate electrical contact region trench 52 and a terminal protection region trench 53, each of the deep trenches penetrates through the body region 213 and extends to the top of the drift region 22, gate dielectric layers 7 are formed on the inner walls and the bottoms of the deep trenches, a gate 81 in contact with the gate dielectric layer 7 is further partially filled in the deep trenches, and a first insulating dielectric layer 91 in contact with the gate dielectric layer 7 is formed on the gate 81, wherein the upper surface of the first insulating dielectric layer 91, the deep trench opening and the upper surface of the third epitaxial layer are all located in the same plane, so that the source contact metal layer 121 in the cell region I is insulated and isolated from the gate 81 of the cell trench 51 through the first insulating dielectric layer 91; furthermore, a contact hole exposing the upper surface of the gate 81 is formed in the first insulating medium layer 91 of the gate electrical contact region II; further, the distance between the upper surface of the gate 81 in the cell trench 51 and the terminal protection region trench 53 and the upper surface of the third epitaxial layer is the thickness of the first insulating medium layer 91, and the thickness of the first insulating medium layer 91 is 10 to 500 angstroms, preferably 10 to 200 angstroms in the second embodiment.
The depth range of the deep trench is 1-8.5 μm, and in the second embodiment, 1.3-2 μm is preferred; the width of the trench 52 of the gate electrical contact region is 0.1 to 100 μm, preferably 1 to 20 μm in the second embodiment.
It should be further noted that the gate dielectric layer 7 is silicon oxide or silicon oxynitride, in the second embodiment, the gate dielectric layer 7 is silicon oxide; the gate 81 is polysilicon, titanium, aluminum copper, aluminum silicon copper or copper, further, the gate 81 is a doped gate, in the second embodiment, the gate 81 is doped polysilicon; the first insulating dielectric layer 91 is made of silicon oxide, silicon oxynitride or silicon nitride, and in the second embodiment, the first insulating dielectric layer 91 is made of silicon oxide.
It is noted that the specific doping impurities of the gate 81 are determined according to different requirements of a specific pre-fabricated device, and the main purpose of doping is to reduce the resistance of the gate 81.
It should be further noted that how to communicate the cell region I, the gate electrical contact region II and the terminal protection region III and how to interconnect the gates in the deep trenches 5 are well known to those skilled in the art, and therefore, the details thereof are not repeated herein.
As shown in fig. 18, the cell region I further includes a source region 211, a body contact region 212, and a source body contact metal layer 121, and each of the cells of the cell region I includes a cell trench 51, wherein each of the structures further included in the cell region I specifically includes the following structures:
the source regions 211 are of a heavily doped first conductivity type, are formed on top of the third epitaxial layer of the cell region I, are located above the body regions 213, and are in contact with the outer walls of the cell trenches 51, and a space is formed between the source regions 211 of the adjacent cells. In the second embodiment, the source region 211 is an N + type, and preferably, the N-type dopant ions are P.
The body contact region 212 is of the second conductivity type, and is formed on top of the third epitaxial layer of the cell region I and located above the body region 213, and at the same time, the body contact region 212 is located in the space between the source regions 211 of adjacent cells and is in contact with the source regions 211. In the second embodiment, the body contact region 212 is P-type, and preferably, the P-type dopant ion is B.
The source contact metal layer 121 is located on the third epitaxial layer of the cell region and in ohmic contact with the source region 211 and the body contact region 212, and meanwhile, the source contact metal layer 121 is insulated and isolated from the gate 81 of the cell trench 51 by the first insulating medium layer 91. The material of the source contact metal layer 121 is aluminum, aluminum copper, aluminum silicon copper or copper, and aluminum copper is preferred in the second embodiment.
It should be noted that, in the cell region I, when the source body contact metal layer 121 makes ohmic contact with the source region 211 and the body contact region 212, the whole metal is in direct contact, rather than making metal contact through a contact hole, so that the manufacturing process and the device structure are simpler, and the process difficulty is reduced.
It should be further noted that in the prior art patent (application No.: 201110405658.7) that does not require a contact hole process, the body region itself is directly used to make the source region and the body region equipotential, while in the cell region I of the present invention, the body contact region 212 of the same type as the body region 213 is used to make the source region 211 and the body region 213 equipotential, so that the concentration of the body contact region 212 in the cell region I of the present invention may not be the same as the concentration of the body region 213, and the concentration of the body contact region 212 may be adjusted as needed, thereby further increasing the doping concentration of the body contact region 212 without changing the concentration of the body region 213, and further reducing the contact resistance between the body contact region 212 and the source body contact metal layer 122.
As shown in fig. 18, the gate electrical contact region II further includes a second insulating dielectric layer 92 and a gate contact metal layer 122, wherein each structure included in the gate electrical contact region II is as follows:
the second insulating dielectric layer 92 is formed on the first insulating dielectric layer 91, and a contact hole exposing the upper surface of the gate electrode is formed in the second insulating dielectric layer 92, wherein the contact hole formed in the second insulating dielectric layer 122 corresponds to the contact hole formed in the first insulating dielectric layer 91 so as to expose the upper surface of the gate electrode through the contact hole; further, the second insulating medium layer 92 is also formed on the third epitaxial layer of the gate electrical contact region II; the second insulating dielectric layer 92 is made of silicon oxide, silicon oxynitride or silicon nitride, and in the second embodiment, the second insulating dielectric layer 92 is made of silicon oxide.
The gate contact metal layer 122 is formed on the second insulating dielectric layer 92 and contacts the gate 81 through the contact hole of the first insulating dielectric layer 91 and the contact hole of the second insulating dielectric layer 92. The material of the gate contact metal layer 122 is aluminum, aluminum copper, aluminum silicon copper or copper, and in the second embodiment, aluminum copper is preferred.
As shown in fig. 18, the terminal protection region III further includes a body contact region 212, a third insulating dielectric layer 93, and a body contact metal layer 123, the first insulating dielectric layer 91 in the terminal protection region trench 53 is located on the gate 81 and is in contact with the gate dielectric layer 7 and the third insulating dielectric layer 93, where the structures further included in the terminal protection region III are as follows:
the body contact region 212, which is of the second conductivity type, is formed on top of the third epitaxial layer of the termination protection region III and over the body region 213, and the body contact region 212 is in contact with the termination protection region trench 53. In the second embodiment, the body contact region 212 is P-type, and preferably, the P-type dopant ion is B.
The third insulating medium layer 93 is formed on the third epitaxial layer of the terminal protection region III, a contact hole is formed in the third insulating medium layer 93, the contact hole exposes a part of the upper surface of the body region 212, and meanwhile, the third insulating medium layer 93 is in contact with the first insulating medium layer 91 formed in the terminal protection region groove 53; the third insulating dielectric layer 93 is made of silicon oxide, silicon oxynitride or silicon nitride, and in the second embodiment, the third insulating dielectric layer 93 is made of silicon oxide.
The body contact metal layer 123 is formed on the third insulating dielectric layer 93 and contacts the body contact region 212 located in the terminal protection region III through the contact hole of the third insulating dielectric layer 93. The material of the body contact metal layer 123 is aluminum, aluminum copper, aluminum silicon copper or copper, and in the second embodiment, aluminum copper is preferred.
It should be noted that, in the termination protection region III of the present invention, the concentration of the body contact region 212 may not be consistent with the concentration of the body region 213 located thereunder, so that the concentration of the body contact region 212 may be adjusted as required, thereby further increasing the doping concentration of the body contact region 212 without changing the concentration of the body region 213, and further reducing the contact resistance between the body contact region 212 and the body contact metal layer 123.
It should be further noted that, in the second embodiment, the line width of the deep trench formed with the gate dielectric layer 7 and the gate 81 is about 0.4 μm; for a 248nm DUV lithography machine, the minimum line width of the body contact region 212 is 0.16 μm; due to the limitation of the alignment accuracy of the contact hole and the deep trench, the width of the source region 211 contacting the cell trench 51 is at least 0.09 μm, so that the minimum achievable cell pitch (pitch) is about 0.76 μm in the second embodiment.
In summary, in the deep trench power MOS device and the manufacturing method thereof of the present invention, in the cell region, the body contact region that is prepared in an inversion manner and has the same type as the body region is used to make the source region and the body region have the same potential; when the minimum cell spacing can reach 0.76 mu m and the device is high in cell density, the part of the injection process adopts maskless Implantation (Blank Implantation), the process is simplified, and the process difficulty is reduced, and when the body contact region is injected, the minimum photoresist line width of 0.16 mu m is ensured, and the problem of reverse photoresist caused by the over-small photoresist width in the small line width photoetching process is avoided; in addition, the concentration of the body contact region and the concentration of the body region can be inconsistent, so that the concentration of the body contact region can be adjusted as required, and the doping concentration of the body contact region is further increased while the concentration of the body region is not changed, so that the contact resistance between the body contact region and the source body contact metal layer and between the body contact region and the body contact metal layer is reduced; in addition, the invention has determined that the electrical contact method of grid is the contact hole connection (big trench with contact pick-up) method on the wide ditch groove, utilize the characteristic that the ion bombardment ability of the pattern dense area is stronger than the open area in the dry etching craft ingeniously, while the electrical contact of grid realizes the electrical contact of metal level, have guaranteed source body contact metal level and grid in the area of unit cell can keep insulating; furthermore, in the grid electrical contact method, only the insulating medium layer is windowed to the upper surface of the grid positioned below the insulating medium layer, so that the process for preparing the contact hole in the conventional grid electrical contact method is improved, the situation that the insulating medium layer is etched and the grid positioned below the insulating medium layer is deeply etched during electrical contact in the conventional process is avoided, and the process difficulty is further reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A manufacturing method of a deep trench power MOS device is characterized by at least comprising the following steps:
1) providing a substrate, wherein the substrate comprises a drain region of a first conductivity type and a first epitaxial layer of the first conductivity type formed on the drain region, and the first epitaxial layer is transversely divided into a cell region, a gate electrical contact region and a terminal protection region;
2) depositing a hard mask on the upper surface of the substrate, and photoetching and etching the hard mask until the upper surface of the substrate is exposed to form a hard mask window;
3) etching the substrate through the hard mask window to form a plurality of regularly arranged and mutually parallel deep grooves in a first epitaxial layer of the substrate, wherein the deep grooves comprise cell grooves, grooves of a grid electrical contact area and grooves of a terminal protection area;
4) forming a gate dielectric layer on the upper surface of the substrate and in the deep groove;
5) depositing a grid electrode material layer on the grid electrode dielectric layer, wherein the deep groove is filled with the grid electrode material layer and covers the upper surface of the grid electrode dielectric layer on the surface of the substrate;
6) etching the grid material layer to enable the cell groove, the grid electrical contact region groove and the terminal protection region groove to be partially filled with the grid material layer to form a grid;
7) forming a third epitaxial layer of the second conductivity type on top of the first epitaxial layer, forming a source region of the first conductivity type on top of the third epitaxial layer, forming body contact regions of the second conductivity type on top of the third epitaxial layer at the cell regions to space the source regions, forming a body contact region contacting with the trench of the termination protection region on top of the third epitaxial layer located in the termination protection region, forming a first insulating medium layer with the upper surface positioned on the same plane with the upper surface of the substrate on the grid of the cellular groove, wherein the third epitaxial layer under the source region or/and the body contact region is a body region, the first epitaxial layer under the third epitaxial layer is a drift region, meanwhile, the depth of the third epitaxial layer is smaller than that of the deep groove, so that the deep groove extends to the top of the drift region and contacts with the adjacent body region or/and source region;
8) depositing an insulating medium layer on the upper surface of the structure obtained after the step 7), and then etching the insulating medium layer by a dry method to form a second insulating medium layer positioned in the grid electrical contact area and a third insulating medium layer positioned in the terminal protection area, wherein a contact hole exposing the upper surface of the grid is formed in the second insulating medium layer, a contact hole exposing the upper surface of the body contact area is formed in the third insulating medium layer, and the insulating medium layer positioned in the cellular area is etched until the upper surface of the substrate is exposed, but the first insulating medium layer positioned in the cellular groove is reserved;
9) depositing metal on the surface of the structure obtained after the step 8), and then forming a source body contact metal layer positioned in the cell area, a grid contact metal layer positioned in the grid electrical contact area, and a body contact metal layer positioned in the terminal protection area by adopting photoetching and etching processes, wherein the source body contact metal layer is in ohmic contact with the source area and the body contact area directly, the source body contact metal layer is insulated and isolated from the grid of the cell groove through a first insulating medium layer, the grid contact metal layer is in ohmic contact with the corresponding grid through a contact hole positioned in the grid electrical contact area, and the body contact metal layer is in ohmic contact with the corresponding body contact area through a contact hole positioned in the terminal protection area.
2. The method of manufacturing a deep trench power MOS device of claim 1, wherein: and a second epitaxial layer of the first conductivity type is arranged between the first epitaxial layer and the drain region and is used as a buffer region, namely the second epitaxial layer is formed on the drain region, and the first epitaxial layer is formed on the second epitaxial layer.
3. The method of manufacturing a deep trench power MOS device of claim 2, wherein: the doping concentrations of the drain region, the second epitaxial layer and the first epitaxial layer are sequentially reduced, wherein the drain region is of a heavily doped first conductivity type, and the first epitaxial layer is of a lightly doped first conductivity type.
4. The method of manufacturing a deep trench power MOS device of claim 1, wherein: and 4) before the gate dielectric layer is formed, growing a sacrificial oxide layer on the upper surface of the substrate and in the deep groove and then removing the sacrificial oxide layer so as to remove defects and impurities on the upper surface of the substrate, the side wall of the deep groove and the bottom of the deep groove.
5. The method of manufacturing a deep trench power MOS device of claim 1, wherein: and 5), the gate material layer is a doped gate material layer, wherein doping is carried out simultaneously when the gate material layer is deposited, or ion implantation and annealing processes are carried out after the gate material layer is deposited, so as to reduce the resistance of the gate material layer.
6. The method of manufacturing a deep trench power MOS device of claim 1, wherein: the specific steps of forming the third epitaxial layer, the source region and the body contact region in step 7) are as follows: forming a third epitaxial layer on the top of the first epitaxial layer by two times of maskless doping injection, and forming a source region on the top of the third epitaxial layer; and then, forming a concentration-adjustable body contact region in the source region of the cell region by adopting photoetching, ion implantation and annealing processes, and simultaneously converting a region of the first conductivity type above the body region in the terminal protection region into a second conductivity type to form the concentration-adjustable body contact region of the terminal protection region.
7. The method of manufacturing a deep trench power MOS device of claim 1, wherein: the step 7) of forming the first insulating dielectric layer specifically includes: and depositing an insulating medium layer on the grid electrode and the grid medium layer, and etching the insulating medium layer to ensure that the insulating medium layer is reserved on the surface of the cellular groove to form the first insulating medium layer.
8. The method for manufacturing a deep trench power MOS device according to any one of claims 1 to 7, wherein: in the step 7), the first insulating medium layer is formed before the third epitaxial layer, the source region and the body contact region are formed.
9. The method for manufacturing a deep trench power MOS device according to any one of claims 1 to 7, wherein: in the step 7), the first insulating medium layer is formed and then manufactured after the third epitaxial layer, the source region and the body contact region are formed.
10. A deep trench power MOS device, characterized in that the deep trench power MOS device comprises at least:
the cell area, the grid electrical contact area and the terminal protection area that are used for the grid electricity to connect of a plurality of regular arrangements and parallel arrangement cell each other, wherein, cell area, grid electrical contact area and terminal protection area all include:
a drain region of a heavily doped first conductivity type;
a drift region of a lightly doped first conductivity type formed on the drain region;
the third epitaxial layer is formed on the drift region and at least comprises a body region of the second conductivity type, wherein the body region is positioned at the bottom of the third epitaxial layer and is in contact with the drift region;
a plurality of deep trenches which are concavely arranged on the third epitaxial layer and comprise cell trenches, trenches of electrical contact regions of gates and trenches of terminal protection regions, the deep trenches penetrate through the body region and extend to the top of the drift region, gate dielectric layers are formed on the inner walls and the bottoms of the deep trenches, the deep trenches are also partially filled with the gates which are in contact with the gate dielectric layers, first insulating dielectric layers which are in contact with the gate dielectric layers are formed on the gates, and the upper surfaces of the first insulating dielectric layers, the openings of the deep trenches and the upper surface of the third epitaxial layer are all located in the same plane;
the cell area also comprises a source area, a body contact area and a source body contact metal layer, and each cell of the cell area comprises a cell groove; wherein,
the source region is of a heavily doped first conduction type, is formed at the top of the third epitaxial layer of the cellular region, is positioned above the body region and is contacted with the outer wall of each cellular groove, and a gap is formed between the source regions of the adjacent cells;
the body contact region is of a second conductivity type, is formed at the top of the third epitaxial layer of the cell region, is positioned above the body region, is positioned in the interval between the source regions of the adjacent cells and is in contact with the source regions;
the source body contact metal layer is positioned on the third epitaxial layer of the cellular region and is in ohmic contact with the source region and the body contact region, and meanwhile, the source body contact metal layer is insulated and isolated from the grid electrode of the cellular groove through a first insulating medium layer;
the grid electrode electric contact area also comprises a second insulating medium layer and a grid electrode contact metal layer; wherein,
the second insulating medium layer is formed on the first insulating medium layer, and a contact hole for exposing the upper surface of the grid electrode is formed in the second insulating medium layer;
the grid electrode contact metal layer is formed on the second insulating medium layer and is in contact with the grid electrode through the contact hole of the first insulating medium layer and the contact hole of the second insulating medium layer.
11. The deep trench power MOS device of claim 10, wherein: and a second epitaxial layer of the first conductivity type is arranged between the drift region and the drain region to serve as a buffer region, namely the second epitaxial layer is formed on the drain region, and the drift region is formed on the second epitaxial layer.
12. The deep trench power MOS device of claim 11, wherein: the doping concentrations of the drain region, the second epitaxial layer and the drift region are sequentially reduced, wherein the drain region is of a heavily doped first conduction type, and the drift region is of a lightly doped first conduction type.
13. The deep trench power MOS device of claim 10, wherein: the thickness of the first insulating medium layer is 10-500 angstroms.
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| CN103515444A (en) * | 2013-09-24 | 2014-01-15 | 哈尔滨工程大学 | Groove gate power MOS device |
| CN106384718B (en) * | 2016-10-21 | 2020-04-03 | 华润微电子（重庆）有限公司 | Manufacturing method and structure of medium-high voltage groove type MOSFET device |
| CN107579002A (en) * | 2017-08-01 | 2018-01-12 | 中航（重庆）微电子有限公司 | A kind of preparation method of trench type device |
| CN107611022B (en) * | 2017-09-02 | 2019-10-29 | 西安交通大学 | The silicon carbide IGBT device and preparation method of a kind of low on-resistance, small grid charge |
| CN111769157A (en) * | 2020-08-07 | 2020-10-13 | 上海维安半导体有限公司 | High density trench device structure and method of making same |
| CN114335170A (en) * | 2020-09-30 | 2022-04-12 | 苏州东微半导体股份有限公司 | Semiconductor power device |
| CN112820648B (en) * | 2020-12-31 | 2023-08-01 | 扬州扬杰电子科技股份有限公司 | Gallium nitride metal oxide semiconductor transistor and preparation method thereof |
| CN114420636A (en) * | 2021-12-22 | 2022-04-29 | 深圳深爱半导体股份有限公司 | Semiconductor device structure and preparation method thereof |
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