CN105448732B - Improve groove power semiconductor device of UIS performances and preparation method thereof - Google Patents
Improve groove power semiconductor device of UIS performances and preparation method thereof Download PDFInfo
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- CN105448732B CN105448732B CN201410443846.2A CN201410443846A CN105448732B CN 105448732 B CN105448732 B CN 105448732B CN 201410443846 A CN201410443846 A CN 201410443846A CN 105448732 B CN105448732 B CN 105448732B
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Abstract
The present invention relates to a kind of MOSFET semiconductor devices for power conversion, the groove power semiconductor device with preferable non-clamper perception switching ability is intended to provide, optimize the high avalanche breakdown ability of groove power semiconductor device and the method for preparing the device is provided.With the first contact hole extended downward into active region mesa and with the second contact hole extended downward into transition region mesa structure, wherein correspondence is bigger than depth value, the width value of the second contact hole respectively for the depth value of the first contact hole, width value.
Description
Technical field
The present invention relates to a kind of MOSFET semiconductor devices for power conversion, and more precisely, the present invention is directed to carry
For having the groove power semiconductor device of preferable non-clamper perception switching ability, optimize groove power semiconductor device
The avalanche breakdown ability of part simultaneously provides the method for preparing the device.
Background technology
In power semiconductor, based on the considerations of transistor unit density and other various advantages, grid can be with shape
Into among the groove extended downwardly from the surface of bulk silicon substrate, typical example is exactly that groove type metal oxide is partly led
Body field-effect transistor (MOSFET), for others such as the insulated gate bipolar transistor for further including plough groove type, they have one
A public feature is exactly all to include all kinds of grooves with various functions, but for the characteristic of device self structure, Mou Xieshi
It waits, the electric field strength at many channel bottoms shows that the maximum electric field for device is horizontal, is increased to device in voltage and enters snow
On the point collapsed, ionization by collision will occur in the corner avalanche breakdown process of groove, it may occur that breakdown generates avalanche current.Snowslide
Breakdown is generally easy to cause hot carrier's effect, and when puncturing close at grid oxic horizon, an adverse consequences is hot load
Stream can be captured and be injected into grid oxic horizon, this can damage or be broken grid oxic horizon, and it is long-term to induce power device
Integrity problem.In addition, such groove usually becomes the limiting factor that device reaches high-breakdown-voltage.
Another problem is that, if during low current level avalanche breakdown, the harm that breakdown will not be excessive occurs for termination environment
Hinder the performance of device, device need not worry trouble free service problem at this time.But once during some special work, for example, it is non-
During clamper perception switch (UIS) switching, since the electric current of inductance in circuit system will not be mutated, device is caused often to bear
Some bigger voltage strengths are equivalent to during device is in the horizontal avalanche breakdown event of high current, the terminal of limited area
Area is likely to will be unable to safely and effectively processing power loss, because a power device can not possibly the abatement effective transistor of device
The area of unit and ad infinitum distribute excessive area to termination environment, and consequence is exactly, the breakdown of termination environment can be used as one it is negative
Face effect affects the area of safety operaton of device (SOA), this is all that our institutes are undesired.
Exactly in view of such various difficult problems that the prior art is faced, it is considered herein that necessary limit device
In area of safety operaton (SOA) and under the conditions of being set in optimal non-clamper perception switch (UIS), readjust and be distributed in device
Electric field strength, power conversion apparatus is made to have preferable SOA and good UIS abilities, so the present invention is exactly before this
Put the every embodiment proposed in subsequent content.
Invention content
In one embodiment, the present invention propose a kind of preparation method of groove power semiconductor device, including with
Lower step：One Semiconductor substrate, the epitaxial layer comprising base substrate and above base substrate are provided；Etch epitaxial layer,
Form an annular isolation groove and the active groove on the inside of isolated groove, an active groove near isolated groove
It is active to terminal transition region there are one tools between isolated groove, between active area and termination environment；Fill conductive material extremely
In isolated groove, and grid is prepared in active groove；One insulating passivation layer of deposition is covered in semiconductor substrate；Etching
Insulating passivation layer and the respective mesa structure of transition region, active area form through insulating passivation layer, extend downward into active area platform
The first contact hole and formation in the structure of face run through insulating passivation layer, second extended downward into transition region mesa structure connects
Contact hole；Correspondence is bigger than depth value, the width value of the second contact hole respectively for depth value, the width value of first contact hole.
The above method, Semiconductor substrate has the first conduction type, before insulating passivation layer is deposited, first on the top of epitaxial layer
Portion's implantation dopant forms the body layer of second conduction type；And it is then at least planted at the top of the body layer of active area
Enter the top doped layer that dopant forms first conduction type.
The above method, in the step of forming contact hole：One mask is covered in above insulating passivation layer, and is at least formed
First, second opening in mask；While preparing the first contact hole with the first opening to etch, also etched with the second opening
The second contact hole is prepared, the size of the first aperture efficiency second opening is big.
The above method, in the step of forming contact hole：One first mask is covered on insulating passivation layer and
The first opening is at least formed in one mask, the first contact hole is prepared with the first opening etching；After removing the first mask, by one second
Mask is covered on insulating passivation layer and the second opening is at least formed in the second mask, and second is prepared with the second opening etching
Contact hole；Opening size of first aperture efficiency second opening with bigger.
The above method, by first, second contact hole, injection and ontology into transition region, active area respective body layer
Layer doping type is identical, but the dopant of doping concentration bigger is to form body contact region；Due to the second contact hole opposite first
Contact hole and smaller depth value, width value, make the body contact region ratio for being formed in the second contact hole bottom periphery be formed in
The body contact region depth of one contact hole bottom periphery is more shallow, range of scatter smaller.
In one embodiment, the present invention proposes a kind of groove power semiconductor device, including：One semiconductor lining
Bottom, the epitaxial layer comprising base substrate and above base substrate；A setting annular isolation groove in the epitaxial layer and
Active groove on the inside of isolated groove, one near the isolated groove is between active groove and isolated groove there are one tools
It is active to terminal transition region, between active area and termination environment；Inside be lining in isolated groove, active groove bottom and side wall it is exhausted
Edge layer and the conductive material being arranged in isolated groove and the grid being arranged in active groove；It is covered in Semiconductor substrate
One insulating passivation layer of top；Through insulating passivation layer, the first contact hole in active region mesa is extended downward into, is passed through
It wears insulating passivation layer, extend downward into the second contact hole in transition region mesa structure；Depth value, the width value of first contact hole
Correspondence is bigger than depth value, the width value of the second contact hole respectively.
Above-mentioned groove power semiconductor device, metal plug in first, second contact hole and blunt set on insulating
Change the metal plug in alignment isolated groove in the contact hole of conductive material in layer, all overlapped on insulating passivation layer top active
Top metal electrode on area, transition region and isolated groove is in electrical contact.
Above-mentioned groove power semiconductor device, Semiconductor substrate have the first conduction type, are formed at the top of epitaxial layer
There is the body layer of one second conduction type and the top of one first conduction type is at least formed at the top of the body layer of active area
Portion's doped layer；Wherein first, second contact hole is terminated in body layer.
Above-mentioned groove power semiconductor device is implanted with the second conductive-type in the bottom periphery of first, second contact hole
The body contact region of type；Wherein, the depth of the body contact region of the second contact hole bottom periphery, range of scatter, correspond to ratio respectively
The depth of the body contact region of first contact hole bottom periphery, range of scatter are small.Device is not clamping inductive switches UIS
Transition period, when avalanche breakdown occurs, PN junction occurs not trigger also during avalanche breakdown between active area body layer and epitaxial layer
Avalanche breakdown at isolated groove bottom corners.
Above-mentioned groove power semiconductor device is arranged on the grid in active groove and includes being located at lower part in active groove
Dhield grid and the control grid positioned at active groove internal upper part, and dhield grid and control grid between be provided with insulation
They are dielectrically separated from by layer；Dhield grid has identical potential with the conductive material in isolated groove.
In another alternative embodiment, present invention is disclosed a kind of groove power semiconductor device, including：One and half
Conductor substrate, Semiconductor substrate include base substrate and the epitaxial layer above base substrate；With multiple first grooves, and
The first table top being arranged between adjacent first trenches and the second table top being arranged between first groove and second groove,
In first, second, and third groove extended among epitaxial layer from the upper surface of epitaxial layer；The first table top is arranged on from epitaxial layer
Upper surface extend to the source area of the first depth among epitaxial layer, which has and the identical conductive-type of epitaxial layer
Type and the entire width for extending the first table top；Be arranged on the first table top extend downwardly into epitaxial layer from the bottom of source area among
The first noumenon area of two depth, the first noumenon area have the conduction type opposite with epitaxial layer and extend the entire width of the first table top
Degree；Be arranged on the second table top extend to epitaxial layer from the upper surface of epitaxial layer among third depth the second body zone, second
Body area has the conduction type opposite with epitaxial layer and extends the entire width of the second table top；It is extended through from the upper surface of epitaxial layer
The first contact hole that source area reaches the first noumenon area is crossed, the first contact hole is filled by conductive material；From the upper surface of epitaxial layer
The second contact hole of the second body zone is extended to, the second contact hole is filled by conductive material；Wherein the depth value of the first contact hole,
Correspondence is bigger than depth value, the width value of the second contact hole respectively for width value.
Above-mentioned groove power semiconductor device, the first groove is active groove, internal to be filled with conduction material
Material, the conductive material in first groove insulate with epitaxial layer and form trench-gate.
Above-mentioned groove power semiconductor device, second groove filling conductive material are described in second groove
Conductive material insulate with epitaxial layer, and second groove forms isolated groove.
Above-mentioned groove power semiconductor device, the third depth and the second depth have identical depth.
Above-mentioned groove power semiconductor device further includes the ontology conductive type doped region for being arranged on the first contact hole bottom
Or body contact region, doping concentration are more taller than the doping concentration in the first noumenon area.
Above-mentioned groove power semiconductor device further includes the ontology conductive type doped region for being arranged on the second contact hole bottom
Or body contact region, doping concentration are more taller than the doping concentration of second body zone.
Above-mentioned groove power semiconductor device, the third groove surround the first and second grooves.
Above-mentioned groove power semiconductor device fills the conductive material of the first contact hole and leading for the second contact hole of filling
Electric material is electrically connected.
Above-mentioned groove power semiconductor device, to be filled with conductive material in the third groove of termination groove,
The conductive material insulate with epitaxial layer in third groove.
Above-mentioned groove power semiconductor device, further includes the body zone at the top of the epitaxial layer being arranged on the outside of third groove
In third contact hole, the conductive material filled wherein in third contact hole is electrically connected with the conductive material of filling third groove.
Description of the drawings
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Fig. 1 is the partial top view that the device of the present invention contains termination groove, isolated groove and active groove.
Fig. 2A~2J is the method flow schematic diagram for preparing trenched MOSFET devices.
The step of Fig. 3 A~3B are based on Fig. 2A~2J but the contact hole that different depth and width are prepared using two masks；
Fig. 4 A show termination environment to the contact hole of active area interface and the contact hole of active area in same widths and depth
Under conditions of degree, the substantially electric field strength of the isolated groove adjacent corner of the interface one；
Fig. 4 B show that the isolated groove corner portion of termination environment to active area interface in the structure of Fig. 4 A occurs snowslide and hits
The general diagram of avalanche current flow direction when wearing；
Fig. 5 A show termination environment to the contact hole of active area interface and the contact hole of active area in different in width and depth
Under conditions of degree, the substantially electric field strength of the isolated groove adjacent corner of the interface one；
Fig. 5 B show that the isolated groove corner portion of termination environment to active area interface in the structure of Fig. 5 A occurs snowslide and hits
The general diagram of avalanche current flow direction when wearing.
Specific embodiment
In fig. 2, in trenched MOSFET devices, a Semiconductor substrate includes the base substrate of a heavy doping
100 and including an opposing floor portion substrate 100 and doping concentration wants much lower epitaxial layer 110, their conductiving doping type
Identical, subsequent content is illustrated using the epitaxial layer 110 of the base substrate 100 of N+ and N- as demonstration.Not illustrate in scheming
A mask with patterns of openings epitaxial layer 110 is implemented to etch, form respectively from the upper table of epitaxial layer 110 towards
Termination groove 101, isolated groove 102 and the multiple active grooves 103 of lower extension, their bottom is terminated in epitaxial layer 110.
In order to understand the layout type between each groove more in detail, in the vertical view of Fig. 1, the half of a separate wafer is illustrated
The Local map of conductor substrate, chip have the edge 125 that dotted line represents, and in an annular isolated groove of Semiconductor substrate
102 inside is formed with multiple active grooves 103 in Semiconductor substrate, is then Semiconductor substrate in 102 outside of isolated groove
Termination environment 200, termination environment 200 around isolated groove 102, and in termination environment 200 formed there are one annular termination
Groove 101 leans on proximal edge 125.
In fig. 2b, first an insulating layer 101b is formed in termination 101 side wall of groove and bottom and in isolated groove 102
Side wall and bottom form an insulating layer 102b and form an insulating layer in the side wall of each active groove 103 and bottom
103b, these insulating layers 101b, 102b, 103b can synchronize to be formed, such as the silicon dioxide layer grown by hot oxygen technique.
In the step of Fig. 2 B~2C, need to fill conductive material in each trench interiors again, such as fill the polycrystalline silicon material of doping and arrive
Among termination groove 101, isolated groove 102 and active groove 103.But it needs the conduction material on each 103 top of active groove
Material performs back quarter to remove, and the conductive material for only retaining each 103 lower part of active groove forms a bucking electrode
(SGT) hereafter 103a recycles LPCVD or PECVD to prepare such as SiO2Insulating materials, be filled in 103 top of active groove
In the clearance space formed due to removal conductive material, to be covered on bucking electrode 103a.And it returns carve gap sky immediately
Between in insulating materials and the original insulating layer 103b of 103 upper portion side wall of active groove, they are removed, only retain be located at
A layer insulating 103c above bucking electrode 103a.Thereafter the exhausted of densification is generated on the side wall on 103 top of active groove again
Edge layer 103d such as SiO2As grid oxic horizon, and refill and lead again in the clearance space on each 103 top of active groove
Electric material prepares a control grid 103e.In active groove 103, the insulating layer 103d as grid oxic horizon is than active
The insulating layer 103b retained on the side wall of 103 lower part of groove is thin, and control grid 103e is overlapped on bucking electrode 103a, but
It is electrically insulated from one another by the insulating layer 103c between them.Control grid 103e having as mosfet transistor unit
Imitate gate electrode, but each bucking electrode 103a be then all coupled to MOSFET source electrode and with source electrode equipotentiality, in this way can be with
The appropriate parasitic capacitance C reduced between grid drain electrodegd。
In fig. 2 c, FET unit is formed on active area 300, and active groove 103 is used as MOSFET crystal
The gate trench of pipe unit or structure cell has multiple such active grooves 103 in the preparation of active area 300 of Semiconductor substrate.
Between an active groove 103-1 and isolated groove 103 near isolated groove 102 tool there are one it is active to terminal transition region or
Interface area (Active to termination interface area) 250, the transition region 250 of Semiconductor substrate is between having
Between source region 300 and termination environment 200, many times in fact it is also assumed that transition region 250 is to play the work of terminal structure
With.In order to distinguish, in all active grooves 103, it is what all that was arranged side by side to define active groove 103-1
Outermost groove in active groove 103, at the same also near isolated groove 102 be parallel to active groove 103 that
Point, the region between outermost this active groove 103-1 and isolated groove 102 is defined as transition region 250.According to Fig. 1 and
Fig. 2 C can be learned, in the inside of isolated groove 102, other than active area 300, and also transition region 250.
Fig. 2A~2C is only the exemplary packing material or control grid, shield grid for giving and preparing in respective groove
The method of pole, but the structure of Fig. 2 C is actually prepared, method is not unique, and also many embodiments can be realized, considers
These steps are not the most important contents of the present invention, so only very rough introduction.
Isolated groove 102 and its neighbouring active groove 103-1 define a table top of Semiconductor substrate between them
Structure (Mesa) 250a, and semiconductor serves as a contrast between the active groove 103 of arbitrary neighborhood then defines two neighboring active groove 103
One mesa structure 300a at bottom.
In figure 2d, body layer 120 and top doped layer 130 are prepared for, wherein top doped layer 130 is in active area 300
It is presented as the source area of transistor unit.For example, in a manner of to be implanted into comprehensively (blanket implant), mixing for P types is utilized
Heteroion is implanted to the top of entire epitaxial layer 110, prepares a P-type body layer 120 for being located at 110 top of epitaxial layer, surrounds
In lateral wall circumference of these grooves compared with top.Thereafter, then the Doped ions of N+ types is recycled to be implanted to the ontology of active area 300
The top of layer 120 prepares the top doped layer 130 of a N+ type at the top of the body layer 120 of active area 300, has been centered around
Source groove 103 in the illustrated embodiment, has only been implanted into doped layer 130 compared with the lateral wall circumference on top in mesa structure 300a,
And the mesa structure 250a not on the outside of active groove 103-1 is implanted into doped layer 130.Pay attention to the implantation depth of body layer 120,
Ensure that it is slightly above the basal surface position for controlling grid 103e with interface of the epitaxial layer 110 near active groove 103, so as to
In body layer 120 vertical inversion layer can be formed along the side wall of active groove 103 to establish raceway groove.Although without special
Explanation, although it is understood that ion implanting also tend to along with annealing spread the step of.Although in the embodiment of Fig. 2 D, only
Top doped layer 130 is formd in the body layer 120 of active area 300, not in the ontology of transition region 250 and termination environment 200
Doped layer 130 is formed on 130 top of layer, but in some other alternative embodiments, can be with comprehensive injection side of globality
Formula, while doped layer 130 at the top of being formed together at the top of body layer 130 of transition region 250 and termination environment 200, at this time without
Additional shield mask is used in the step of ion implanting.
In Fig. 2 E, side deposits an insulating passivation layer 140 on a semiconductor substrate, covers the upper table of epitaxial layer 110
Face, while be also covered on termination groove, isolated groove and each active groove.It is typical for example to prepare insulating passivation layer 140
The deposit low temperature oxide LTO and/or silica glass BPSG containing boric acid.In fig. 2f, insulating passivation layer is covered in mask 400
On 140, such as coating photoresist layer, after the exposure imaging by well known photolithography technology, multiple open is prepared in mask 400
Mouth (400a~400e).In these openings, the local ontology in 101 outside of termination groove of opening 400a alignments termination environment 200
Layer 120, the opening 400b alignment interior conductive material 101a filled of termination groove 101, and be open in 400c alignment isolated grooves 102
The conductive material 102a of filling, opening 400d alignment mesa structure 250a, opening 400e alignment mesa structures 300a.In addition, it covers
The opening of some other functions does not illustrate in film 400, such as is filled out for being aligned in grid pickup groove (gate pickup)
The opening of the grid material filled does not illustrate.
One aspect of the invention is that the size for making the size ratio opening 400d of opening 400e is some larger, for side
Just it distinguishes, the 400e that can sometimes be open is referred to as the first opening, and opening 400d is known as the second opening.
In fig 2g, using mask 400 as etch mask, contact hole is prepared with anisotropic dry etch, successively to
Lower etching insulating passivation layer 140, Semiconductor substrate, etching are terminated in body layer 120.Using the 400d that is open, etching forms
The contact hole 504 of the mesa structure 250a of transition region is directed at, using the 400e that is open, etching forms alignment active region mesa
The contact hole 505 of 300a.For the convenience of differentiation, it is the first contact hole that can be referred to as or define contact hole 505, defines contact hole
504 be the second contact hole, and definition contact hole 501 is third contact hole.
The contact hole 504 of preparation is through insulating passivation layer 140 and extends in mesa structure 250a, and terminate in transition region
In the body layer 120 of mesa structure 250a.The contact hole 505 of preparation is through insulating passivation layer 140 and extends to mesa structure
In 300a, and run through the top doped layer 130 of active area and terminate in the body layer 120 of active region mesa 300a.By
In the opening 400e reasons bigger than the opening size for the 400d that is open, lead to the etching of the material speed that 400e lower sections expose that is open
Rate, than opening 400d below material etch rate it is many soon, and faster etch rate can be further formed it is deeper
Contact hole.So in the etch step of contact hole, producing both sides influences, one is active region contact hole 505
Depth value is bigger than the depth value of transition region contact hole 504, the second is the width value of contact hole 505 or lateral cross-sectional dimension ratio
The width value or lateral cross-sectional dimension of contact hole 504 are big.It is known that contact hole 505 extends to semiconductor lining from Fig. 2 G
Part 505a in bottom firmly gets more than the part 504a that contact hole 504 is extended in Semiconductor substrate.
In etch step in fig 2g, also synchronous etching forms contact hole 501,502,503 etc..Wherein utilize opening
400a etches to form contact hole 501, etches to form contact hole 502 and etch to be formed using the 400c that is open using the 400b that is open and connects
Contact hole 503.Since opening 400a is located at 101 outside local ontology layer of termination groove, 120 top, the contact hole 501 of formation runs through
Insulating passivation layer 140, and extend into termination environment 200 in the body layer 120 for being located at 101 outside of termination groove, if termination ditch
120 top of body layer in 101 outside of slot also implants top doped layer 130, then contact hole 501 also extends through the top doping at this
Layer 130.In addition, contact hole 502 is through insulating passivation layer 140 and exposes the conductive material 101a filled in termination groove 101,
Contact hole 503 is through insulating passivation layer 140 and exposes the conductive material 102a filled in isolated groove 102.
In Fig. 2 H, in order to form the body contact region of the contact hole bottom of active area and transition region, an ion is performed
The step of injection, the injection of this step intermediate ion or p-type dopant are realized in a self-aligned manner.The ion and body layer of implantation
120 conduction type is identical, but bigger than the doping concentration of body layer 120, is P+ type.By contact hole 504, it is implanted in transition
Ion in the body layer 120 in area 250 forms the body contact region 601 in mesa structure 250a, is located at contact hole 504
Bottom periphery.By contact hole 505, the ion being implanted in the body layer 120 of active area 300 forms mesa structure 300a
In be located at 505 bottom periphery of contact hole body contact region 602.The step of ion implanting also tends to spread along with annealing.By
It is bigger than the width dimensions of contact hole 504 in the width dimensions of contact hole 505, so the total ion concentration injected from contact hole 505
It is many more than the total ion concentration that is injected from contact hole 504, thus the range of scatter of body contact region 602 is then caused to be connect than ontology
The range of scatter for touching area 601 is big, and in other words, 601 volume of volume ratio body contact region of final body contact region 602 is big.Separately
Outside, since contact hole 504 extends to the part in substrate inherently than shallower, it is clear that the body contact region of 504 bottom of contact hole
601 naturally also just much lighters than the depth in the semiconductor substrate of the body contact region 602 of 505 bottom of contact hole.
In Fig. 2 I, in some embodiments, often first in the bottom of each contact hole 501~505 and side wall and exhausted
Barrier metal layer is deposited on the upper surface of edge passivation layer 140, then the redeposited metal material (such as tungsten) not illustrated is covered in
In barrier metal layer, a part for metal material, which also synchronizes, to be filled in each contact hole 501 to 505, returns quarter metal material later
Material removes the part metals material of 140 top of insulating passivation layer, but retains the barrier metal in each contact hole 501 to 505
Layer and the metal material of filling, can form metal plug 555 or metal joint.
In Fig. 2 J, the metal layer not illustrated in a figure is prepared, is deposited on the top of entire insulating passivation layer 140,
If 140 upper surface of insulating passivation layer has been previously deposited barrier metal layer, metal layer be substantially be covered in barrier metal layer it
On.Later they are implemented to pattern, divide the metal layer and barrier metal layer below, form Metal field plate 611 and pushed up
Portion's metal electrode 612 is disconnected and electrically isolated between them.In addition, the additional coverage also on the bottom surface of base substrate 100
There is another metal layer as bottom metal electrode 613, it forms Ohmic contact between the base substrate 100 of heavy doping.Absolutely
Field plate 611 on edge passivation layer 140 is arranged on termination environment 200, at least to overlap on termination groove 101 and overlap on contact
The top of hole 501, so as to electrical with the metal plug 555 in contact hole 501 and with the metal plug 555 in contact hole 502 simultaneously
Contact so that be located at the conduction filled in the body layer 120 and termination groove 101 in 101 outside of termination groove in termination environment 200
Material 101a is electrically connected, in identical potential.If the top of the body layer 120 in 101 outside of termination groove has been implanted
Top doped layer 130, top doped layer 130 at this also with 555 short circuit of metal plug in contact hole 501, so as to termination
Conductive material 101a equipotentiality in groove 101.It terminates groove 101 and ends (channel stop) structure as channel.
In addition, the top metal electrode 612 on insulating passivation layer 140 is then provided at least at transition region 250 and active
Area 300, and at least overlap on isolated groove 102 and overlap on mesa structure 250a, 300a.In this case, it contacts
The conductive material 102a filled in isolated groove 102 is electrically connected to top metal electrode by the metal plug 555 in hole 503
On 612, the body layer 120 of transition region 250 is electrically connected to top metal electrode 602 by the metal plug 555 in contact hole 504
On.And the metal plug 555 in contact hole 505 is then using the top doped layer 130 and body layer as source area in active area 300
Source area and body layer 130 are also further electrically connected in top metal electrode 612 by 130 short circuits.It is worth noting that,
In optional nonessential embodiment, in the dimension not illustrated, the active groove 103 of strip can be with isolated groove 102
Perpendicular to active groove 103 a part connection, so as in each active groove 103 the bucking electrode 103a of lower part with every
From the conductive material 102a interconnection filled in groove 102, so equally can also be electrically connected to top metal electrode 612.But it controls
Grid 103e processed is not interconnected with the conductive material 102a mutually insulateds filled in isolated groove 102.In the dimension not illustrated
On, the control grid 103e of all 103 internal upper parts of active groove is connected with each other, and is connected in grid pickup groove and is filled
Grid material on, and have the grid material filled in some contact holes alignment grid pickup groove, can set inside them
Metal plug is put, grid 103e will be controlled to export on the gate metal of 140 top of insulating passivation layer.
Due to source electrode of the top metal electrode 612 as MOSFET element, bottom metal electrode 613 is used as MOSFET devices
The drain electrode of part, so the top of the body layer 120 for including transition region and active area of 102 inside of isolated groove, active area 300
Portion's doped layer 130 all with source electrode equipotentiality (if transition region 250 have top doped layer 130 if its also with source electrode equipotentiality), shielding electricity
The conductive material 102a filled in pole 103a and isolated groove 102 also with source electrode equipotentiality.
In the embodiment of Fig. 3 A~3B, for etching the opening 400e (the first opening) for preparing contact hole 505 with being used for
The opening 400d (the second opening) that etching prepares contact hole 504 is not formed on same mask.It for example can be exhausted in passivation
The first mask 401 is coated in edge layer 140, forms the opening 400e in the first mask 401 in advance, and synchronize and yet form other
Be open 400a, 400b, 400c, but does not form opening 400d.First it is sequentially etched down be open 400a, 400b, 400c, 400e
The insulating passivation layer 140 of side, Semiconductor substrate correspondingly form contact hole 501,502,503,505, then remove respectively
Fall the first mask 401.Thereafter another second mask 402 is coated on insulating passivation layer 140 again, and in the second mask 402
Opening 400d is formed, insulating passivation layer 140, the Semiconductor substrate of lower section are sequentially etched with the 400d that is open, forms contact hole 504.
The feature of contact hole 501~505 is identical with previous embodiment, and only difference only etches preparation opportunity and changed
Become.
In addition, in another embodiment not illustrated, can first be formed in the first mask 401 opening 400a,
400b, 400c, 400d to prepare contact hole 501,502,503,504, then remove the first mask 401.Thereafter again second
Opening 400e is formed in mask 402, to prepare contact hole 505.
It is without being limited thereto, it is also an option that forming opening 400a, 400b, 400c not in the first mask 401, and covered second
Opening 400a, 400b, 400c are formed in film 402.Namely opening 400e is first formed in the first mask 401, prepare contact hole 505
Later, the first mask 401 is removed.Thereafter opening 400a, 400b, 400c, 400d are formed in the second mask 402 again, to prepare
Contact hole 501,502,503,504.Alternatively, opening 400d, after preparing contact hole 504, stripping are first formed in the first mask 401
From the first mask 401.Thereafter opening 400a, 400b, 400c, 400e are formed in the second mask 402 again, to prepare contact hole
501、502、503、505。
As long as in short, ensureing that opening 400e ratio openings 400d has the opening size of bigger, take this to prepare than contact hole 504
Deeper and broader contact hole 505, any mode are suitable for the present invention.
In Figure 4 A, according to the prior art, it is assumed that extend to the contact hole 504' in mesa structure 250a in Semiconductor substrate
In part have depth D'1, and assume extend to the part of contact hole 505 in the semiconductor substrate in mesa structure 300a
With depth D2, D'1=D2.In the UIS load applications of device, the potential of bottom metal electrode 613 compares top metal electrode
612 is much higher, and especially device is in and does not clamp inductive switches UIS (Unclamped Inductive Switching) and cut
During changing event.It is distributed to understand the electric field in device in detail, at 103 bottom corners of isolated groove 102 and active groove
Etc. the substantially schematic diagrames of electric field strengths be depicted in Figure 4 A, not only the electric field strength at 102 bottom corners of isolated groove is remote
It is much bigger more than the field strength at the PN junction between the body layer 120 of active area 300 and epitaxial layer 110, and 102 bottom of isolated groove
Electric field strength at 103 bottom corners of electric field ratio active groove of corner of portion is also big so that the bottom of isolated groove 102
The phenomenon that corner of portion will be a main avalanche breakdown weakness, this is one bad.The breakdown voltage of transition region 250 is less than
The breakdown voltage of active area 300, high pressure avalanche breakdown will be happened at the high electric field at 102 bottom corners of isolated groove of Fig. 4 A
Intensity locations, avalanche current will pour in transition region 250, as shown in Figure 4 B at 102 bottom corners of isolated groove near induce
Avalanche current 700 flow direction, so as to weaken the avalanche capability performance of device.In UIS events, the limited face of transition region 250
Product is difficult that processing power is lost, this serious area of safety operaton SOA for affecting device.
In fig. 5, according to the present invention, the portion of contact hole 504 in the semiconductor substrate in mesa structure 250a is extended to
Divide 504a that there is depth D1, extend to the part of contact hole 505 in the semiconductor substrate in mesa structure 300a with depth
D2, at this time D1 ＜ D2.In the UIS load applications of device, at 103 respective bottom corners of isolated groove 102 and active groove
Etc. field strength at PN junction between electric field strengths and the body layer 120 of active area 300 and epitaxial layer 110, be substantially depicted in Fig. 5 A
In.In body layer 120, the ontology of 505 bottom periphery of opposite contact hole of body contact region 601 of 504 bottom periphery of contact hole
Contact zone 602 and the small volume that seems, depth are shallower.For situations of Fig. 5 A with respect to Fig. 4 A, isolated groove 102 and active ditch
At PN junction in electric field strength and active area 300 at 103 respective bottom corners of slot between body layer 120 and epitaxial layer 110
Field strength change.It is embodied in, the electric field strength being weakened at isolated groove 102,103 bottom corners of active groove induces
The probability of snowslide can almost ignore completely instead, body layer 120 and 110 interface of epitaxial layer in active area 300
PN junction generate highest vertical electric field in the center of mesa structure 300a, this center is generally also adjacent two
Center between a active groove 103, and electric field ratio isolated groove 102,103 bottom corners of active groove at this
The electric field strength at place is much greater.So in fig. 5, device has in during not clamping inductive switches UIS handover events
Center position of the interface (PN junction) between neighboring active groove 103 between the body layer 120 of source region and epitaxial layer 110
Become main breakdown weak points, will no longer be avalanche breakdown weakness at the bottom corners of isolated groove 102, it is active so as to cause
The leading triggering avalanche breakdown of ontology-epitaxial layer PN junction in area 300, so Fig. 5 B and Fig. 4 A are by contrast, high pressure avalanche breakdown is not
It is to be happened at 102 bottom corners of isolated groove again.After the high pressure avalanche breakdown of Fig. 5 B shows, in active area ontology-epitaxial layer
Between the avalanche current 700' that induces at PN junction flow to trend.It can learn, originally in the snowslide of the transition region of limited area 250
Electric current is all transferred to the larger active area 300 of area.This avoids the hot carrier generated from breakdown area by insulating layer
102b is captured, and prevents from generating damage to the insulating layer 102b of 102 bottom of isolated groove, it is often more important that, due to avalanche current
Transfer improves the robustness of trenched MOSFET devices.Therefore, it is quite necessary to the transition region and active area of appropriate design
It contacts hole depth and changes the depth location of body contact region, appropriate change electric field is distributed, and makes the breakdown potential of power MOSFET
Pressure reaches maximum, and to improve the UIS performances of groove MOSFET, spirit of the invention can meet these requirements just.
It in the embodiment of Fig. 5 A~5B, can learn, the body layer 120 and extension of transition region (there is contact hole 504)
Interface between layer 110 is still horizontal, however the body layer 120 and epitaxial layer 110 of active area (having contact hole 505)
Between interface but slightly to lower recess, this is largely to be attributed to the p-type dopant diffusion of body contact region 602 to lure into
The downwardly convex reason of body layer 120, the center position p-type dopant between two neighboring active groove 103 spreads most
It is deep namely body layer 120 extends downwardly and protrudes most deep at this center.In other words, although transition region ontology-epitaxial layer
PN junction is still parallel plane knot, but active area ontology-epitaxial layer PN junction is no longer ideal parallel plane knot, is taken and generation
, profile is substantially the bending knot of curved surface, and electric field is easier to gather at this, and breakdown is easier to occur.
More than, by explanation and attached drawing, give the exemplary embodiments of the specific structure of specific embodiment, foregoing invention
Existing preferred embodiment is proposed, but these contents are not intended as limiting to.For a person skilled in the art, in reading
State it is bright after, various changes and modifications undoubtedly will be evident.Therefore, appended claims, which should be regarded as, covers the present invention
True intention and range whole variations and modifications.In Claims scope the range of any and all equivalence with it is interior
Hold, be all considered as still belonging to the intent and scope of the invention.
Claims (20)
1. a kind of preparation method of groove power semiconductor device, which is characterized in that include the following steps：
Semi-conductive substrate, the epitaxial layer comprising base substrate and above base substrate are provided；
Epitaxial layer is etched, an annular isolation groove and the active groove on the inside of isolated groove are formed, near isolated groove
An active groove and isolated groove between have it is one active to terminal transition region, between active area and termination environment；
It fills in conductive material to isolated groove, and grid is prepared in active groove；
It deposits an insulating passivation layer and is covered in semiconductor substrate；
Insulating passivation layer and the respective mesa structure of transition region, active area are etched, is formed through insulating passivation layer, extended downward into
The first contact hole and formation in active region mesa run through insulating passivation layer, extend downward into transition region mesa structure
The second contact hole；
Correspondence is bigger than depth value, the width value of the second contact hole respectively for depth value, the width value of first contact hole.
2. the method as described in claim 1, which is characterized in that Semiconductor substrate has the first conduction type, blunt in deposition insulation
Before changing layer, first in the body layer of the top of epitaxial layer implantation dopant one second conduction type of formation；And
Then at least in the top doped layer of the top of the body layer of active area implantation dopant one first conduction type of formation.
3. the method as described in claim 1, which is characterized in that in the step of forming contact hole：
One mask is covered in above insulating passivation layer, and at least forms first, second opening in mask；
While preparing the first contact hole with the first opening to etch, the second contact hole also is prepared to etch with the second opening, the
The size of one aperture efficiency second opening is big.
4. the method as described in claim 1, which is characterized in that in the step of forming contact hole：
One first mask is covered on insulating passivation layer and the first opening is at least formed in the first mask, with the first opening
Etching prepares the first contact hole；
After removing the first mask, one second mask is covered on insulating passivation layer and at least forms second in the second mask
Opening prepares the second contact hole with the second opening etching；
Opening size of first aperture efficiency second opening with bigger.
5. method as claimed in claim 2, which is characterized in that each to transition region, active area by first, second contact hole
From body layer in injection it is identical with body layer doping type, but the dopant of doping concentration bigger is to form body contact region；
Due to the second contact hole with respect to the first contact hole smaller depth value, width value, make to be formed in the second contact hole bottom
Body contact region around is more shallow than the body contact region depth for being formed in the first contact hole bottom periphery, range of scatter smaller.
6. a kind of groove power semiconductor device, which is characterized in that including：
Semi-conductive substrate, the epitaxial layer comprising base substrate and above base substrate；
An annular isolation groove in the epitaxial layer and the active groove on the inside of isolated groove are set, near isolated groove
An active groove and isolated groove between have it is one active to terminal transition region, between active area and termination environment；
Isolated groove, the insulating layer of active groove bottom and side wall and the conductive material that is arranged in isolated groove are inside lining in,
With the grid being arranged in active groove；
It is covered in an insulating passivation layer of semiconductor substrate；
Through insulating passivation layer, the first contact hole in active region mesa is extended downward into, through insulating passivation layer, downwards
Extend to the second contact hole in transition region mesa structure；
Correspondence is bigger than depth value, the width value of the second contact hole respectively for depth value, the width value of first contact hole.
7. groove power semiconductor device as claimed in claim 6, which is characterized in that in first, second contact hole
Metal plug and in insulating passivation layer be aligned isolated groove in conductive material contact hole in metal plug, all with
The top metal electrode overlapped on active area, transition region and isolated groove above insulating passivation layer is in electrical contact.
8. groove power semiconductor device as claimed in claim 6, which is characterized in that Semiconductor substrate has the first conductive-type
Type is formed with the body layer of one second conduction type and at least in the top shape of the body layer of active area at the top of epitaxial layer
The top doped layer of the first conduction types of Cheng Youyi；
Wherein first, second contact hole is terminated in body layer.
9. groove power semiconductor device as claimed in claim 8, which is characterized in that at the bottom of first, second contact hole
The body contact region of the second conduction type is implanted with around portion；
Wherein, the depth of the body contact region of the second contact hole bottom periphery, range of scatter correspond to the first contact hole bottom of ratio respectively
The depth of body contact region around portion, range of scatter are small.
10. groove power semiconductor device as claimed in claim 6, which is characterized in that the grid being arranged in active groove
Pole includes being located at the dhield grid of lower part and the control grid positioned at active groove internal upper part in active groove, and in dhield grid
Insulating layer is provided between control grid to be dielectrically separated from them；
Dhield grid has identical potential with the conductive material in isolated groove.
11. a kind of groove power semiconductor device, which is characterized in that including：
Semi-conductive substrate, the epitaxial layer comprising base substrate and above base substrate；
The second table top between the first table top and first groove and second groove that are arranged between adjacent first trenches, wherein
First, second, and third groove is extended to from the upper surface of epitaxial layer among epitaxial layer；
The source area that the first table top extends to the first depth among epitaxial layer from the upper surface of epitaxial layer is arranged on, source area has
The conduction type identical with epitaxial layer and the entire width of the first table top of extension；
Be arranged on the first table top extend downwardly into epitaxial layer from the bottom of source area among the second depth the first noumenon area, first
Body zone has the conduction type opposite with epitaxial layer and extends the entire width of the first table top；
Be arranged on the second table top extend to epitaxial layer from the upper surface of epitaxial layer among third depth the second body zone, second
Body area has the conduction type opposite with epitaxial layer and extends the entire width of the second table top；
First contact hole in source area arrival the first noumenon area is extended through from the upper surface of epitaxial layer, the first contact hole is conductive
Material is filled；
The second contact hole of the second body zone is extended to from the upper surface of epitaxial layer, the second contact hole is filled by conductive material；
Wherein correspondence is bigger than depth value, the width value of the second contact hole respectively for the depth value of the first contact hole, width value；It is described
First table top is active area, and second table top is active to terminal transition region.
12. groove power semiconductor device as claimed in claim 11, which is characterized in that the first groove filling is led
Electric material, the conductive material in first groove insulate with epitaxial layer and form trench-gate.
13. groove power semiconductor device as claimed in claim 12, which is characterized in that the second groove filling is led
Electric material, the conductive material in second groove insulate with epitaxial layer and form isolated groove.
14. groove power semiconductor device as claimed in claim 11, which is characterized in that the third depth and second
Depth has identical depth.
15. groove power semiconductor device as claimed in claim 14, which is characterized in that further include and be arranged on the first contact
The ontology conductive type doped region of the taller concentration in the first noumenon area described in the ratio in bottom hole portion.
16. groove power semiconductor device as claimed in claim 15, which is characterized in that further include and be arranged on the second contact
The ontology conductive type doped region of the taller concentration of the second body zone described in the ratio in bottom hole portion.
17. groove power semiconductor device as claimed in claim 11, which is characterized in that the third groove is around the
One and second groove.
18. groove power semiconductor device as claimed in claim 11, which is characterized in that the conduction of the first contact hole of filling
Material is electrically connected with filling the conductive material of the second contact hole.
19. groove power semiconductor device as claimed in claim 11, which is characterized in that the third trench fill is led
Electric material, the conductive material in third groove insulate with epitaxial layer.
20. groove power semiconductor device as claimed in claim 19, which is characterized in that further include and be arranged on third groove
Third contact hole in body zone at the top of the epitaxial layer in outside, wherein third contact hole fill conductive material and filling third ditch
The conductive material electrical connection of slot.
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| US10032728B2 (en) * | 2016-06-30 | 2018-07-24 | Alpha And Omega Semiconductor Incorporated | Trench MOSFET device and the preparation method thereof |
| CN107546303B (en) | 2017-08-25 | 2019-06-21 | 扬州乾照光电有限公司 | A kind of AlGaInP based light-emitting diode and its manufacturing method |
| US10679991B2 (en) * | 2018-10-12 | 2020-06-09 | Micron Technology, Inc. | Methods and apparatuses including a boundary of a well beneath an active area of a tap |
| CN110444591B (en) * | 2019-08-31 | 2021-04-20 | 电子科技大学 | Trench device with low on-resistance and method of manufacturing the same |
| CN110896053B (en) * | 2019-12-06 | 2022-04-29 | 绍兴中芯集成电路制造股份有限公司 | Shielded gate field effect transistor and method of forming the same |
| CN117461142A (en) * | 2021-12-13 | 2024-01-26 | 华为技术有限公司 | Trench FET device and method of manufacturing a trench FET device |
| CN116454022B (en) * | 2023-06-16 | 2023-08-25 | 合肥新晶集成电路有限公司 | Semiconductor device and method for manufacturing the same |
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| CN103247681A (en) * | 2012-02-02 | 2013-08-14 | 万国半导体股份有限公司 | nano mosfet with trench bottom oxide shielded and third dimensional p-body contact |
| CN103633068A (en) * | 2012-08-26 | 2014-03-12 | 万国半导体股份有限公司 | Flexible crss adjustment in a sgt mosfet to smooth waveforms and to avoid emi in dc-dc application |
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| CN103247681A (en) * | 2012-02-02 | 2013-08-14 | 万国半导体股份有限公司 | nano mosfet with trench bottom oxide shielded and third dimensional p-body contact |
| CN103633068A (en) * | 2012-08-26 | 2014-03-12 | 万国半导体股份有限公司 | Flexible crss adjustment in a sgt mosfet to smooth waveforms and to avoid emi in dc-dc application |
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Effective date of registration: 20200428 Address after: Ontario, Canada Patentee after: World semiconductor International Limited Partnership Address before: 475 oakmead Avenue, Sunnyvale, California 94085, USA Patentee before: Alpha and Omega Semiconductor Inc. |