CN103633068A - Flexible crss adjustment in a sgt mosfet to smooth waveforms and to avoid emi in dc-dc application - Google Patents
Flexible crss adjustment in a sgt mosfet to smooth waveforms and to avoid emi in dc-dc application Download PDFInfo
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- CN103633068A CN103633068A CN201310290017.0A CN201310290017A CN103633068A CN 103633068 A CN103633068 A CN 103633068A CN 201310290017 A CN201310290017 A CN 201310290017A CN 103633068 A CN103633068 A CN 103633068A
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Abstract
A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
Description
Technical field
The present invention relates generally to semiconductor power device.More precisely, the invention relates to new and improved preparation technology and device architecture with the power device of flexible Crss, so that smooth waveform, avoid the electromagnetic interference in shield grid groove (SGT) MOSFET of enhancement mode DC-to-DC device.
Background technology
Partial continuous (CIP) application case of three common applications co-pending that present application for patent is co-inventor: the application case that the application number of submitting on August 14th, 2009 is US12/583192; The application case of the US12/583191 submitting on August 14th, 2009 and the US13/016804 that submits on January 28th, 2011.The application's case is also another co-pending continuity application of co-inventor: partial continuous (CIP) application case of the US13/066947 submitting on April 28th, 2011.Application case US13/066947, for dividing an application, requires to be US7633119 and to have announced in another application case US11/356944(patent No. that on February 17th, 2006 submits) and the priority of the co-pending application case US12/653355 that submits on December 11st, 2009 of co-inventor.Hereby quote the content of following patent application case US11/356944, US12/653355, US12/583192, US12/583191, US13/016804 and US13/066947, with for referencial use.
The conventional art of the power device that designs and apply for the preparation of DC-to-DC, because the crest voltage of phase node is very low, therefore still face many difficulties, especially concerning the higher DC-to-DC device of efficiency, require the crest voltage of phase node all lower than 80% specified drain-source voltage (VDS), thereby avoid electromagnetic interference (EMI).These technical problems have produced restriction and negative effect to device performance conventionally.
In addition,, by the conventional art of gate leakage capacitance Cgd in shield grid (SGT) Structure Decreasing power semiconductor, other technologies limitation and a difficult problem have still been run into.Exactly, be arranged on the source electrode of channel bottom in traditional SGT device, the fringe region by semiconductor power device, is connected on source voltage.This has inevitably increased source electrode resistance.In addition, this connection needs many extra masks, has increased the cost of preparation.The invention of many patented power has proposed this structure.
Baliga has proposed a kind of DMOS structure cell in patent US5998833, as shown in Figure 1A.Source electrode is positioned at trench-gate below, to reduce gate leakage capacitance.The grid of DMOS structure cell is divided into two parts.Grid leak overlay region is eliminated the impact of electric capacity, thereby has reduced gate leakage capacitance.
In United States Patent (USP) 6690062, MOSFET device has as shown in Figure 1B been proposed, by prepare a bucking electrode in marginal zone, improve the switch motion of transistor arrangement.Bucking electrode at least surrounds one section of active unit cell arrays.Between edge gate structure and drain region, there is electric capacity.Bucking electrode in marginal zone has reduced the electric capacity between edge gate structure and drain region, thereby has reduced transistorized gate leakage capacitance C
gD.
In United States Patent (USP) 6891223, the people such as Krumrey have proposed a kind of transistor that contains transistor unit cell, and transistor unit cell is along the groove setting in Semiconductor substrate, and two or more electrode structures are arranged in groove.In addition, metallization structure is arranged on substrate surface top, as shown in Figure 1 C.Groove extends in transistorized non-active marginal zone.Electrical connection between electrode structure and corresponding metallization thereof, is based upon in marginal zone.
Yet the above-mentioned patent and the specification that comprise transistor arrangement, still run into a general difficult problem, be just arranged on the source electrode on channel bottom in traditional SGT device, the marginal zone by semiconductor power device, is connected on source voltage.Due to increasing to the demand of HF switch power device, so the effective scheme of above-mentioned technical barrier in the urgent need to address and limitation.For MOSFET and IGBT constant power transistor, new device structure and preparation technology must reduce the grid of these switch power devices and the speed limit electric capacity between drain electrode.
In addition, must improve traditional structure by the bucking electrode of top grid part below is connected on source electrode, to meet the requirement of phase node to lower peak voltages, and the electromagnetic interference problem in power device while avoiding DC-to-DC application.
Therefore, in power semiconductor design and preparation field, be extremely necessary to propose a kind of new preparation process and device architecture of power device, thereby solve above-mentioned difficulties and limitation.
Summary of the invention
Therefore, one aspect of the present invention is, proposed a kind of novel, improvement with shield grid groove (Shield gate trench, abbreviation SGT) semiconductor power device of structure, the electrode of part bottom shield is connected to source metal, and some bottom shield electrode is connected to gate metal, to meet the lower peak voltages requirement of phase node, and the electromagnetic interference problem while avoiding DC-to-DC application in power device, thereby solved an above-mentioned difficult problem.
Exactly, one aspect of the present invention is, proposed a kind of novel, improvement the semiconductor power device with shield grid groove (SGT) structure, the electrode of a part of bottom shield is connected to source metal, some bottom shield electrode is connected to gate metal.New structure is configured in low side MOSFET, improves Crss, and generating portion is used for the structure cell of break-through, thereby reaches the object that reduces phase node peak value ring.
Another aspect of the present invention is, proposed a kind of novel, improvement the semiconductor power device with shield grid groove (SGT) structure, the electrode of part bottom shield is connected to source metal, and some bottom shield electrode is connected to gate metal.New structure is configured in high-end MOSFET, improves Crss, makes the switching speed of high-end MOSFET slack-off, thereby reaches the object that reduces phase node peak value ring.
Another aspect of the present invention is, proposed a kind of novel, improvement the semiconductor power device with shield grid groove (SGT) structure, the electrode of part bottom shield is connected to source metal, some bottom shield electrode is connected to gate metal, by adjusting, be connected to the quantity of the bottom electrode on gate metal, can adjust flexibly Crss, thereby to dissimilar application, reach different design objects.
A preferred embodiment of the present invention has mainly proposed a kind of semiconductor power device that contains a plurality of power transistor structure cells, each power transistor structure cell has a channel grid, be arranged in gate trench, wherein channel grid comprises a shielding bottom electrode, be arranged on gate trench bottom, by in m-electrode dielectric layer, with the top grid electrode electric insulation that is arranged on gate trench top.At least one contains the transistor unit cell that shields bottom electrode, as source electrode-connection shielding bottom electrode, be electrically connected on the source metal of semiconductor power device, at least one contains the transistor unit cell that shields bottom electrode, as grid-connection shielding bottom electrode, be electrically connected on the gate metal of semiconductor power device.
In one embodiment of the invention, a kind of a plurality of power transistor structure cells semiconductor power device of (or being called transistor unit) that contains is disclosed, each power transistor structure cell has a channel grid, be arranged in gate trench, wherein said channel grid comprises a shielding bottom electrode, be arranged on the bottom of gate trench, by target insulating barrier, isolated with the top grid electrode that is arranged on gate trench top, wherein: at least one transistor unit cell contains shielding bottom electrode, as source electrode-connection (Source-connecting) shielding bottom electrode, be electrically connected to the source electrode of semiconductor power device, at least one transistor unit cell contains shielding bottom electrode, as grid-connection (Gate-connecting) shielding bottom electrode, be electrically connected to the gate metal of semiconductor power device.
Above-mentioned semiconductor power device, Semiconductor substrate also comprises an active area and a termination area (Termination region), at transistor unit cell described in described active area, has a source area, is arranged near channel grid; And described at least one, transistor unit cell forms a source electrode contact structure cell, comprise that a source electrode of opening connects groove in described source area, for described source electrode-connection shielding bottom electrode is electrically connected to and is arranged on the source metal that described source electrode connects groove top.
Above-mentioned semiconductor power device, described Semiconductor substrate comprises an active area and a termination area, described gate trench also comprises gate pad contact trench, be arranged on termination area, described gate trench also comprises a plurality of grid slideway grooves, gate trench from active area starts, and extends to the gate pad contact trench in termination area; Gate pad contact trench described at least one, as shielding bottom to gate pad contact trench (Shielding-bottom-to-gate-pad contact trench), by electric conducting material, filled, for grid described at least one being connected to shielding bottom electrode, is electrically connected to the gate metal that is arranged on described shielding bottom to gate pad contact trench top.
Above-mentioned semiconductor power device; also comprise: an insulating protective layer that is arranged on described semiconductor power device top; above connecting groove, described source area and described source electrode there are a plurality of source electrode openings; wherein electric conducting material is filled in described a plurality of source electrode openings, for source area is connected to shielding bottom electrode with source electrode, is electrically connected to described source metal.
Above-mentioned semiconductor power device; also comprise: an insulating protective layer that is arranged on described semiconductor power device top; above described gate pad contact trench, there are a plurality of gate openings; with described shielding bottom to gate pad contact trench in described termination area, for channel grid is connected with grid, shields bottom electrode and be electrically connected to described gate pad.
Above-mentioned semiconductor power device, the described gate pad contact trench that at least one is filled by electric conducting material, is only electrically connected on top grid electrode, with the shielding bottom electrode electric screen that is arranged on channel grid bottom.
Above-mentioned semiconductor power device; also comprise: a virtual groove; be arranged in the outer peripheral areas of termination area; by being arranged on the insulation protection layer open of described semiconductor power device top; wherein said virtual groove is to be filled by the metallic plug of electric conducting material top; electric conducting material is filled in virtual channel bottom; wherein the metallic plug in virtual groove has also contacted a drain metal of the insulating protective layer that is covered with periphery, termination area, as the tunnel end points (Channel stop) of semiconductor power device.
Above-mentioned semiconductor power device, described grid slideway groove also comprises shielding bottom electrode, is arranged on grid slideway channel bottom, by target insulating barrier, with top grid electrode electric insulation.
Above-mentioned semiconductor power device, there is the quantity that the grid that is electrically connected on gate metal connects the transistor unit cell of shielding bottom electrode, and there is the ratio of quantity that the source electrode being electrically connected on source electrode is connected the transistor unit cell that shields bottom electrode between 1% to 50%.
Above-mentioned semiconductor power device, has the quantity that the grid that is electrically connected on gate metal connects the transistor unit cell of shielding bottom electrode, is 25% with the ratio that has the source electrode being electrically connected on source electrode and be connected the quantity of the transistor unit cell that shields bottom electrode.
Above-mentioned semiconductor power device, wherein has the quantity that the source electrode that is electrically connected on source electrode connects the transistor unit cell of shielding bottom electrode, connects four times of transistor unit cell quantity of shielding bottom electrode for having the grid being electrically connected on gate metal.
Above-mentioned semiconductor power device, has the quantity that the grid that is electrically connected on gate metal connects the transistor unit cell of shielding bottom electrode, is 50% with the ratio that has the source electrode being electrically connected on source electrode and be connected the quantity of the transistor unit cell that shields bottom electrode.
Above-mentioned semiconductor power device, wherein has the quantity that the source electrode being electrically connected on source electrode connects the transistor unit cell of shielding bottom electrode, connects the twice of the transistor unit cell quantity of shielding bottom electrode for having the grid being electrically connected on gate metal.
In another embodiment of the invention, a kind of method for the preparation of semiconductor power device is also provided, this device comprises a source metal and a gate metal, divide and be else electrically connected to source electrode and the grid of semiconductor power device, it is characterized in that, the method comprises: in substrate, open a plurality of grooves, and fill described groove by conductive gate material; And utilize a mask, carry out timing etching, near each selected groove active transistor structure cell, carve described grid material last time, thereby retain the bottom of selected groove, leave the groove being covered by mask of still filling with grid conducting material; In described selected groove, by shield dielectric, cover bottom, form a bottom insulation electrode; By the part groove of still filling by conductive gate material, as source electrode contact trench, for connecting source metal, the residue groove of filling by conductive gate material, as gate contact groove, for connecting gate metal; And predefined first group of bottom shield electrode is electrically connected at least one source electrode contact trench, and predefined second group of bottom shield electrode is electrically connected at least one gate contact groove.
Said method, the step of preparing gate contact groove also comprises, prepares gate contact groove in termination area, away from active structure cell, for contacting the gate metal that covers top, termination area.
Said method, the step of preparing source electrode contact trench also comprises, near the active cell region active structure cell, prepares source electrode contact trench, for contacting the source metal that covers active cell region top.
Said method, also comprise: the described step that respectively first group of predefine and second group of bottom shield electrode of predefine is electrically connected to source electrode contact trench and gate contact groove, also comprises second group of bottom shield electrode of predefine is configured to 1% to 50% of first group of predefine.
Above-mentioned method, also comprise: prepare an insulating barrier, cover the end face of described semiconductor power device, above described groove remainder, open a plurality of source electrode contact openings, form source connection, directly contact the grid material in described groove remainder, to be electrically connected to described bottom shield electrode.
Said method, also comprise: prepare an insulating barrier, for covering the end face of described semiconductor power device, and open at least one gate contact opening, for the gate pad providing is electrically connected to the grid material described in the channel grid described in selected part groove.
Said method, also comprise: open a plurality of grooves and also comprise and open a plurality of grid slideway grooves (Gate runner trenches), gate trench near active area active transistor structure cell starts, and extends to the grid-contact trench (Gate-contacting trenches) being arranged in termination area; And second group of bottom shield electrode of predefine is electrically connected to grid-contact trench, also comprises by conductive gate material and fill grid slideway groove, to by grid slideway groove, second group of bottom shield electrode of predefine is electrically connected to grid-contact trench.
Read following describe in detail and with reference to after accompanying drawing, these and other characteristics and advantages of the present invention, for a person skilled in the art, undoubtedly will be apparent.
Accompanying drawing explanation
Figure 1A to 1C represents the profile of the grooved MOSFET device described in this patent, to reduce gate leakage capacitance.
Fig. 2 A-2C represents the profile with the part grooved MOSFET device of improvement layout structure of the present invention.
Fig. 3 A and 3B represent that the shielding bottom electrode of different proportion in SGT MOSFET structure cell is electrically connected to two vertical views on grid and source electrode.
Fig. 3 C represents that top grid electrode, by gate connection, is electrically connected to the vertical view on grid slideway metal.
Fig. 4 A to 4P represents preparation technology's profile of grooved MOSFET device as shown in Figure 2 A.
Fig. 5 represents a kind of circuit diagram of synchronous step-down converter.
Embodiment
Fig. 2 A represents the profile of shield grid groove (SGT) the MOSFET power device 300 of a part of novel layouts of the present invention.As shown in Figure 2 A, along the A-A' of Fig. 3 A and the profile of B-B' line, SGT MOSFET300 is positioned on silicon substrate, comprises a light dope epitaxial loayer 110 on heavily doped layer 105.The active area of this structure comprises the active gate trenchs such as 115, and wherein gate electrode 150 is formed on groove top, and bottom shield electrode 130 is formed on channel bottom, by dielectric layer 120, with gate electrode 150 insulation.SGT MOSFET device 300 also comprises source electrode polysilicon trench 115-S, is formed near termination area, active area.SGT MOSFET device 300 also comprises virtual polysilicon trench (Dummy poly trench) 115-D, is formed in termination area.In active area, source metal 190-S is for example, by dielectric layer (oxide 180), with gate electrode 150 insulation.Source metal 190-S passes through for example tungsten plug of metal joint 145-S(), be electrically connected to 170He Zhe tagma, source area 160, tungsten plug has been filled source-body contact openings, from source metal, through source area 170, extends in this tagma 160.The end face of gate electrode 150 in source area 170 end face with lower recess.The source electrode polysilicon trench 115-S being formed in termination area comprises a source electrode 130-S', by metallic conductor 145-S'(tungsten plug for example), be electrically connected to source metal 190-S upper, tungsten plug has been filled the contact openings in oxide 180.The source electrode contact openings of opening by oxide layer 180, injects contact doping district 165, to strengthen tungsten plug 145-S, 145-S' electrically contacting to 170He Zhe tagma, source area 160.Virtual groove 115-D comprises a virtual polysilicon 130-D, by metallic conductor 145-D', is electrically connected to drain metal 190-D.Metallic conductor 145-D is also connected to drain metal 190-D.Virtual polysilicon trench 115-D and metallic conductor 145-D are as the tunnel end points of device 300, as shown in Figure 3 C.
Fig. 2 B is illustrated in termination area the profile along the part on the third direction of shield grid groove (SGT) MOSFET power device 300.As shown in Figure 2 B, along in the profile of the D-D' line of Fig. 3 C, grid slideway metal 190-G is electrically connected to the gate electrode 150 in the trench-gate 115 of expansion, or by grid conductor 145-G, along the third dimension degree in termination area, is electrically connected to grid slideway groove.
In the present invention, the shielding bottom electrode of most active groove 115 is all electrically connected to source metal 190-S, 130-S for example, and other shielding bottom electrode (for example 130-G) is electrically connected to gate metal 190-G.As shown in Figure 2 A, by being formed on source electrode 130-S' and the metallic conductor 145-S' in source electrode polysilicon trench 115-S, shielding bottom electrode 130-S is electrically connected to source metal 190-S.As shown in Figure 2 C,, along the profile of the C-C' line of Fig. 3 A, by the metallic conductor 145-G' of third dimension degree in gate electrode 130-G' and termination area, shielding bottom electrode 130-G is electrically connected to gate metal 190-G.Partly shielding effect bottom electrode is shorted to gate metal, and more gate-to-drain is overlapping, can increase the reverse transfer capacitance Crss of SGT MOSFET device 300.The structure cell quantity by adjusting with the shielding bottom electrode being connected on gate metal, Crss that can flexible SGT MOSFET device 300, thus no matter how layout changes, and the RdsA of device can be not influenced.
Fig. 3 A and 3B represent the vertical view of two examples of two kinds of different layout structures.As shown in Figure 3A, 50% structure cell has shielding bottom electrode, is configured to 130-G, is connected to gate metal 190-G, and remaining shielding bottom electrode is 130-S, is connected to source metal 190-S.Specifically, for each, there is the structure cell that shielding bottom electrode 130-S is shorted to source metal 190-S, have a structure cell with shielding bottom electrode 130-G to be shorted to gate metal 190-G.
Fig. 3 B represents that 25% the structure cell with shielding bottom electrode is configured to 130-G, is connected to gate metal 190-G, and remaining shielding bottom electrode 130-S is connected to source metal 190-S.Specifically, for having, shield three structure cells that bottom electrode 130-S is shorted to source metal 190-S, all can have a structure cell with shielding bottom electrode 130-G to be shorted to gate metal 190-G.The structure cell quantity that can flexible bottom electrode be shorted to source metal, is shorted to the structure cell quantitative proportion of gate metal with bottom electrode, and preferably from 1% to 50%.In device layout of the present invention, partly shielding effect bottom electrode is connected to grid potential, and the standard SGT device being all connected in source potential with all shielding bottom electrode is compared, and has produced more accumulation area, thereby has reduced Rdson.
The preparation technology of MOSFET device 300 is as shown in Fig. 4 A-4P.In Fig. 4 A, for example on silicon substrate, first use hard mask 812(
thick oxide layer), silicon substrate comprises that a lightly doped epitaxial loayer 810 is above heavy doping epitaxial loayer 805.Above hard mask 812, use a trench mask (not expressing in figure), to prepare oxide hardmask 812, then remove.Referring to Fig. 4 B, by trench etch process, in epitaxial loayer 810, open a plurality of grooves 815.Electrode and the desired clear depth of target oxide thickness have determined gash depth, and gash depth is about 1.5 microns to 6.0 microns.In Fig. 4 C, remove hard mask 812, sacrifice oxidation, then, by oxide etching, remove surface impaired on trench wall, make smooth-sided.Then, by bottom, be oxidized growth bottom oxidization layer 817.According to the device optimization requirement of low Rds and high-breakdown-voltage, the growth thickness of oxide layer 817 is about
extremely
thicker oxide layer 817 can reduce silicon surface electric field, allows to use heavier doping, and for identical specified puncturing, the Rds of generation is less.
In Fig. 4 D, source electrode polysilicon layer 830 is deposited in groove 815.In Fig. 4 E, carry out comprehensive polysilicon and return quarter, to return, carve source electrode polysilicon layer 830.Return and carve source electrode polysilicon layer 830 without mask, until its end face has just arrived silicon substrate end face below.In Fig. 4 F, utilize the second mask (being source electrode polysilicon mask 832), cover the termination area of silicon substrate.Then, return and carve source electrode polysilicon layer 830, remove the top in groove, for gate electrode.Utilize the carving technology that returns regularly, source electrode polysilicon 830 is etched into target depth, for example, source electrode polysilicon is carved into following about 0.6 micron to 1.8 microns of surface of silicon for 830 times.Can preserve source electrode polysilicon mask 832, so that further oxide returns quarter (wet etching erosion), be conducive to the high density deposition (HDP) in subsequent technique.
Utilize wet etching erosion, peel off source electrode polysilicon mask 832.In Fig. 4 G, by HDP, deposit and chemico-mechanical polishing (CMP), preparation HDP oxide layer 834, for example thickness is
left and right, on the top of groove 815 and the end face of silicon substrate.In Fig. 4 H, utilize P-mask film covering 836 to cover the termination area of silicon substrate.Then, by timing, return carving technology, the HDP layer 834 of trenched side-wall and thick-oxide are returned and be carved into target depth, for example, source electrode polysilicon is carved into following 1.0 microns of surface of silicon for 830 times, as shown in Fig. 4 I.
In Fig. 4 J, peel off P-mask film covering 836.For example prepare a very thin grid oxic horizon 837(
extremely
left and right), the end face of silicon substrate in the top of covering groove wall and active area.Thin-oxide in gate trench sidewalls is conducive to reduce threshold voltage of the grid.In Fig. 4 K, in gate trench, deposit and return and carve gate polysilicon layer 850, form gate electrode.Simple returning carved this gate polysilicon layer 850 without mask, until its surface at silicon substrate end face with lower recess.
In Fig. 4 L, by bulk doped, inject, at silicon substrate top, prepare a plurality of bulk doped district 860.For example, be about under the energy energy level of 60keV to 300keV, implantation dosage is about 5e12cm
-2to 2e13cm
-2boron alloy.By bulk diffusion, form this tagma 860.Ontology-driven makes alloy be diffused into desired depth, more shallow than upper gate electrode.
Then as shown in Fig. 4 M, utilize the 4th mask (being that photoresist is as source mask 838), carry out source dopant injection, prepare a plurality of source doping region 870.Before injecting source electrode, carry out local oxidation thing attenuate.In Fig. 4 N, remove photoresist layer 838, then utilize high temperature, diffuse source polar region 870.After source drive, above silicon substrate, deposit LTO/BPSG layer 880.Then, carry out BPSG flow process.
In Fig. 4 O, utilize contact mask (not expressing in figure), through LTO/BPSG layer 880, open contact openings 842, below the bottom surface of contact trench, inject contact doping district 844, remove contact mask after (in figure, not expressing), deposit a metal level.In Fig. 4 P, utilize metal mask (not expressing in figure), metal level made in gate metal 890-G(figure and do not expressed), the pattern of source metal 890-S and drain metal 890-D.Carry out plasma and strengthen oxide and nitride deposition, preparation oxide layer and nitration case, above silicon substrate as passivation layer (not expressing in figure), cover gate metal 890-G, source metal 890-S and drain metal 890-D.Then, utilize unsharp mask, etching passivation layer, makes not express this process in gate metal 890-G, source metal 890-S and drain metal 890-D(figure) electric insulation.Attenuate wafer, deposition back-metal, forms drain electrode (not expressing this process in figure).
Boost or the high-end MOSFET and/or low side MOSFET of step-down controller in, the new layout of configuration SGT MOSFET device, some shielding bottom electrodes are connected on grid potential, to reduce the crest voltage of phase node.Fig. 5 represents a kind of circuit diagram of synchronous buck converter 10, comprises a high-end switch 11 and a low-end switch 13, and they are all as MOSFET device.High-end switch 11 is connected to voltage source V
ccand between inductor 15.Low-end switch 13 is connected between inductor 15 and earth terminal.By high-end switch 11 and low-end switch 13 added voltage on gate electrode separately, drive their switch performance.Transducer 10 also comprises the electric capacity 17 being connected between inductor 15 and earth terminal.High-end MOSFET is inductor and low side MOSFET charging, replaces traditional step-down modulator diode, for inductive current provides low-loss backflow.
Due in low side MOSFET, configured the new layout of SGT MOSFET device, some shielding bottom electrodes are connected on grid potential, therefore obtained higher Crss, cause when VGS spike is during higher than the threshold voltage in local structure cell (VTH), part structure cell generation break-through, makes waveform level and smooth, produces lower phase node peak value ring.In addition, when high-end MOSFET opens, can there is higher grid spike in very fast switching speed in local structure cell.Due in high-end MOSFET, configured the new layout of SGT MOSFET device, some shielding bottom electrodes are connected on grid potential, therefore obtained higher Crss, cause when high-end switch mosfet is slower, make waveform level and smooth, produce lower phase node peak value ring.In addition, DC-to-DC converter needs lower conduction resistance, and can not damage the performance of non-clamp inductance switch (UIS), or increases switching loss.SGT MOSFET device of the present invention is this solution that contributes to reduce the protected type grid of electromagnetic interference.
Although the present invention has described existing preferred embodiment in detail, should understand these explanations should be as limitation of the present invention.Those skilled in the art reads after above-mentioned detailed description, and various changes and modifications undoubtedly will be apparent.For example, except polysilicon, can also utilize other electric conducting material filling grooves.Therefore, should think that appending claims contained whole variations and the correction in true intention of the present invention and scope.
Claims (20)
1. a semiconductor power device that contains a plurality of power transistor structure cells, each power transistor structure cell has a channel grid, be arranged in gate trench, wherein said channel grid comprises a shielding bottom electrode, be arranged on the bottom of gate trench, by target insulating barrier, isolated with the top grid electrode that is arranged on gate trench top, it is characterized in that, wherein:
At least one transistor unit cell contains shielding bottom electrode, as source electrode-connection shielding bottom electrode, be electrically connected to the source electrode of semiconductor power device, at least one transistor unit cell contains shielding bottom electrode, as grid-connection shielding bottom electrode, be electrically connected to the gate metal of semiconductor power device.
2. semiconductor power device claimed in claim 1, is characterized in that, Semiconductor substrate also comprises an active area and a termination area, at the transistor unit cell described in described active area, has a source area, is arranged near channel grid; And
Transistor unit cell described at least one forms a source electrode contact structure cell, comprise that a source electrode of opening connects groove in described source area, for described source electrode-connection shielding bottom electrode is electrically connected to and is arranged on the source metal that described source electrode connects groove top.
3. semiconductor power device claimed in claim 1, it is characterized in that, described Semiconductor substrate comprises an active area and a termination area, described gate trench also comprises gate pad contact trench, be arranged on termination area, described gate trench also comprises a plurality of grid slideway grooves, and the gate trench from active area starts, and extends to the gate pad contact trench in termination area;
Gate pad contact trench described at least one, as shielding bottom to gate pad contact trench, by electric conducting material, filled, for the grid described at least one being connected to shielding bottom electrode, be electrically connected to the gate metal that is arranged on described shielding bottom to gate pad contact trench top.
4. semiconductor power device claimed in claim 2; it is characterized in that; also comprise: an insulating protective layer that is arranged on described semiconductor power device top; above connecting groove, described source area and described source electrode there are a plurality of source electrode openings; wherein electric conducting material is filled in described a plurality of source electrode openings, for source area is connected to shielding bottom electrode with source electrode, is electrically connected to described source metal.
5. semiconductor power device claimed in claim 3; it is characterized in that; also comprise: an insulating protective layer that is arranged on described semiconductor power device top; above described gate pad contact trench, there are a plurality of gate openings; with described shielding bottom to gate pad contact trench in described termination area, for channel grid is connected to the gate pad of shielding bottom electrode described in being electrically connected to grid.
6. semiconductor power device claimed in claim 3, is characterized in that, the described gate pad contact trench that at least one is filled by electric conducting material, is only electrically connected on top grid electrode, with the shielding bottom electrode electric screen that is arranged on channel grid bottom.
7. semiconductor power device claimed in claim 3; it is characterized in that; also comprise: a virtual groove; be arranged in the outer peripheral areas of termination area; by being arranged on the insulation protection layer open of described semiconductor power device top; wherein said virtual groove is to be filled by the metallic plug of electric conducting material top; electric conducting material is filled in virtual channel bottom; wherein the metallic plug in virtual groove has also contacted a drain metal of the insulating protective layer that is covered with periphery, termination area, as the tunnel end points of semiconductor power device.
8. semiconductor power device claimed in claim 3, is characterized in that, described grid slideway groove also comprises shielding bottom electrode, is arranged on grid slideway channel bottom, by target insulating barrier, with top grid electrode electric insulation.
9. semiconductor power device claimed in claim 1, it is characterized in that, there is the quantity that the grid that is electrically connected on gate metal connects the transistor unit cell of shielding bottom electrode, and there is the ratio of quantity that the source electrode being electrically connected on source electrode is connected the transistor unit cell that shields bottom electrode between 1% to 50%.
10. semiconductor power device claimed in claim 9, it is characterized in that, having the quantity that the grid that is electrically connected on gate metal connects the transistor unit cell of shielding bottom electrode, is 25% with the ratio that has the source electrode being electrically connected on source electrode and be connected the quantity of the transistor unit cell that shields bottom electrode.
11. semiconductor power devices claimed in claim 10, it is characterized in that, there is the quantity that the source electrode that is electrically connected on source electrode connects the transistor unit cell of shielding bottom electrode, for thering is the grid being electrically connected on gate metal, connect four times of transistor unit cell quantity of shielding bottom electrode.
12. semiconductor power devices claimed in claim 9, it is characterized in that, having the quantity that the grid that is electrically connected on gate metal connects the transistor unit cell of shielding bottom electrode, is 50% with the ratio that has the source electrode being electrically connected on source electrode and be connected the quantity of the transistor unit cell that shields bottom electrode.
Semiconductor power device described in 13. claims 12, it is characterized in that, there is the quantity that the source electrode being electrically connected on source electrode connects the transistor unit cell of shielding bottom electrode, for thering is the grid being electrically connected on gate metal, connect the twice of the transistor unit cell quantity of shielding bottom electrode.
14. 1 kinds of methods for the preparation of semiconductor power device, this device comprises a source metal and a gate metal, divides and is else electrically connected to source electrode and the grid of semiconductor power device, it is characterized in that, the method comprises:
In substrate, open a plurality of grooves, and fill described groove by conductive gate material; And
Utilize a mask, carry out timing etching, near each selected groove active transistor structure cell, carve described grid material last time, thereby retain the bottom of selected groove, leave the groove being covered by mask of still filling with grid conducting material;
In described selected groove, by shield dielectric, cover bottom, form a bottom insulation electrode;
By the part groove of still filling by conductive gate material, as source electrode contact trench, for connecting source metal, the residue groove of filling by conductive gate material, as gate contact groove, for connecting gate metal; And
Predefined first group of bottom shield electrode is electrically connected at least one source electrode contact trench, and predefined second group of bottom shield electrode is electrically connected at least one gate contact groove.
Method described in 15. claims 14, is characterized in that, the step of preparing gate contact groove also comprises, prepares gate contact groove in termination area, away from active structure cell, for contacting the gate metal that covers top, termination area.
Method described in 16. claims 14, is characterized in that, the step of preparing source electrode contact trench also comprises, near the active cell region active structure cell, prepares source electrode contact trench, for contacting the source metal that covers active cell region top.
Method described in 17. claims 14, it is characterized in that, also comprise: the described step that respectively first group of predefine and second group of bottom shield electrode of predefine is electrically connected to source electrode contact trench and gate contact groove, also comprises second group of bottom shield electrode of predefine is configured to 1% to 50% of first group of predefine.
Method described in 18. claims 14, it is characterized in that, also comprise: prepare an insulating barrier, cover the end face of described semiconductor power device, above described groove remainder, open a plurality of source electrode contact openings, form source connection, directly contact the grid material in described groove remainder, to be electrically connected to described bottom shield electrode.
Method described in 19. claims 14, it is characterized in that, also comprise: prepare an insulating barrier, for covering the end face of described semiconductor power device, and open at least one gate contact opening, for the gate pad providing is electrically connected to the grid material described in the channel grid described in selected part groove.
Method described in 20. claims 14, it is characterized in that, also comprise: open a plurality of grooves and also comprise and open a plurality of grid slideway grooves, the gate trench near active area active transistor structure cell starts, and extends to the grid-contact trench being arranged in termination area; And
Second group of bottom shield electrode of predefine is electrically connected to grid-contact trench, also comprises by conductive gate material and fill grid slideway groove, to by grid slideway groove, second group of bottom shield electrode of predefine is electrically connected to grid-contact trench.
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| US13/539,330 | 2012-08-26 | ||
| US13/539,330 US8692322B2 (en) | 2006-02-17 | 2012-08-26 | Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application |
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| TW201409652A (en) | 2014-03-01 |
| TWI529900B (en) | 2016-04-11 |
| CN103633068B (en) | 2016-08-10 |
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