CN104465781A - Groove type double-gate MOS and technological method - Google Patents

Groove type double-gate MOS and technological method Download PDF

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Publication number
CN104465781A
CN104465781A CN201410852324.8A CN201410852324A CN104465781A CN 104465781 A CN104465781 A CN 104465781A CN 201410852324 A CN201410852324 A CN 201410852324A CN 104465781 A CN104465781 A CN 104465781A
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groove
polysilicon
silicon
layer
oxide layer
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陈晨
周颖
陈正嵘
陈菊英
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a groove type double-gate MOS. A body zone is arranged in a silicon substrate of the groove type double-gate MOS, source grooves are located in the body zone, the bottoms of the source grooves are located in the substrate, and the grooves are filled with polycrystalline silicon; the polycrystalline silicon is slightly lower than the surface of the silicon substrate, and heat oxidation layers are arranged on the polycrystalline silicon to enable the grooves to be filled; boron-phosphorosilicate glass is arranged on the surface of the substrate; Schottky grooves are further formed in the silicon substrate and filled with polycrystalline silicon, and the polycrystalline silicon is isolated from the grooves through oxidation layers; isolating layers are further arranged between the polycrystalline silicon in the source grooves and the source grooves for partitioning, and the isolating layers are combined sandwich structures of first silicon oxide layers, silicon nitride and second silicon oxide layers; The source grooves are not filled with the boron-phosphorosilicate glass, and the Schottky grooves are filled with the polycrystalline silicon. The invention further discloses a technological method of the groove type double-gate MOS. By means of the method, the morphology of a Schottky zone is improved, the deep contact hole technology is avoided, bowl-opening interfaces are effectively avoided, the etching accuracy is more easily controlled accordingly, and cost is saved.

Description

Groove type double-layer grid MOS and process
Technical field
The present invention relates to integrated circuit (IC) design and manufacture field, refer to a kind of groove type double-layer grid MOS especially, the invention still further relates to the process of described groove type double-layer grid MOS.
Background technology
Groove type double-layer grid MOS, as a kind of power device, have puncture voltage high, conducting resistance is low, the feature that switching speed is fast.Figure 1 shows that a kind of source electrode groove structure schematic diagram of common groove-type double-layer grid MOS device, its source electrode groove middle and lower part is filled with polysilicon, silica rete in interval between polysilicon and groove, above polysilicon, there is thermal oxide layer, remaining space in full groove is filled again, dark contact hole break-through boron-phosphorosilicate glass and thermal oxide layer and polysilicon contact with boron-phosphorosilicate glass.About being characterized in that the polysilicon of filling in source electrode groove only accounts for the half in trench interiors space, make source contact openings need to do the polysilicon contact that more deeply could fill with lower trench.Fig. 2 is gate trench schematic diagram, and Fig. 3 is the groove of schottky region, similar with source electrode groove, and its trench interiors is filled with polysilicon, and between polysilicon and groove, there is oxide layer at interval.Have thermal oxide layer above polysilicon, about the polysilicon of filling in groove only accounts for the half in trench interiors space, its complementary space is filled with dielectric layer.
The defect of this structure is: as shown in Figure 4, because schottky region is less, cannot pass through EPD (etching terminal monitoring) and control etching depth, what current technique generally adopted is that etch period controls, control precision is not high, causes etching the depth uniformity formed bad.In addition, because the groove of schottky region is comparatively dark, after inter-level dielectric deposit, the drop on surface, groove place is large, and due to the etch rate of the different film quality of inter-level dielectric inconsistent, cause etching rear surface pattern to be bowl-type, contact hole region interface is more coarse, affects the interface quality of titanium/titanium nitride.
Above-mentioned defect combines and causes described groove type double-layer grid MOS may form more fragile Dian Huo district at the edge of schottky region, and the puncture voltage of device is reduced.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of groove type double-layer grid MOS structure.
The technical problem that the present invention also will solve is the manufacture method providing described groove type double-layer grid MOS structure, improves the pattern of Schottky, improves the breakdown voltage property of device.
For solving the problem, groove type double-layer grid MOS of the present invention, has tagma in its silicon substrate, and source electrode groove is arranged in tagma and bottom is positioned at substrate, fills polysilicon in groove; Polysilicon, a little less than surface of silicon, has thermal oxide layer and fills up groove above polysilicon; Substrate surface is boron-phosphorosilicate glass; Also have schottky trench in described silicon substrate, described schottky trench fills polysilicon, and isolates with oxide layer between polysilicon and groove;
Polysilicon in described source electrode groove and between source electrode groove also between be separated with separator, described separator is the compound sandwich structure of the first silicon oxide layer, silicon nitride and the second silicon oxide layer; Described boron-phosphorosilicate glass is not packed into source electrode groove; Fill completely with polysilicon in described schottky trench.
Described separator, wherein the thickness of the first silicon oxide layer is the thickness of silicon nitride is the thickness of the second silicon oxide layer is
For solving the problem, the process of groove type double-layer grid MOS of the present invention, comprises following steps:
The first step, surface of silicon deposited oxide layer and atmospheric pressure oxidation layer, lithographic definition etching forms groove;
Second step, deposit first silicon oxide layer, silicon nitride layer and the second silicon oxide layer in groove;
3rd step, deposit first polysilicon in groove also returns quarter, and utilizes mask plate to protect the first polysilicon connecting hole region, carries out back carving to other regions;
4th step, the deposit of groove internal heating oxidation layer, and manufacturing gate oxide layers;
5th step, the deposit of the second polysilicon is also returned and is carved;
6th step, injects and forms P type tagma, and carry out high-temperature hot propelling;
7th step, source electrode wet etching also carries out ion implantation under photoresist definition;
8th step, removes photoresist, pick after deposit inter-level dielectric into;
9th step, forms boron-phosphorosilicate glass;
Tenth step, contact hole etching, boron-phosphorosilicate glass etching and silicon substrate etching;
11 step, lithographic definition is carried out etching to boron-phosphorosilicate glass and is formed schottky junctions contact hole;
12 step, deposit titanium/titanium nitride, deposition tungsten also returns quarter, deposited metal.
Further, in the described first step, the thickness of deposited oxide layer is the thickness of atmospheric pressure oxidation layer is
Further, in described second step, the thickness of the first silicon oxide layer is the thickness of silicon nitride layer is the thickness of the second silicon oxide layer is
Further, described 3rd step, the gross thickness of the first polysilicon deposition is
Further, described 4th step, the thickness of thermal oxide layer deposit is
Further, described 6th step, P type tagma is carried out 1150 DEG C and is picked into 30 minutes.
Further, described 7th step, source electrode wet etching is to retaining oxide layer
Further, described 9th step, the thickness of deposit boron-phosphorosilicate glass is
Groove type double-layer grid MOS of the present invention, the separator of its source electrode groove have employed the sandwich composite construction of silicon oxide/silicon nitride/silicon oxide, inner polysilicon of filling is more simultaneously, make the depth shallower of source contact openings, reduce the difficulty of etching groove, equally, the polysilicon of filling in schottky trench is also more closer to groove top.
Accompanying drawing explanation
Fig. 1 is existing groove type MOS source electrode groove structure schematic diagram.
Fig. 2 is existing groove type MOS gate trench structural representation.
Fig. 3 is existing groove type MOS grid schottky trench structural representation.
Fig. 4 is existing groove type MOS planar structure schematic diagram.
Fig. 5 ~ 11 are present invention process step schematic diagrames.
Figure 12 is present invention process flow chart.
Description of reference numerals
1 is MOSFET region, and 2 is grids, and 3 is schottky region, 4 is substrates, and 5 is (first) silicon oxide layers, and 6 is polysilicons, 7 is thermal oxide layers, and 8 is P type tagmas, and 9 is contact holes, 10 is inter-level dielectrics, 11 is boron-phosphorosilicate glasss, and 12 is silicon nitrides, and 13 is second silicon oxide layers, 14 is polysilicons, and 15 is photoresists.
Embodiment
Groove type double-layer grid MOS of the present invention, its source electrode groove as shown in Figure 10, has tagma 8 in silicon substrate 4, source electrode groove is arranged in tagma 8 and bottom is positioned at substrate 4, fills polysilicon 6 in groove; Polysilicon 6, a little less than silicon substrate 4 surface, has thermal oxide layer 7 and fills up groove above polysilicon 6; Substrate surface is inter-level dielectric 10 and boron-phosphorosilicate glass 11; Also have schottky trench in described silicon substrate 4, as shown in figure 11, described schottky trench fills polysilicon, and isolates with oxide layer between polysilicon and groove.
Polysilicon 6 in described source electrode groove and between source electrode groove also between be separated with separator, described separator is the compound sandwich structure of the first silicon oxide layer 5, silicon nitride 12 and the second silicon oxide layer 13, and wherein the thickness of the first silicon oxide layer is the thickness of silicon nitride is the thickness of the second silicon oxide layer is described boron-phosphorosilicate glass is not packed into source electrode groove; The present embodiment selects the first silicon oxide layer thickness silicon nitride thickness silicon dioxide layer thickness fill completely with polysilicon in described schottky trench.
The process of groove type double-layer grid MOS of the present invention, comprises following steps:
The first step, surface of silicon deposited oxide layer and atmospheric pressure oxidation layer, the thickness of deposited oxide layer is as deposit the thickness of atmospheric pressure oxidation layer is as deposit lithographic definition etching forms groove.As shown in Figure 5.
Second step, deposit first silicon oxide layer, silicon nitride layer and the second silicon oxide layer in groove; The thickness of the first silicon oxide layer is the thickness of silicon nitride layer is the thickness of the second silicon oxide layer is
3rd step, depositing polysilicon in groove also returns quarter, polysilicon deposition 12K, and utilizes mask plate to protect the first polysilicon contact bore region, carries out back carving, as shown in Figure 6 to other regions.
4th step, the deposit of groove internal heating oxidation layer 7, the thickness of thermal oxide layer 7 deposit is and manufacturing gate oxide layers; As shown in Figure 7.
5th step, the deposit of the second polysilicon is also returned and is carved, and forms polysilicon gate.
6th step, injects and forms P type tagma 8, and carries out 1150 DEG C of high-temperature hot propellings picked into 30 minutes.
7th step, source electrode wet etching also carries out ion implantation under photoresist definition; Source electrode wet etching is to retaining oxide layer
8th step, removes photoresist, pick after deposit inter-level dielectric 10 into.
9th step, formed as the boron-phosphorosilicate glass 11 of thickness.
Tenth step, contact hole etching, boron-phosphorosilicate glass etching and silicon substrate etching, as shown in Figure 8.
11 step, lithographic definition is carried out etching to boron-phosphorosilicate glass and is formed schottky junctions contact hole, as shown in Figure 9.
12 step, deposit titanium/titanium nitride, deposition tungsten also returns quarter, deposited metal.As shown in Figures 10 and 11, Figure 10 is source electrode groove structure schematic diagram to the device of final formation, and Figure 11 is schottky trench structural representation (gate trench is still with reference to figure 2).
Pass through said method, the source polysilicon of schottky area shows to maintain an equal level in the oxidation rear surface finished between two-layer polysilicon and substrate, the rim of a bowl interface can be effectively avoided the formation of when Schottky etches, source polysilicon thickness after IPO oxidation in schottky region is consistent, ensure that the homogeneity of etching, the edge, schottky region formed does not have breakdown point, ensure that the stable breakdown voltage of device.Draw-out area above first polysilicon of source electrode changes staircase structural model into by sustained height, namely the height of the first polysilicon is not identical, higher needing the region of connecting hole, maintain an equal level with silicon face, avoid the etching that deep trench processes brings uneven, make etching groove severity control more accurate, cost-saving.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a groove type double-layer grid MOS, has tagma in its silicon substrate, and source electrode groove is arranged in tagma and bottom is positioned at substrate, fills polysilicon in groove; Polysilicon, a little less than surface of silicon, has thermal oxide layer and fills up groove above polysilicon; Substrate surface is boron-phosphorosilicate glass; Also have schottky trench in described silicon substrate, described schottky trench fills polysilicon, and isolates with oxide layer between polysilicon and groove; It is characterized in that: the polysilicon in described source electrode groove and between source electrode groove also between be separated with separator, described separator is the compound sandwich structure of the first silicon oxide layer, silicon nitride and the second silicon oxide layer; Described boron-phosphorosilicate glass is not packed into source electrode groove; Fill completely with polysilicon in described schottky trench.
2. as claimed in claim 1, it is characterized in that: described separator, wherein the thickness of the first silicon oxide layer is the thickness of silicon nitride is the thickness of the second silicon oxide layer is
3. prepare the process of groove type double-layer grid MOS as claimed in claim 1, it is characterized in that: comprise following steps:
The first step, surface of silicon deposited oxide layer and atmospheric pressure oxidation layer, lithographic definition etching forms groove;
Second step, deposit first silicon oxide layer, silicon nitride layer and the second silicon oxide layer in groove;
3rd step, deposit first polysilicon in groove also returns quarter, and utilizes mask plate to protect the first polysilicon connecting hole region, carries out back carving to other regions;
4th step, the deposit of groove internal heating oxidation layer, and manufacturing gate oxide layers;
5th step, the deposit of the second polysilicon is also returned and is carved;
6th step, injects and forms P type tagma, and carry out high-temperature hot propelling;
7th step, source electrode wet etching also carries out ion implantation under photoresist definition;
8th step, removes photoresist, pick after deposit inter-level dielectric into;
9th step, forms boron-phosphorosilicate glass;
Tenth step, contact hole etching, boron-phosphorosilicate glass etching and silicon substrate etching;
11 step, lithographic definition is carried out etching to boron-phosphorosilicate glass and is formed schottky junctions contact hole;
12 step, deposit titanium/titanium nitride, deposition tungsten also returns quarter, deposited metal.
4. the process of groove type double-layer grid MOS as claimed in claim 3, it is characterized in that: in the described first step, the thickness of deposited oxide layer is the thickness of atmospheric pressure oxidation layer is
5. the process of groove type double-layer grid MOS as claimed in claim 3, it is characterized in that: in described second step, the thickness of the first silicon oxide layer is the thickness of silicon nitride layer is the thickness of the second silicon oxide layer is
6. the process of groove type double-layer grid MOS as claimed in claim 3, is characterized in that: described 3rd step, the gross thickness of the first polysilicon deposition is
7. the process of groove type double-layer grid MOS as claimed in claim 3, is characterized in that: described 4th step, the thickness of thermal oxide layer deposit is
8. the process of groove type double-layer grid MOS as claimed in claim 3, it is characterized in that: described 6th step, P type tagma is carried out 1150 DEG C and is picked into 30 minutes.
9. the process of groove type double-layer grid MOS as claimed in claim 3, is characterized in that: described 7th step, source electrode wet etching is to retaining oxide layer
10. the process of groove type double-layer grid MOS as claimed in claim 3, is characterized in that: described 9th step, the thickness of deposit boron-phosphorosilicate glass is
CN201410852324.8A 2014-12-31 2014-12-31 Groove type double-gate MOS and technological method Pending CN104465781A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105845579A (en) * 2016-05-31 2016-08-10 上海华虹宏力半导体制造有限公司 Technological method for groove type double-gate MOS
CN107527802A (en) * 2017-08-15 2017-12-29 上海华虹宏力半导体制造有限公司 Groove type double-layer grid MOS film build methods
CN110491782A (en) * 2019-08-13 2019-11-22 上海华虹宏力半导体制造有限公司 The manufacturing method of groove type double-layer gate MOSFET
CN113130633A (en) * 2019-12-30 2021-07-16 华润微电子（重庆）有限公司 Groove type field effect transistor structure and preparation method thereof
CN113497122A (en) * 2020-03-18 2021-10-12 和舰芯片制造(苏州)股份有限公司 Split Gate structure, Power MOS device and manufacturing method
CN113517193A (en) * 2021-04-06 2021-10-19 江苏新顺微电子股份有限公司 Process method for improving performance of trench MOS structure Schottky diode
CN118366927A (en) * 2024-06-19 2024-07-19 杭州积海半导体有限公司 Preparation method of MOS transistor

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CN1090680A (en) * 1992-10-22 1994-08-10 株式会社东芝 Semiconductor device
CN102129999A (en) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 Method for producing groove type dual-layer grid MOS (Metal Oxide Semiconductor) structure
US20120018802A1 (en) * 2010-07-21 2012-01-26 Wei Liu Ultra-low-cost three mask layers trench MOSFET and method of manufacture
CN102856182A (en) * 2011-06-27 2013-01-02 半导体元件工业有限责任公司 Method of making an insulated gate semiconductor device and structure
CN103633068A (en) * 2012-08-26 2014-03-12 万国半导体股份有限公司 Flexible CRSS adjustment in SGT MOSFETs to smooth waveforms to avoid emi in dc-dc devices

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Publication number Priority date Publication date Assignee Title
CN1090680A (en) * 1992-10-22 1994-08-10 株式会社东芝 Semiconductor device
CN102129999A (en) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 Method for producing groove type dual-layer grid MOS (Metal Oxide Semiconductor) structure
US20120018802A1 (en) * 2010-07-21 2012-01-26 Wei Liu Ultra-low-cost three mask layers trench MOSFET and method of manufacture
CN102856182A (en) * 2011-06-27 2013-01-02 半导体元件工业有限责任公司 Method of making an insulated gate semiconductor device and structure
CN103633068A (en) * 2012-08-26 2014-03-12 万国半导体股份有限公司 Flexible CRSS adjustment in SGT MOSFETs to smooth waveforms to avoid emi in dc-dc devices

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105845579A (en) * 2016-05-31 2016-08-10 上海华虹宏力半导体制造有限公司 Technological method for groove type double-gate MOS
CN107527802A (en) * 2017-08-15 2017-12-29 上海华虹宏力半导体制造有限公司 Groove type double-layer grid MOS film build methods
CN110491782A (en) * 2019-08-13 2019-11-22 上海华虹宏力半导体制造有限公司 The manufacturing method of groove type double-layer gate MOSFET
CN110491782B (en) * 2019-08-13 2021-11-09 上海华虹宏力半导体制造有限公司 Manufacturing method of trench type double-layer gate MOSFET
CN113130633A (en) * 2019-12-30 2021-07-16 华润微电子（重庆）有限公司 Groove type field effect transistor structure and preparation method thereof
CN113130633B (en) * 2019-12-30 2022-11-22 华润微电子（重庆）有限公司 Groove type field effect transistor structure and preparation method thereof
CN113497122A (en) * 2020-03-18 2021-10-12 和舰芯片制造(苏州)股份有限公司 Split Gate structure, Power MOS device and manufacturing method
CN113517193A (en) * 2021-04-06 2021-10-19 江苏新顺微电子股份有限公司 Process method for improving performance of trench MOS structure Schottky diode
CN118366927A (en) * 2024-06-19 2024-07-19 杭州积海半导体有限公司 Preparation method of MOS transistor
CN118366927B (en) * 2024-06-19 2024-08-30 杭州积海半导体有限公司 Preparation method of MOS transistor

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Application publication date: 20150325