CN104916544B - A kind of manufacture method of plough groove type point grid power device - Google Patents
A kind of manufacture method of plough groove type point grid power device Download PDFInfo
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- CN104916544B CN104916544B CN201510182461.XA CN201510182461A CN104916544B CN 104916544 B CN104916544 B CN 104916544B CN 201510182461 A CN201510182461 A CN 201510182461A CN 104916544 B CN104916544 B CN 104916544B
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000009413 insulation Methods 0.000 claims abstract description 98
- 238000005530 etching Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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Abstract
The invention belongs to semiconductor power device manufacturing technology field, the manufacture method of more particularly to a kind of plough groove type point grid power device.A kind of manufacture method of plough groove type point grid power device of the present invention is during etching forms control grid recess, the lateral recesses positioned at the first insulation film bottom of control grid recess are formed by increasing lateral etching, and then directly can form control gate using the first insulation film as the conductive film of mask etching first after the first conductive film is deposited.Present invention process process simplification is reliable, easy to control, can greatly improve the yield rate of plough groove type point grid power device.The present invention is especially suitable for the manufacture of 25V 200V semiconductor power devices.
Description
Technical field
The invention belongs to semiconductor power device manufacturing technology field, specifically related to a kind of manufacture of semiconductor power device
Method, the manufacture method of more particularly to a kind of plough groove type point grid power device.
Background technology
With continuing to develop for microelectric technique, semiconductor power device is with the high and low loss of its input impedance, switching speed
Hurry up, without second breakdown, safety operation area is wide, dynamic property is good, easy coupled with preceding pole realizes that high current, conversion efficiency height etc. are excellent
Point, gradually substituting bipolar device turns into the main flow that current power device develops.Plough groove type point grid power device can reduce control
Parasitic capacitance between grid processed and drain region, reduces the dynamic power consumption of device and improves switching speed, it has also become semiconductor power device
The preferred structure of part.The manufacture method of existing typical plough groove type point grid power device, including：First in substrate epitaxial layer 100
Control grid recess is formed, the method for returning quarter again by first depositing conductive layer afterwards is controlling the both sides of grid recess to form control respectively
Grid 105, as shown in Figure 1a.Next, returning the carving method covering formation insulation film of control gate 105 again by first depositing insulation film
Side wall 201, then along insulation film side wall 201 edge etched substrate epitaxial layer to form a point grid recess, as shown in Figure 1 b.
The problem of manufacture method of existing typical plough groove type point grid power device is present be：The horizontal stroke of control gate 105 first
To narrower width, the etching difficulty of control gate contact hole is added；Secondly by returning the method carved formation insulation film side wall
During 201, the insulation film sidewall section positioned at the top of control gate 105 is easily etched, it is difficult to play protection control gate
105 effect, so that the manufacturing process of plough groove type point grid power device is difficult to control to, yield rate is low.
The content of the invention
The purpose of the present invention is the manufacture to overcome the deficiencies in the prior art to propose a kind of plough groove type point grid power device
Method, the present invention ensure that the stable manufacturing process of plough groove type point grid power device is reliable, easy to control, high yield rate.
According to a kind of manufacture method of plough groove type proposed by the present invention point grid power device, comprise the following specific steps that：
Step one：The substrate epitaxial of the first doping type is formed on the top in the drain region of the first doping type first
Layer, then forms the first insulation film on the top of substrate epitaxial layer, first of photoetching is carried out afterwards, finally to described the
One insulation film is performed etching, in the opening for being internally formed the first insulation film of first insulation film；
Step 2：Using first insulation film described in mask etching substrate epitaxial layer, the substrate epitaxial layer
Control grid recess is internally formed, the both sides edge of the control grid recess extends to the both sides of the opening of first insulation film
The first insulation film bottom, formed positioned at first insulation film bottom lateral recesses；
Step 3：The second insulation film is formed on the surface of the control grid recess, the first conductive film is then deposited, should
First conductive film fills up the control grid recess；
Step 4：Etching positioned at the first insulation film top first conductive film, and along described first
The edge of the opening of insulation film continues to etch first conductive film, and control is formed in the both sides of the control grid recess
Grid；Or first conductive film is etched first to the surface of substrate epitaxial layer, then the insulation of deposit first is thin again
Film simultaneously returns quarter to form the first insulation film side wall of the opening both sides for being located at first dielectric film, afterwards along described first
The edge of insulation film side wall etches first conductive film, and control gate is formed in the both sides of the control grid recess；
Step 5：Second insulation film of the control gate groove surfaces first to exposing is performed etching, and is then formed sediment
The 3rd insulation film of product simultaneously returns quarter, the 3rd insulation film side wall is formed on the side wall of the control gate exposed, afterwards along institute
The edge for stating the 3rd insulation film side wall etches the substrate epitaxial layer to form a point grid recess；
Step 6：The 4th insulation film is formed on the surface of described point of grid recess；
Step 7：The 3rd insulation film side wall is performed etching first, then in the control gate table exposed
Face forms the 5th insulation film；
Step 8：Deposit the second conductive film and return and carve, a point grid, the table of described point of grid are internally formed in described point of grid recess
Face is slightly below the surface of the substrate epitaxial layer；
Step 9：First insulation film is performed etching first, the ion note of second of doping type is then carried out
Enter, form channel region in substrate epitaxial layer, second photoetching and the ion implanting of the first doping type are carried out afterwards,
Source region is formed in substrate epitaxial layer；
Step 10：The 6th insulation film is deposited first and the figure that the 3rd road is lithographically formed contact hole is carried out, then to institute
State the 6th insulation film to perform etching to form contact hole, the ion implanting and deposited metal of second of doping type are carried out afterwards
Form Ohmic contact；
Step 11：The 4th road photoetching is carried out first, the metal level is then etched, to form source electrode, control respectively
Gate electrode and point gate electrode, are finally passivated deposit, pattern transfer and the etching of layer, so as to form plough groove type point grid power device
Part.
A kind of plough groove type of the present invention divides the further preferred scheme of the manufacture method of grid power device to be：
The material of first insulation film of the present invention is silica or silicon nitride.
The material of 3rd insulation film of the present invention is silicon nitride.
The material of second insulation film of the present invention, the 4th insulation film and the 5th insulation film is silica.
The material of 6th insulation film of the present invention is silica glass, boron-phosphorosilicate glass or phosphorosilicate glass.
Control gate of the present invention is polysilicon gate or metal gate.
The material of second conductive film of the present invention is polysilicon.
The first doping type adulterates for n-type described in each scheme of the present invention, and second of doping type is mixed for p-type
It is miscellaneous；Or the first described doping type adulterates for p-type, second of doping type adulterates for n-type.
Its remarkable advantage is the present invention compared with prior art：A kind of plough groove type proposed by the present invention point grid power device
Manufacture method during etching forms control grid recess, form by increasing lateral etching control grid recess and be located at
The lateral recesses part of first insulation film bottom, and then can be after the first conductive film is deposited directly with the first insulation film
For the conductive film of mask etching first to form control gate so that whole technical process, which simplifies, is reliable, easy to control, can carry significantly
The yield rate of high groove-type power device.A kind of manufacture method of plough groove type proposed by the present invention point grid power device is particularly suitable
In the manufacture of 25V-200V semiconductor power devices.
Brief description of the drawings
Fig. 1 a and Fig. 1 b divide the partial process flow of the manufacture method of grid power device for a kind of existing typical plough groove type
Schematic diagram.
Fig. 2 to Figure 11 is a kind of one embodiment of the manufacture method of plough groove type proposed by the present invention point grid power device
Process flow diagram.
Embodiment
The embodiment of the present invention is described in further detail below in conjunction with drawings and examples.
For convenience of description, layer and the thickness in region are exaggerated in the accompanying drawings, and shown size does not represent actual size.Although
Shown accompanying drawing not fully reflects the actual size of device exactly, but they still intactly reflect region and composition
Mutual alignment between structure, particularly constitute structure between up and down and neighbouring relations.Embodiments of the invention as described below
The given shape in region shown in accompanying drawing is should not be considered limited to, but including resulting shape, it is inclined as caused by manufacture
Difference etc..
With reference to Fig. 2 to Figure 11, a kind of technical process of the manufacture method of plough groove type proposed by the present invention point grid power device
Specifically include：
First, as shown in Fig. 2 forming the first doping type on the top in the drain region 300 of the first doping type first
Substrate epitaxial layer 301, then substrate epitaxial layer 301 top formed the first insulation film 400, first of light is carried out afterwards
Carving technology defines the position of control grid recess, the first insulation film 400 is finally etched, in the inside of the first insulation film 400
Form the opening 410 of the first insulation film.
The material of first insulation film 400 is silica or silicon nitride, in the present embodiment by taking silica as an example.
Next, as shown in figure 3, being mask etching substrate epitaxial layer 301 with the first insulation film 400, outside the substrate
That prolongs layer 301 is internally formed control grid recess 500.In the etching technics of the step, it can be formed by the etching for increasing horizontal
The lateral recesses positioned at the bottom of the first insulation film 400 of grid recess 500 are controlled, the transverse width of the lateral recesses is a.
Next, as shown in figure 4, then covering institute in the second insulation film 302 of surface formation of control grid recess first
Structure the first conductive film 600 of formation of formation, first conductive film 600 should fill up control grid recess 500.
The material of second insulation film 302 is preferably silica, the material of the first conductive film 600 for polysilicon or
Person's metal.
Next, as shown in figure 5, etch away first conductive film 600 on the top of the first insulation film 400, then along
The edge of the opening 410 of first insulation film continues to etch the first conductive film 600, so that in the both sides difference of control grid recess
Form the control gate 303 that transverse width is a, the transverse width of the control gate 303 should be to meet follow-up control gate contact hole for a
Formation on the basis of, if the transverse width of control gate 303 be a it is too small, it will influence control gate contact hole formation.
The transverse width of the control gate 303 can be limited by lateral etching technique, it is preferable that：In etching first
During conductive film 600, can first etch the first conductive film 600 to substrate epitaxial layer 301 apparent height, then again
Deposit the first insulation film and return and carve to form the first insulation film side wall 800 in the both sides of the opening 410 of the first insulation film,
The transverse width of first insulation film 800 is b, as shown in Figure 6 a；Afterwards, carved along the edge of the first insulation film side wall 800
Lose the first conductive film 600 and form control gate 303 respectively with the both sides in control grid recess 500, as shown in Figure 6 b；Thus can be by
The transverse width of control gate 303 is designed as a+b, can reduce the limitation of lateral etching technique.
Next, follow-up detailed description is still carried out to the present embodiment with structure shown in Fig. 5.
As shown in fig. 7, the second insulation film 302 that etching exposes, then deposits the 3rd insulation film and returns and carve, sudden and violent
The 3rd insulation film side wall 401 is formed on the side wall of the control gate 303 exposed, afterwards along the 3rd insulation film side wall 401
Edge etched substrate epitaxial layer 301 divides a grid recess to be formed；The material of 3rd insulation film is preferably silicon nitride.
In above-mentioned steps, a point grid recess is by being that the self aligned etching of mask is served as a contrast with the 3rd insulation film side wall 401
The formation of bottom epitaxial layer 301, because the etching of control grid recess and point grid recess only used one for etching control grid recess
Block mask plate, so as to reduce the complexity and cost of device fabrication.
Next, as shown in figure 8, forming the 4th insulation film 304 on the surface of point grid recess first, the 4th insulation is thin
The material of film 304 is preferably silica；Then, as shown in figure 9, etching away the 3rd insulation film side wall 401, and in exposed control
The surface of grid 303 processed forms the 5th insulation film 305, and the material of the 5th insulation film 305 is preferably silica.
Next, as shown in Figure 10, covering formed structure and depositing the second conductive film and return quarter, in point grid recess
A point grid 306 are formed, the surface of this point of grid 306 should be slightly below the surface of substrate epitaxial layer 301, and the material of point grid 306 is preferably to mix
Miscellaneous polysilicon.
Next, as shown in figure 11, the first insulation film 400 is etched away first, then oxidation forms one layer of thin oxidation
Surface of the layer 307 to repair substrate epitaxial layer 301；Then the ion implanting of second of doping type is carried out with substrate epitaxial
Channel regions 308 are formed in layer 301, the bottom of the channel region 308 is preferably placed at the bottom position of control grid recess, the is carried out afterwards
Two road photoetching processes define the position of source region, then carry out the ion implanting of the first doping type, the shape in substrate epitaxial layer 301
Into source region 309, formed structure is covered afterwards and deposits the 6th insulation film 310, then carries out the 3rd road photoetching process formation connect
The figure of contact hole, then etches the 6th insulation film 310 formation contact hole；Finally carry out the ion of second of doping type
Inject and the formation Ohmic contact of deposited metal 311.Wherein, the material of the 6th insulation film 310 is silica glass, boron phosphorus silicon
Glass or phosphorosilicate glass.
Second of doping type of the present invention is opposite doping type with the first doping type, and even the first is mixed
Miscellany type adulterates for n-type, then second of doping type adulterates for p-type；Or, if the first doping type adulterates for p-type, the
Two kinds of doping types adulterate for n-type.
Finally, carry out the 4th road photoetching, and metal level performed etching, with formed respectively source electrode, control grid electrode and
Divide gate electrode, deposit, pattern transfer and the etching of layer are passivated afterwards, so as to form plough groove type point grid power device.
All explanations not related to belong to techniques known in the embodiment of the present invention, refer to known skill
Art is carried out.
The present invention achieves satisfied application effect through validation trial.
Involved embodiment is to a kind of plough groove type proposed by the present invention point grid power device in above embodiment
The specific support of the manufacture method technological thought of part, it is impossible to which protection scope of the present invention is limited with this, it is every to be carried according to the present invention
The technological thought gone out, any equivalent variations done on the basis of the technical program or equivalent change, still fall within the present invention
The scope of technical scheme protection.
Claims (8)
1. the manufacture method of a kind of plough groove type point grid power device, it is characterised in that comprise the following specific steps that：
Step one：The substrate epitaxial layer of the first doping type is formed on the top in the drain region of the first doping type first, so
The first insulation film is formed on the top of substrate epitaxial layer afterwards, first of photoetching is carried out afterwards, it is finally exhausted to described first
Edge film is performed etching, in the opening for being internally formed the first insulation film of first insulation film；
Step 2：Using first insulation film described in mask etching substrate epitaxial layer, the substrate epitaxial layer inside
Control grid recess is formed, the both sides edge of the control grid recess extends to the of the both sides of the opening of first insulation film
The bottom of one insulation film, forms the lateral recesses positioned at the bottom of first insulation film；
Step 3：The second insulation film is formed on the surface of the control grid recess, the first conductive film is then deposited, this first
Conductive film fills up the control grid recess；
Step 4：Etching is located at first conductive film on the first insulation film top, and is insulated along described first
The edge of the opening of film continues to etch first conductive film, and control gate is formed in the both sides of the control grid recess；Or
Person etches first conductive film to the surface of substrate epitaxial layer first, and the first insulation film is then deposited again and is returned
Carve to form the first insulation film side wall of the opening both sides for being located at first dielectric film, it is thin along the described first insulation afterwards
The edge of film side wall etches first conductive film, and control gate is formed in the both sides of the control grid recess；
Step 5：Second insulation film of the control gate groove surfaces first to exposing is performed etching, and then deposits
Three insulation films are simultaneously returned and carved, and the 3rd insulation film side wall is formed on the side wall of the control gate exposed, afterwards along described the
The edge of three insulation film side walls etches the substrate epitaxial layer to form a point grid recess；
Step 6：The 4th insulation film is formed on the surface of described point of grid recess；
Step 7：The 3rd insulation film side wall is performed etching first, then on the control gate surface exposed and
Substrate epitaxial layer surface the 5th insulation film of formation exposed；
Step 8：Deposit the second conductive film and return and carve, a point grid are internally formed in described point of grid recess, the surface of described point of grid is omited
Less than the surface of substrate epitaxial layer；
Step 9：First insulation film is performed etching first, the ion implanting of second of doping type is then carried out,
Channel region is formed in the substrate epitaxial layer, second photoetching and the ion implanting of the first doping type are carried out afterwards, in institute
State in substrate epitaxial layer and form source region；
Step 10：The 6th insulation film of deposit and carry out the 3rd road first and be lithographically formed the figure of contact hole, then to described the
Six insulation films are performed etching to form contact hole, and the ion implanting and deposited metal that second of doping type is carried out afterwards are formed
Ohmic contact；
Step 11：The 4th road photoetching is carried out first, the metal level is then etched, to form source electrode, control gate electricity respectively
Pole and point gate electrode, are finally passivated deposit, pattern transfer and the etching of layer, so as to form plough groove type point grid power device.
2. the manufacture method of a kind of plough groove type according to claim 1 point grid power device, it is characterised in that described first
The material of insulation film is silica or silicon nitride.
3. the manufacture method of a kind of plough groove type according to claim 1 point grid power device, it is characterised in that the described 3rd
The material of insulation film is silicon nitride.
4. the manufacture method of a kind of plough groove type according to claim 1 point grid power device, it is characterised in that described second
The material of insulation film, the 4th insulation film and the 5th insulation film is silica.
5. the manufacture method of a kind of plough groove type according to claim 1 point grid power device, it is characterised in that the described 6th
The material of insulation film is silica glass, boron-phosphorosilicate glass or phosphorosilicate glass.
6. a kind of manufacture method of plough groove type according to claim 1 point grid power device, it is characterised in that the control
Grid are polysilicon gate or metal gate.
7. the manufacture method of a kind of plough groove type according to claim 1 point grid power device, it is characterised in that described second
The material of conductive film is polysilicon.
8. a kind of manufacture method of plough groove type point grid power device according to claim any one of 1-7, it is characterised in that
The first described doping type adulterates for n-type, and second of doping type adulterates for p-type；Or the first described doping class
Type adulterates for p-type, and second of doping type adulterates for n-type.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510182461.XA CN104916544B (en) | 2015-04-17 | 2015-04-17 | A kind of manufacture method of plough groove type point grid power device |
| KR1020167033055A KR101812440B1 (en) | 2015-04-17 | 2016-03-15 | Manufacturing method for split-gate power device |
| PCT/CN2016/076432 WO2016165516A1 (en) | 2015-04-17 | 2016-03-15 | Manufacturing method for split-gate power device |
| DE112016000050.2T DE112016000050B4 (en) | 2015-04-17 | 2016-03-15 | Method for manufacturing a split gate power device |
| JP2016570830A JP6310577B2 (en) | 2015-04-17 | 2016-03-15 | Manufacturing method of split gate type power device |
| US15/307,341 US9673299B2 (en) | 2015-04-17 | 2016-03-15 | Method for manufacturing split-gate power device |
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| JP6310577B2 (en) * | 2015-04-17 | 2018-04-11 | スー ジョウ オリエンタル セミコンダクター カンパニー リミテッドＳｕ Ｚｈｏｕ Ｏｒｉｅｎｔａｌ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｃｏ．， Ｌｔｄ． | Manufacturing method of split gate type power device |
| CN106653834A (en) * | 2015-09-22 | 2017-05-10 | 苏州东微半导体有限公司 | Method for manufacturing semiconductor power device |
| CN105551964B (en) * | 2015-12-25 | 2018-10-26 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of groove separation side gate MOSFET with shield grid |
| CN109216174B (en) * | 2017-07-03 | 2021-04-13 | 无锡华润上华科技有限公司 | Split gate structure of semiconductor device and manufacturing method thereof |
| CN113628968B (en) * | 2020-05-06 | 2022-06-24 | 苏州东微半导体股份有限公司 | Manufacturing method of semiconductor super junction device |
| CN112271134B (en) | 2020-10-20 | 2021-10-22 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device |
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| CN1729558A (en) * | 2002-12-19 | 2006-02-01 | 皇家飞利浦电子股份有限公司 | Vertical split gate non-volatile memory cell and method of fabrication thereof |
| CN101325157A (en) * | 2007-06-11 | 2008-12-17 | 南亚科技股份有限公司 | Memory construction and preparation method thereof |
| CN102157527A (en) * | 2009-12-31 | 2011-08-17 | 三星电子株式会社 | Semiconductor memory devices |
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| KR100607785B1 (en) * | 2004-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method for manufacturing split gate flash EEPROM |
| US20080150013A1 (en) * | 2006-12-22 | 2008-06-26 | Alpha & Omega Semiconductor, Ltd | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
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| CN1729558A (en) * | 2002-12-19 | 2006-02-01 | 皇家飞利浦电子股份有限公司 | Vertical split gate non-volatile memory cell and method of fabrication thereof |
| CN101325157A (en) * | 2007-06-11 | 2008-12-17 | 南亚科技股份有限公司 | Memory construction and preparation method thereof |
| CN102157527A (en) * | 2009-12-31 | 2011-08-17 | 三星电子株式会社 | Semiconductor memory devices |
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