CN106684126A - Trench type transistor device structure and making method - Google Patents
Trench type transistor device structure and making method Download PDFInfo
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- CN106684126A CN106684126A CN201611140369.8A CN201611140369A CN106684126A CN 106684126 A CN106684126 A CN 106684126A CN 201611140369 A CN201611140369 A CN 201611140369A CN 106684126 A CN106684126 A CN 106684126A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 239000004065 semiconductor Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 229910000906 Bronze Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- -1 aluminum copper silicon Chemical compound 0.000 claims description 6
- 239000010974 bronze Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000003870 refractory metal Substances 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 210000000746 body region Anatomy 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a trench type transistor device structure and a making method. The structure comprises a source region, a body region, a drift region, a drain region and a trench type gate region, wherein the source region, the body region, the drift region and the drain region are distributed in sequence from top to bottom; the trench type gate region is vertical to the source region, the body region, the drift region and the drain region; and the trench type gate region comprises polycrystalline silicon filled in a trench, a gate dielectric layer positioned between an inner wall of the trench and the polycrystalline silicon, and a metal conducting layer which is inserted into the polycrystalline silicon. In the trench type transistor device structure, a sandwich structure of an oxide layer/polycrystalline silicon/metal conducting layer is formed in a gate trench, and a metal with low resistivity substitutes for a part of the polycrystalline silicon with relatively high resistivity, so that the gate resistance of a device is lowered effectively, and the switching speed of the device is increased.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of groove-shaped transistor device structures and making side
Method.
Background technology
For trench type device, resistance is an important parameter.The signal of telecommunication during devices switch
Transmission speed affected by resistance, gate resistance is bigger, and the switching loss of device is bigger, and switching speed is slower.At present,
The grid of traditional trench MOSFET is to connect trench polisilicon passage by the metal of chip periphery to be transmitted to the signal of telecommunication
The cellular grid of chip internal, because transmission route is longer and resistivity of polysilicon passage is higher, so trench type device
Resistance is larger, and the switching speed of device is relatively low.Trench MOSFET device is frequently utilized for the higher occasion of frequency, because
This people have also been made many effort in terms of gate resistance is reduced.Patent CN2035317U, CN101826551A,
CN103928512A changes device structure design, but grid is made using the of a relatively high polysilicon of resistance, so
The reduction aspect of gate resistance has certain restriction.
Therefore, it is necessary in fact to provide a kind of new structure and technique, resistance is effectively reduced, so as to improve opening for device
Close speed.
The content of the invention
Prior art in view of the above, it is an object of the invention to provide a kind of groove-shaped transistor device structures and system
Make method, for solving prior art in groove-shaped transistor device resistance it is larger, devices switch is relatively lower speed
Problem.
For achieving the above object and other related purposes, the present invention provides a kind of groove-shaped transistor device structures, including：
Source region, body area, drift region and the drain region arranged successively from top to bottom, and perpendicular to the source region, body area, drift
Area and the groove-shaped grid region in drain region；
Wherein, the groove-shaped grid region includes the polysilicon being filled in groove, many with described positioned at the trench wall
Gate dielectric layer between crystal silicon, and insert the metal conducting layer inside the polysilicon.
Alternatively, the material of the metal conducting layer is refractory metal.
Alternatively, the material of the metal conducting layer be tungsten, aluminum, aluminum copper silicon, aluminum bronze, copper, or comprising tungsten, aluminum, aluminum copper silicon,
The alloy of aluminum bronze or copper.
Alternatively, the groove-shaped transistor device structures include multiple groove-shaped grid regions.
Alternatively, the groove-shaped grid region is inserted perpendicularly into and through the source region and body area.
Alternatively, the drain region is heavily doped first conductive type semiconductor layer, and the drift region is in the drain region
Epitaxial growth is lightly doped the first conductive type semiconductor layer.
Alternatively, the source region for ion implanting heavily doped first conductive type semiconductor layer, the body area be from
The second conductive type semiconductor layer of son injection.
Alternatively, the groove-shaped transistor device structures also include connecting the source region, drain region and groove-shaped grid respectively
The source electrode in area, drain electrode and gate electrode, the gate electrode is connected with the metal conducting layer in the groove-shaped grid region.
For achieving the above object and other related purposes, the present invention also provides a kind of system of channel-type semiconductor device structure
Make method, comprise the steps：
S1 provides the Semiconductor substrate of first conduction type of heavy doping, and gently mixes in semiconductor substrate surface growth
The epitaxial layer of miscellaneous first conduction type；
S2 forms on said epitaxial layer there oxide layer, and etching groove；
S3 removes the oxide layer, and forms gate dielectric layer in the trench wall；
S4 fills polysilicon in the groove；
S5 ion implantings and high annealing formation body area；
S6 ion implantings form source region；
S7 lithographic definition contact hole and carries out etching polysilicon above the groove, is subsequently filled conductive metal material,
Form the metal conducting layer inside the insertion polysilicon.
Alternatively, in step S3, it is initially formed oxide layer and the sacrifice layer described in one layer of sacrifice layer rewetting method erosion removal.
Alternatively, in step S3, grow to form gate oxide as the gate dielectric layer by the use of high-temperature oxydation.
Still optionally further, the gate oxide also covers the area surface.
Alternatively, in step S4, to after the trench fill polysilicon, the groove is removed using dry etching outer unnecessary
Polycrystalline silicon material.
Alternatively, the manufacture method also includes：Form the passivation layer for covering the polysilicon and the source electrode surface.
Alternatively, the manufacture method also includes：Formed respectively with metallic conduction in the source region, drain region and the groove
Source electrode, drain electrode and gate electrode that layer is electrically connected.
As described above, the groove-shaped transistor device structures and manufacture method of the present invention, have the advantages that：
The groove-shaped transistor device structures and manufacture method of the present invention, by increasing a contact hole photoetching process,
Polysilicon gate top forms contact hole, carries out filler metal conductive layer after the etching of polysilicon, is formed in gate trench
" sandwich " structure of oxide layer/polysilicon/metal conducting layer, a part of resistivity of the low metal substitute of resistivity is relatively high
Polysilicon, can so be such that the gate resistance of device effectively reduces, so as to improve the switching speed of device.
Description of the drawings
Fig. 1 is shown as the groove-shaped transistor device structures schematic diagram of present invention offer.
Fig. 2 is shown as the manufacture method schematic diagram of the groove-shaped transistor device structures of present invention offer.
Fig. 3 a-3h are shown as the preparation flow schematic diagram of groove-shaped transistor device structures provided in an embodiment of the present invention.
Component label instructions
100 drain regions
100 ' Semiconductor substrates
200 drift regions
200 ' epitaxial layers
201 oxide layers
300 groove-shaped grid regions
301 gate dielectric layers
301 ' gate oxides
302 polysilicons
303 metal conducting layers
304 gate electrodes
400 body areas
500 source regions
501 source electrodes
600 passivation layers
S1~S7 steps
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands easily other advantages and effect of the present invention.The present invention can also pass through concrete realities different in addition
The mode of applying is carried out or applies, the every details in this specification can also based on different viewpoints with application, without departing from
Various modifications and changes are carried out under the spirit of the present invention.It should be noted that, in the case where not conflicting, following examples and enforcement
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates in a schematic way the basic structure of the present invention
Think, only show in schema then with relevant component in the present invention rather than according to component count during actual enforcement, shape and size
Draw, it is actual when the implementing kenel of each component, quantity and ratio can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
Fig. 1 is referred to, the present invention provides a kind of groove-shaped transistor device structures, including：
Source region 500, body area 400, drift region 200 and the drain region 100 arranged successively from top to bottom, and perpendicular to the source
The groove-shaped grid region 300 in area 500, body area 400, drift region 200 and drain region 100；
Wherein, the groove-shaped grid region 300 includes being filled in polysilicon 302 in groove, positioned at the trench wall with
Gate dielectric layer 301 between the polysilicon 302, and insert the metal conducting layer 303 inside the polysilicon 302.
Specifically, the material of the metal conducting layer 303 can be selected from refractory metal, such as tungsten, aluminum, aluminum copper silicon, aluminum bronze,
The metals such as copper and the alloy comprising these compositions etc..The resistivity of the metal conducting layer 303 can be 1.75E-6-5.5E-
6 ohmcms.It can be 0.5-2 microns that the metal conducting layer 303 inserts the depth in the polysilicon 302.
In some embodiments of the invention, the groove-shaped transistor device structures can include multiple described groove-shaped
Grid region 300, and multiple source regions 500 and the body area 400 in the multiple groove-shaped grid regions 300 of correspondence.
In some embodiments of the invention, the groove-shaped grid region 300 is inserted perpendicularly into and through the source region 500 and body
Area 400.The bottom in the groove-shaped grid region 300 can contact with the drift region 200.
In some embodiments of the invention, the drain region 100 can be heavily doped first conductive type semiconductor layer,
Such as n+ types；The drift region 200 can be that the first conductive type semiconductor is lightly doped in the Epitaxial growth of the drain region 100
Layer, such as n-type.
In some embodiments of the invention, the source region 500 can be heavily doped first conductive-type of ion implanting
Type semiconductor layer, such as n+ types；The body area 400 can be the second conductive type semiconductor layer of ion implanting, such as p-type body
Area.
Source region, drain region, body area with regard to groove-shaped transistor device, the structure of drift region, material, processing technology, principle
Deng being that those skilled in the art are known, and therefore not to repeat here, source region, drain region, body area in device architecture of the present invention, drift
Area can adopt any suitable structure, material and processing technology, the invention is not limited in this regard.
In some embodiments of the invention, the groove-shaped transistor device structures can also include connecting described respectively
The source electrode 501, drain electrode (not shown in accompanying drawing) of source region 500, drain region 100 and groove-shaped grid region 300 and gate electrode
304.Gate electrode 304 can be connected with the metal conducting layer 303 inserted inside the polysilicon 302.
The present invention is changed into oxide layer/polysilicon/metal and leads the grid structure of gate oxide/polysilicon in traditional groove
" sandwich " structure of electric layer, due to the relatively high polysilicon of a part of resistivity of the low metal substitute of resistivity, so can be with
Making the gate resistance of device is effectively reduced, so as to improve the switching speed of device.
Fig. 2 is referred to, the present invention also provides a kind of manufacture method of above-mentioned groove-shaped transistor device structures, including as follows
Step：
S1 provides the Semiconductor substrate of first conduction type of heavy doping, and gently mixes in semiconductor substrate surface growth
The epitaxial layer of miscellaneous first conduction type；
S2 forms on said epitaxial layer there oxide layer, and etching groove；
S3 removes the oxide layer, and forms gate dielectric layer in the trench wall；
S4 fills polysilicon in the groove；
S5 ion implantings and high annealing formation body area；
S6 ion implantings form source region；
S7 lithographic definition contact hole and carries out etching polysilicon above the groove, is subsequently filled conductive metal material,
Form the metal conducting layer inside the insertion polysilicon.
Describe above-mentioned manufacture method in detail below by specific example.
First, as shown in Figure 3 a, there is provided the Semiconductor substrate 100 ' of first conduction type of heavy doping as drain region, and
The superficial growth of Semiconductor substrate 100 ' is lightly doped the epitaxial layer 200 ' of the first conduction type, the latter half of epitaxial layer 200 '
Will be used as drift region.
Then, as shown in Figure 3 b, form thick by chemical vapour deposition technique or the like on the epitaxial layer 200 '
The oxide layer 201 that about 2000-10000 angstrom of degree, then, trench lithography version defines grooved position, afterwards by dry etching
Form the groove of device.The width of groove can be 0.2-2 microns.
Subsequently, the oxide layer 201 is removed, and gate dielectric layer is formed in the trench wall.Preferably, can be initially formed
One layer 500-1250 angstrom of sacrifice layer, the sacrifice layer be in order to remove etching groove during silicon face damage.Wet method is used again
Etching away oxide layer 201 and the sacrifice layer, grow afterwards the gate oxide to form 150-1000 angstrom using high-temperature oxydation
301 ' used as the gate dielectric layer.The gate oxide 301 ' is also covered as the surface of epitaxial layer 200 ' of source region.
Next, as shown in Figure 3 c, polysilicon is filled in the groove by chemical vapour deposition technique or the like
302.The thickness of polysilicon 302 of filling can be 0.5-2 microns.During concrete operations, to the trench fill polycrystalline silicon material
Afterwards, the outer unnecessary polycrystalline silicon material of the groove is removed using dry etching, etching can be parked in the surface of gate oxide 301 '.
Then, as shown in Figure 3 d, high annealing forms the body area 400 of device after ion implanting.
After forming body area 400, as shown in Figure 3 e, carry out ion implanting and form source region 500.Specifically, source region can be applied
Injection reticle, defines the source electrode of device and injects in the cellular region of device, forms the device source region of heavy doping (for example, n+)
500。
Next, as illustrated in figure 3f, lithographic definition contact hole and etching polysilicon is carried out above the groove, then
Filler metal conductive material, forms the metal conducting layer 303 inside the insertion polysilicon 302, so as to form oxide layer/polycrystalline
" sandwich " structure of silicon/metal conducting layer.Wherein, the material of the metal conducting layer 303 can be selected from refractory metal, such as
The metals and the alloy comprising these compositions etc. such as tungsten, aluminum, aluminum copper silicon, aluminum bronze, copper.The metal conducting layer 303 inserts described
Depth in polysilicon 302, i.e., the depth that polysilicon 302 is etched can be 0.5-2 microns, and the diameter of the contact hole of definition can
Being 0.2-2 microns.
Afterwards, one layer can also be formed by chemical vapour deposition technique or the like and covers the surface of polysilicon 302
And the passivation layer 600 on the surface of source region 500.The thickness of passivation layer 600 can be 0.2-1 microns.Then, as shown in figure 3g, apply
Contact hole reticle defines the source contact openings of device.
Finally, the source for electrically connecting with metal conducting layer 303 in the source region 500, drain region 100 and the groove respectively is formed
Pole electrode 501, drain electrode (not shown in accompanying drawing) and gate electrode 304.Specifically using physical vaporous deposition or similar
Method forms the thick conductive material of 0.8-2 microns, and the positive and negative of silicon chip all can be deposited, and then, is defined using metal lithographic version
Go out the gate electrode of device, source electrode, as illustrated in figure 3h.
In sum, groove-shaped transistor device structures of the invention and manufacture method, by increasing a contact hole light
Carving technology, forms contact hole above polysilicon gate, filler metal conductive layer after the etching of polysilicon is carried out, in grid ditch
" sandwich " structure of oxide layer/polysilicon/metal conducting layer is formed in groove, because the etching polysilicon in groove can be carved
It is very deep, the metal conducting layer of high connductivity is filled afterwards, therefore resistance is greatly reduced, improve the switch of trench type device
Speed, makes device more adapt to high-frequency work environment.So, the present invention effectively overcomes various shortcoming of the prior art and has height
Degree industrial utilization.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and the scope without prejudice to the present invention to above-described embodiment.Cause
This, such as those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (15)
1. a kind of groove-shaped transistor device structures, it is characterised in that include：
Source region, body area, drift region and the drain region arranged successively from top to bottom, and perpendicular to the source region, body area, drift region and
The groove-shaped grid region in drain region；
Wherein, the groove-shaped grid region includes the polysilicon being filled in groove, positioned at the trench wall and the polysilicon
Between gate dielectric layer, and insert the metal conducting layer inside the polysilicon.
2. groove-shaped transistor device structures according to claim 1, it is characterised in that：The material of the metal conducting layer
For refractory metal.
3. groove-shaped transistor device structures according to claim 1, it is characterised in that：The material of the metal conducting layer
For tungsten, aluminum, aluminum copper silicon, aluminum bronze, copper, or the alloy comprising tungsten, aluminum, aluminum copper silicon, aluminum bronze or copper.
4. groove-shaped transistor device structures according to claim 1, it is characterised in that：The groove-shaped transistor device
Structure includes multiple groove-shaped grid regions.
5. groove-shaped transistor device structures according to claim 1, it is characterised in that：Vertically insert in the groove-shaped grid region
Enter and through the source region and body area.
6. groove-shaped transistor device structures according to claim 1, it is characterised in that：The drain region is heavily doped the
One conductive type semiconductor layer, the drift region is that the first conductive type semiconductor is lightly doped in the drain region Epitaxial growth
Layer.
7. groove-shaped transistor device structures according to claim 1, it is characterised in that：The source region is ion implanting
Heavily doped first conductive type semiconductor layer, the body area is the second conductive type semiconductor layer of ion implanting.
8. groove-shaped transistor device structures according to claim 1, it is characterised in that：The groove-shaped transistor device
Structure also includes connecting the source region, the source electrode in drain region and groove-shaped grid region, drain electrode and gate electrode respectively, described
Gate electrode is connected with the metal conducting layer in the groove-shaped grid region.
9. a kind of manufacture method of groove-shaped transistor device structures, it is characterised in that the method comprising the steps of：
S1 provides the Semiconductor substrate of first conduction type of heavy doping, and is lightly doped the in semiconductor substrate surface growth
The epitaxial layer of one conduction type；
S2 forms on said epitaxial layer there oxide layer, and etching groove；
S3 removes the oxide layer, and forms gate dielectric layer in the trench wall；
S4 fills polysilicon in the groove；
S5 ion implantings and high annealing formation body area；
S6 ion implantings form source region；
S7 lithographic definition contact hole and carries out etching polysilicon above the groove, is subsequently filled conductive metal material, is formed
Insert the metal conducting layer inside the polysilicon.
10. the manufacture method of groove-shaped transistor device structures according to claim 9, it is characterised in that：In step S3,
It is initially formed oxide layer and the sacrifice layer described in one layer of sacrifice layer rewetting method erosion removal.
The manufacture method of 11. groove-shaped transistor device structures according to claim 9, it is characterised in that：In step S3,
Grow to form gate oxide as the gate dielectric layer by the use of high-temperature oxydation.
The manufacture method of 12. groove-shaped transistor device structures according to claim 11, it is characterised in that：The grid oxygen
Change layer and also cover the area surface.
The manufacture method of 13. groove-shaped transistor device structures according to claim 9, it is characterised in that：In step S4,
To after the trench fill polysilicon, using dry etching the outer unnecessary polycrystalline silicon material of the groove is removed.
The manufacture method of 14. groove-shaped transistor device structures according to claim 9, it is characterised in that：The making
Method also includes：Form the passivation layer for covering the polysilicon and the source electrode surface.
The manufacture method of 15. groove-shaped transistor device structures according to claim 9, it is characterised in that：The making
Method also includes：Source electrode, drain electrode that formation is electrically connected respectively with metal conducting layer in the source region, drain region and the groove
Electrode and gate electrode.
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| CN201611140369.8A CN106684126A (en) | 2016-12-12 | 2016-12-12 | Trench type transistor device structure and making method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107768240A (en) * | 2017-09-28 | 2018-03-06 | 上海芯导电子科技有限公司 | A kind of source structure of plough groove type transistor and preparation method thereof |
| CN112309987A (en) * | 2020-10-30 | 2021-02-02 | 福建省晋华集成电路有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN113053738A (en) * | 2019-12-27 | 2021-06-29 | 华润微电子（重庆）有限公司 | Split gate type groove MOS device and preparation method thereof |
| CN117747669A (en) * | 2024-02-19 | 2024-03-22 | 中国科学院长春光学精密机械与物理研究所 | Trench gate MOS semiconductor device and manufacturing method thereof |
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| US6274905B1 (en) * | 1999-06-30 | 2001-08-14 | Fairchild Semiconductor Corporation | Trench structure substantially filled with high-conductivity material |
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| CN117747669A (en) * | 2024-02-19 | 2024-03-22 | 中国科学院长春光学精密机械与物理研究所 | Trench gate MOS semiconductor device and manufacturing method thereof |
| CN117747669B (en) * | 2024-02-19 | 2024-04-30 | 中国科学院长春光学精密机械与物理研究所 | Trench gate MOS semiconductor device and manufacturing method thereof |
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