CN107221500A - Double trench field-effect pipes and preparation method thereof - Google Patents
Double trench field-effect pipes and preparation method thereof Download PDFInfo
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- CN107221500A CN107221500A CN201710325675.7A CN201710325675A CN107221500A CN 107221500 A CN107221500 A CN 107221500A CN 201710325675 A CN201710325675 A CN 201710325675A CN 107221500 A CN107221500 A CN 107221500A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The present invention provides a kind of pair of trench field-effect pipe and preparation method, and method includes：The substrate of first conduction type and the doped layer of the first conduction type are provided, make deep trench plot structure, form deep trench electrode, make trench gate plot structure, the second conductive type layer is formed in the surface of doped layer, the first conductive type layer is formed in the surface of the second conductive type layer, make separation layer, prepare source contact electrode, form Top electrode, bottom electrode, deep trench plot structure includes the first groove area and the second groove area, first groove area has the oxide layer of first thickness, second groove area has the oxide layer of second thickness, the width in the first groove area is less than the second groove area, second thickness is more than first thickness.The present invention is by the way that deep trench electrode to be set to two parts different up and down, while certain second thickness oxidated layer thickness is ensured, the increase of distance between deep trench electrode is realized, so as to be conducive to the preparation of follow-up component, production technology is simplified, preparation cost is reduced.
Description
Technical field
The invention belongs to semiconductor device processing technology field, more particularly to a kind of pair trench field-effect pipe and its preparation
Method.
Background technology
Power transistor is generally used for control power electronic device and rationally worked, and is provided by power electronic device for load
Powerful output.Power transistor is widely used in control power output, the applying electronic equipment of HF power transistor
Scanning circuit in, such as colour TV, display, oscillograph, the horizontal scanning circuit of large-scale console, video amplifier circuit, emitter
Power amplifier etc., is also widely applied to such as intercom, the rf output circuit of mobile phone, at a high speed high-frequency oscillating circuits and electricity
In the circuits such as sub switch circuit.
It is, in general, that under conditions of power device typically operates in high voltage, high current, generally possessing high pressure, work
The features such as electric current is big, itself dissipated power is big, therefore there is certain difference with general low-power device when in use.In order to get out of the way
The function of closing device obtains good performance, and power semiconductor field effect transistor needs to meet two basic demands：1st, device is worked as
When part is in the conduction state, low-down conducting resistance can be possessed, the power attenuation of device in itself is minimized；2nd, when device is in
During off state, sufficiently high breakdown reverse voltage can be possessed.
Existing power transistor typically uses superjunction transistor arrangement, however, the preparation technology of superjunction transistor is complicated,
Due to the influence of the techniques such as annealing, the ion phase counterdiffusion in superjunction is easily caused doping concentration and actually has larger deviation,
And the breakdown voltage of superjunction transistor is more sensitive to ion doping concentration, especially exist so as to substantially increase manufacture craft
The difficulty of high-dopant concentration, the manufacture craft of the wide device of low knot.Further, the power transistor of super-junction structure is generally used for height
In pressure or mesohigh circuit, because the width of super-junction structure power transistor has certain limitation, for the electricity less than 180V
Road, general super-junction structure power transistor is difficult to.
In addition, with the continuous reduction of dimensions of semiconductor devices, also limit the transistor with side oxygen (OB) structure
The increase of distance between deep trench electrode, thus also further increase trench gate plot structure and source contact electrode formation
Complex process degree, has ultimately resulted in the technology difficulty and its cost of manufacture of device.
Sufficiently high breakdown reverse voltage can have been realized there is provided one kind and possess low-down conducting in view of the above
Resistance, and with the distance between larger deep trench electrode so as to which the real category of the transistor of simplified technique and preparation method thereof must
Will.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of pair of trench field-effect pipe and its
Preparation method, for solve in the prior art with side oxygen (OB) structure transistor it is size-limited and cause complex process,
The problem of cost is high is prepared, and further improves its breakdown reverse voltage and reduces its conducting resistance.
In order to achieve the above objects and other related objects, the present invention provides the preparation method of a kind of pair of trench field-effect pipe,
The preparation method comprises the following steps：
1) Semiconductor substrate of the first conduction type is provided, in the semiconductor substrate surface the first conduction type of formation
Doped layer；
2) spaced two deep trench plot structures are made in the doped layer, the deep trench plot structure includes leaning on
First groove area of the nearly doped layer upper surface and the second groove area being connected with the first groove area lower section, first groove
Area surface has the first oxide layer of first thickness, and the second groove area surface has the second oxide layer of second thickness, wherein,
The width in the first groove area is less than the width in the second groove area, and the second thickness is more than the first thickness；
3) in depositing conductive material in the deep trench plot structure to form deep trench electrode；
4) trench gate plot structure is made in the doped layer between the deep trench electrode, and the groove grid region is tied
There is default spacing between structure and the deep trench electrode；
5) the second conductive type layer is formed in the surface of the doped layer of first conduction type；
6) the first conductive type layer is formed in the surface of second conductive type layer；
7) in step 6) obtained by body structure surface formation separation layer, and etch the separation layer to expose deep trench electricity
Pole and the region for going out source contact electrode to be prepared, then deposited metal material is to form Top electrode；
8) Semiconductor substrate of first conduction type is thinned, then deposited metal material is to form bottom electrode.
It is used as a preferred embodiment of the present invention, step 1) include step：
The Semiconductor substrate of the first conduction type is provided, by epitaxy technique in semiconductor substrate surface formation first
The doped layer of conduction type；
Or：
Semi-conductive substrate is provided, the doping process formation the of different levels of doping twice is carried out to the Semiconductor substrate
The doped layer of the Semiconductor substrate of one conduction type and the first conduction type.
It is used as a preferred embodiment of the present invention, step 2) in, making the deep trench plot structure includes step：
2-1) in the doping layer surface formation insulating barrier, and by photo etching process in the insulating barrier and described
Doped layer is to form the first groove of the first depth；
2-2) the first oxide layer and mask layer of first thickness are sequentially formed in the first groove side wall of first depth；
2-3) continue to perform etching the doped layer to form the second groove of the second depth based on the mask layer；
2-4) second groove to second depth is aoxidized to form the second oxide layer of second thickness, and is removed
The mask layer, to form deep trench plot structure.
As a preferred embodiment of the present invention, first depth is 1~2 μm, and second depth is 400~800 μ
m。
It is used as a preferred embodiment of the present invention, step 2) in, the second thickness is 0.4~0.8 μm.
It is used as a preferred embodiment of the present invention, step 4) in, making the trench gate plot structure includes step：
The region between the deep trench electrode 4-1) is etched to form grid region groove；
4-2) in grid region flute surfaces formation grid oxide layer；
4-3) in filling grid material in the grid oxide layer, to form the trench gate plot structure.
As a preferred embodiment of the present invention, the depth of the trench gate plot structure formed is less than the deep trench
The depth of electrode.
It is used as a preferred embodiment of the present invention, step 5) in, by the injection of the second conductive type ion with described the
The surface of the doped layer of one conduction type forms the second conductive type layer.
It is used as a preferred embodiment of the present invention, step 6) in, by the injection of the first conductive type ion with described the
The surface of two conductive type layers forms the first conductive type layer.
It is used as a preferred embodiment of the present invention, step 7) in, the source contact electrode and the trench gate plot structure
The distance between be more than the distance between the source contact electrode and described deep trench electrode.
The present invention also provides a kind of pair of trench field-effect pipe, wherein, described pair of trench field-effect pipe is using above-mentioned any
A kind of double trench field-effect pipes obtained by preparation method, described pair of trench field-effect pipe includes：
The drain region of first conduction type；
The drift region of first conduction type, is incorporated on the drain region；
The channel region of second conduction type, is incorporated on the drift region；
The source region of first conduction type, is incorporated on the channel region；
Trench gate plot structure, including in the middle part of the source region and extend to the grid with predetermined depth of the drift region
Area's groove, the grid material for being incorporated into the grid oxide layer of the grid region flute surfaces and being filled in the grid oxide layer；
Deep trench electrode, including be located at the trench gate plot structure both sides respectively and extend longitudinally to the depth of the drift region
Groove plot structure, and the conductive material being filled in the deep trench plot structure, the deep trench plot structure are included close to institute
The the second groove area for stating the first groove area of source region and being connected with the first groove area second groove, the first groove area surface tool
There is the first oxide layer of first thickness, the second groove area surface has the second oxide layer of second thickness, wherein, described first
The width in groove area is less than the width in the second groove area, and the second thickness is more than the first thickness；
Separation layer, is incorporated into the source region, the deep trench electrode and the trench gate plot structure surface, and with correspondence
In the source region and the electrode through hole of the deep trench electrode；
Top electrode, is covered in the insulation surface and by the electrode through hole and the source region and the deep trench electricity
Extremely it is connected；
Bottom electrode, is incorporated into another surface relative with the drift region of first conductivity type drain region.
As a preferred embodiment of the present invention, the depth in the first groove area is 1~2 μm, the depth in the second groove area
Spend for 400~800 μm, the second thickness is 0.4~0.8 μm.
As a preferred embodiment of the present invention, the drain region is the first conductive type semiconductor material of heavy doping, institute
It is the first conductive type semiconductor material being lightly doped to state drift region.
As described above, the present invention provides a kind of pair of trench field-effect pipe and preparation method thereof, have the advantages that：
1) present invention is ensureing the second certain ditch by the way that deep trench electrode to be set to two-part structures different up and down
While groove oxidated layer thickness, the increase of the distance between deep trench electrode is realized, so as to be conducive to the system of follow-up component
It is standby, production technology is simplified, preparation cost is reduced；
2) present invention use longitudinally disposed grid region, because actual area coverage is small, effectively reduce grid electric charge (Qg) and
Gate-drain charge (Qgd), so that switching speed is improved, in addition, the electrode district set in the wall deep trench of side, due to its Electric Field Modulated
And charge-compensation effects so that it is higher that the doping concentration of drift region can be done, so as to effectively reduction drain-source conducting resistance
(Rdson)。
Brief description of the drawings
Fig. 1~Fig. 6 is shown as the preparation method step 1 of double trench field-effect pipes of the present invention) and step 2) presented
Structural representation.
Fig. 7 is shown as the preparation method step 3 of double trench field-effect pipes of the present invention) structural representation that is presented.
Fig. 8~Figure 11 is shown as the preparation method step 4 of double trench field-effect pipes of the present invention) structural representation that is presented
Figure.
Figure 12 is shown as the preparation method step 5 of double trench field-effect pipes of the present invention) structural representation that is presented.
Figure 13 is shown as the preparation method step 6 of double trench field-effect pipes of the present invention) structural representation that is presented.
Figure 14~Figure 15 is shown as the preparation method step 7 of double trench field-effect pipes of the present invention) structure that is presented shows
It is intended to.
Figure 16 is shown as the preparation method step 8 of double trench field-effect pipes of the present invention) structural representation that is presented.
Component label instructions
101 Semiconductor substrates
102 doped layers
103 insulating barriers
1031 oxide layers
1032 mask layers
104 deep trench
1041 first grooves
1042 second grooves
105 deep trench plot structures
1051 first groove areas
1052 second groove areas
106 conductive materials
107 grid region grooves
108 grid oxide layers
109 grid materials
110 second conductive type layers
111 first conductive type layers
112 separation layers
113 electrode through holes
114 Top electrodes
115 source contact electrodes
116 deep trench electrodes
117 trench gate plot structures
118 bottom electrodes
119 sacrificial oxide layers
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Figure 16.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, then in schema only display with relevant component in the present invention rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 1~Figure 16, the present embodiment provides the preparation method of a kind of pair of trench field-effect pipe, including step：
1) Semiconductor substrate of the first conduction type is provided, in the semiconductor substrate surface the first conduction type of formation
Doped layer；
2) spaced two deep trench plot structures are made in the doped layer, the deep trench plot structure includes leaning on
First groove area of the nearly doped layer upper surface and the second groove area being connected with the first groove area lower section, first groove
Area surface has the first oxide layer of first thickness, and the second groove area surface has the second oxide layer of second thickness, wherein,
The width in the first groove area is less than the width in the second groove area, and the second thickness is more than the first thickness；
3) in depositing conductive material in the deep trench plot structure to form deep trench electrode；
4) trench gate plot structure is made in the doped layer between the deep trench electrode, and the groove grid region is tied
There is default spacing between structure and the deep trench electrode；
5) the second conductive type layer is formed in the surface of the doped layer of first conduction type；
6) the first conductive type layer is formed in the surface of second conductive type layer；
7) in step 6) obtained by body structure surface formation separation layer, and etch the separation layer to expose deep trench electricity
Pole and the region of source contact electrode to be prepared, then deposited metal material is to form Top electrode；
8) Semiconductor substrate of first conduction type is thinned, then deposited metal material is to form bottom electrode.
The preparation method of double trench field-effect pipes of the present invention is discussed in detail with reference to specific accompanying drawing.
As shown in figure 1, carrying out step 1 first) there is provided the Semiconductor substrate 101 of the first conduction type, in the semiconductor
The surface of substrate 101 forms the doped layer 102 of the first conduction type；
As an example, step 1) it can be realized using following steps：
The Semiconductor substrate 101 of the first conduction type is provided, by epitaxy technique in the surface shape of Semiconductor substrate 101
Into the doped layer 102 of the first conduction type；
Or：
Semi-conductive substrate is provided, the doping process formation the of different levels of doping twice is carried out to the Semiconductor substrate
The doped layer 102 of the conduction type of Semiconductor substrate 101 and first of one conduction type.
Specifically, drain electrode of the Semiconductor substrate 101 of first conduction type as transistor, and be heavy doping
N-type semiconductor material, then forms the doped layer 102 of the first conduction type, the doped layer in the Semiconductor substrate 101
102 be the N-type semiconductor material that is lightly doped, the doped layer 102 as transistor drift region.
As shown in figs. 1 to 6, step 2 is carried out), spaced two deep trench plot structures are made in the doped layer
105, the deep trench plot structure 105 is included close to the first groove area 1051 of the upper surface of doped layer 102 and with described the
The second groove area 1052 that one groove area 1051 is connected, the surface of the first groove area 1051 has the first oxide layer of first thickness,
The surface of second groove area 1052 has the second oxide layer of second thickness, wherein, the width in the second groove area 1052 is more than
The width in the first groove area 1051, and the second thickness is more than the first thickness；
As an example, step 2) in, making the deep trench plot structure 105 includes step：
Insulating barrier 103 2-1) is formed in the surface of doped layer 102, and by photo etching process in the insulating barrier
103 and the doped layer 102 to form the first groove 1041 of the first depth；
2-2) the side wall of first groove 1041 in first depth sequentially forms the first oxide layer of first thickness and covered
Film layer, as shown in Figure 3；
2-3) continue to perform etching the doped layer to form the second groove of the second depth based on the mask layer
1042；
2-4) second groove 1042 to second depth is aoxidized to form the second oxide layer of second thickness, and
Remove the mask layer, to form the deep trench plot structure 105, as shown in Figures 5 and 6.
Specifically, step 2-1) in, the material of the insulating barrier 103 can appoint for well known within the skill of those ordinarily skilled
Meaning material, can be that monolayer material can also be laminated material, in the present embodiment, and the insulating barrier 103 includes being formed at institute
State the oxide layer 1031 on the surface of doped layer 102 and be formed at the mask layer 1032 on the surface of oxide layer 1031, wherein, it is described
The material of oxide layer 1031 is silica, and the material of the mask layer 1032 is silicon nitride.Further, the oxide layer 1031
Thickness is 100~300 angstroms, and the thickness of the mask layer 1032 is 1000~3000 angstroms, in the present embodiment, the silica
Thickness is 200 angstroms, and the thickness of the silicon nitride is 2000 angstroms.
Specifically, in the present embodiment, step 2-2) obtained by structure formation, including first in first depth
Groove 1041 bottom and side wall be all sequentially depositing the oxide layer (such as silica) and mask layer (such as silicon nitride), wherein,
The thickness of the oxide layer is preferably 100~300 angstroms, is in the present embodiment 200 angstroms, the thickness of the mask layer is preferably
400~600 angstroms, selection in the present embodiment is 500 angstroms；Then the oxidation of the bottom of groove 1041 of first depth is removed again
Layer and mask layer, and the structure obtained using this carries out follow-up etching technics, as shown in Figures 2 and 3 as mask.
Further, in the present embodiment, step 2-4) after, in addition to remove the insulating barrier 103 on the surface of doped layer 102
In 1032 silicon nitride of mask layer the step of.
In addition, in the present embodiment, the depth of the deep trench plot structure 105 is less than the thickness of the doped layer 102, when
So, in other embodiments, the depth of the deep trench plot structure 105 can also be more than or equal to the doped layer 102
Thickness, is not particularly limited herein.
As an example, first depth is 1~2 μm, second depth is 400~800 μm.
As an example, step 2) in, the second thickness is 0.4~0.8 μm.
Specifically, in the present embodiment, first depth is 1.5 μm, second depth is 600 μm, described second
Thickness is 0.6 μm.
It should be noted that the thickness of the oxide layer in the second groove area 1052 need to be according to transistor operating voltage and institute
The conditions such as the minimum disruptive voltage value needed are limited, in other embodiments, and its thickness can be beyond described in the present embodiment
Number range.Explanation is needed further exist for, due to the limitation in technique and device performance requirements, between current deep trench electrode
It is in small distance, such as to meet oxide layer (the second groove area 1052 in the present embodiment of thicker deep trench electrode district
Second thickness the second oxide layer) thickness to ensure the breakdown voltage of transistor, according to the way of prior art, the depth
The distance between groove plot structure 105 is limited with the distance of its required oxide layer opposite side, and the application is by deep trench
Plot structure 105 is designed to the structure in the first groove area 1051 and the second groove area 1052, it is ensured that bottom oxide layer, i.e., described second
The thickness of second oxide layer in groove area, meanwhile, the distance between described deep trench plot structure 105 has been increased to described first
The distance of the opposite side of the oxide layer in groove area 1051, that is, add the distance between deep trench electrode 116 for subsequently preparing, so
The preparation of follow-up trench gate plot structure 117 and the grade device of Source contact electrode 115 is also easier.
As shown in fig. 7, carrying out step 3), deposition conductive material 106 is to form zanjon in the deep trench plot structure 105
Groove electrode 116；
Specifically, in the present embodiment, the conductive material 106 is polycrystalline silicon material, certainly, in other embodiments
In, the conductive material 106 can be desired other all electrically conductive materials.
Further, the electrode district that the present invention is set in deep trench electrode 116, due to its Electric Field Modulated and charge compensation effect
Should so that it is higher that the doping concentration of drift region can be done, so as to effectively reduction drain-source conducting resistance (Rdson).
As shown in figs. 8-10, step 4 is carried out), the interior making of the doped layer 102 between the deep trench electrode 116
There is default spacing between trench gate plot structure 117, and the trench gate plot structure 117 and the deep trench electrode 116；
As an example, step 4) in, making the trench gate plot structure 117 includes step：
The region between the deep trench electrode 116 4-1) is etched to form grid region groove 107, as shown in Figure 8；
Grid oxide layer 108 4-2) is formed in the surface of grid region groove 107, as shown in figure 11；
4-3) in filling grid material 109 in the grid oxide layer 108, to form the grid region groove structure 117, such as Figure 11
It is shown.
Specifically, mask plate is made first and the doped layer 102 is etched to form grid region groove 107, then using heat
Method for oxidation or sedimentation are SiO forming grid oxide layer 108, the grid oxide layer 108 in the grid region groove 1072Layer, finally
Deposition of gate material 109 is to form the grid region structure 117 in the grid region groove 107, and the grid material 109 uses many
Crystal silicon material.
Furthermore it is preferred that step 4-1) after, in addition to step：Formed in the bottom of formed grid region groove 107 and side wall
One layer of sacrificial oxide layer 119, as shown in figure 9, then removing the sacrificial oxide layer 119 and the grid region groove simultaneously again
The oxide layer positioned at the surface of doped layer 102 around 107, as shown in Figure 10, wherein, remove the technique bag of above-mentioned oxide layer
Include but be not limited to wet etching, after aforesaid operations, step 4-2 is then performed again), further form high-quality gate oxidation
Layer 108, and the surface for the doped layer for simultaneously extending to oxide layer around the grid region groove 107.It is of course also possible to enter
Row first passes through the oxide layer on doped layer around wet etching removal grid region groove, then sunk again after grid region groove 107 is formed
The technique of product sacrifice layer, is not particularly limited herein.
The present invention uses longitudinally disposed trench gate plot structure 117, because actual area coverage is small, can effectively reduce
Grid electric charge (Qg) and gate-drain charge (Qgd), so as to improve switching speed.
As an example, step 4) in, the depth of the trench gate plot structure 117 formed is less than the deep trench electrode
116 depth.
As shown in figure 12, step 5 is carried out), form second in the surface of the doped layer 102 of first conduction type conductive
Type layer 110；
As an example, step 5) in, by the injection of the second conductive type ion with the doping of first conduction type
The surface of layer forms the second conductive type layer.
Specifically, in the present embodiment, by the injection of the second conductive type ion with first conduction type doping
102 surface of layer form the second conductive type layer 110, i.e., the N-type drift region progress ion implanting being lightly doped to described is to form the
Two conductive type layers 110, use boron ion to be injected to form P-type layer, and be used as the channel region of transistor herein.It is preferred that
Ground, is additionally included in and carries out performing etching step to the oxide layer on the surface of doped layer 102 before ion implanting, so that the oxygen is thinned
Change layer, so that follow-up ion implantation technology is more beneficial for, and the oxide layer being thinned keeps certain thickness to reduce
The damage of material surface caused by ion implantation technology.
It should be noted that first conduction type and the second conduction type transoid conduction type each other.In this implementation
In example, first conduction type is N-type conduction type, and second conduction type is P-type conduction type.Obviously, other
Embodiment in, first conduction type can also be P-type conduction type, and second conduction type can be conductive for N-type
Type, the two can be exchanged.
As shown in figure 13, step 6 is carried out), form the first conductive type layer in the surface of second conductive type layer 110
111；
As an example, step 6) in, by the injection of the first conductive type ion with the table of second conductive type layer
Face forms the first conductive type layer.
Specifically, in the present embodiment, by the injection of the first conductive type ion with second conductive type layer 110
Surface forms the first conductive type layer 111, in specific implementation process, and the P-type channel area is entered using arsenic or phosphonium ion
Row heavy doping, to form heavily doped N-type floor in the P-type channel area, the heavily doped N-type layer as transistor source region.
As shown in Figure 14~14, carry out step 7), in step 6) obtained by body structure surface formation separation layer 112, and etch
Region of the separation layer 112 to expose the deep trench electrode and go out source contact electrode 115 to be prepared, then deposits gold
Belong to material to form Top electrode 114；
Specifically, being first that heavily doped N-type area surface makes low temperature SiO in first conductive type layer 1112Layer
(LTO), then in the low temperature SiO2Boron-phosphorosilicate glass (BPSG) is prepared on layer, to complete the preparation of the separation layer 112, when
So, in other embodiments, or other kinds of separation layer.
Specifically, etching the separation layer 112 to expose the deep trench electrode 116 and source contact electrode to be prepared
115 region, that is, form several electrode through holes 113, and then deposited metal material makes the source region to form Top electrode 114
Contact electrode 115 is contacted with the conductive type layer 111 of the second conductive type layer 110 and first simultaneously, while making Top electrode 114
It is electrically connected with deep trench electrode 116, to complete the making of the deep slot power semiconductor field effect transistor.
As an example, step 7) in, the distance between the source contact electrode 115 and the trench gate plot structure 117
More than the distance between the source contact electrode 115 and described deep trench electrode 116.
, can be with specifically, this arrangement enhance the distance between source contact electrode 115 and trench gate plot structure 117
The risk for occurring short circuit between source contact electrode and trench gate plot structure is substantially reduced, technology prejudice is overcome.In this implementation
In example, the distance between the trench gate plot structure 117 and the deep trench electrode 116 are no more than 0.8um, and the source region connects
The width of touched electrode 115 is not less than 0.3um.
As shown in figure 16, step 8 is carried out), the Semiconductor substrate 101 of first conduction type is thinned, gold is then deposited
Belong to material to form bottom electrode 118.
As shown in figure 16, the present invention also provides a kind of pair of trench field-effect pipe, wherein, described pair of trench field-effect pipe is to adopt
With double trench field-effect pipes obtained by any one above-mentioned preparation method, Fig. 1~Figure 15, described pair of groove are specifically referred to
Effect pipe includes：
The leakage 101 of first conduction type；
The drift region 102 of first conduction type, is incorporated on the drain region 101；
The channel region 110 of second conduction type, is incorporated on the drift region 102；
The source region 111 of first conduction type, is incorporated on the channel region 110；
Trench gate plot structure 117, including positioned at the middle part of source region 111 and extend to having in advance for the drift region 102
If the grid region groove of depth, it is incorporated into the grid oxide layer 108 of the grid region flute surfaces and is filled in the grid oxide layer 108
Grid material 109；
Deep trench electrode 116, including be located at the both sides of trench gate plot structure 117 respectively and extend longitudinally to the drift
The deep trench plot structure 105 in area 102, and the conductive material 106 being filled in the deep trench plot structure 105, wherein, institute
Stating deep trench plot structure 105 includes the first groove 1051 of the close source region 111 and is connected with the first groove 1051
Logical second groove 1052, the surface of the first groove area 1051 has the first oxide layer of first thickness, the second groove area
1052 surfaces have the second oxide layer of second thickness, and the width of the first groove 1051 is less than the second groove 1052
Width, and the second thickness is more than the first thickness；
Separation layer 112, is incorporated into the source region 111, the deep trench electrode 116 and the table of trench gate plot structure 117
Face, and with the electrode through hole 113 corresponding to the source region 111 and the deep trench electrode 116；
Top electrode 114, is covered in the surface of separation layer 112 and by the electrode through hole 113 and the phase of source region 111
Even；
Bottom electrode 118, is incorporated into another table relative with the drift region 102 of first conductivity type drain region 101
Face.
As an example, the depth of the first groove is 1~2 μm, preferably 1.5 μm, the depth of the second groove is
400~800 μm, preferably 600 μm, the second thickness is 0.4~0.8 μm, preferably 0.6 μm.
Specifically, in the present embodiment, oxide layer is also included between the source region 111 and the Top electrode 114, wherein,
The thickness of the oxide layer is 100~300 angstroms, preferably 200 angstroms.In addition, the depth of the trench gate plot structure 117 is less than institute
State the depth of deep trench electrode 116.
As an example, the drain region is the first conductive type semiconductor material of heavy doping, the drift region is to be lightly doped
The first conductive type semiconductor material.
It should be noted that first conduction type and the second conduction type transoid conduction type each other.In this implementation
In example, first conduction type is N-type conduction type, and second conduction type is P-type conduction type.Obviously, other
Embodiment in, first conduction type can also be P-type conduction type, and second conduction type can be conductive for N-type
Type, the two can be exchanged.
As described above, the present invention provides a kind of pair of trench field-effect pipe and preparation method thereof, the preparation method includes step
Suddenly：1) Semiconductor substrate of the first conduction type is provided, in the doping of the semiconductor substrate surface the first conduction type of formation
Layer；2) spaced two deep trench plot structures are made in the doped layer, the deep trench plot structure is included close to institute
The the second groove area for stating the first groove area of doped layer upper surface and being connected with the first groove area lower section, the first groove area table
Face has the first oxide layer of first thickness, and the second groove area surface has the second oxide layer of second thickness, wherein, it is described
The width in the first groove area is less than the width in the second groove area, and the second thickness is more than the first thickness；；3) in described
Conductive material is deposited in deep trench plot structure to form deep trench electrode；4) doped layer between the deep trench electrode
Interior make between trench gate plot structure, and the trench gate plot structure and the deep trench electrode has default spacing；5) in institute
The surface for stating the doped layer of the first conduction type forms the second conductive type layer；6) in the surface shape of second conductive type layer
Into the first conductive type layer；7) in step 6) obtained by body structure surface formation separation layer, and etch the separation layer to expose
State deep trench electrode and go out the region of source contact electrode to be prepared, then deposited metal material is to form Top electrode；8) subtract
The Semiconductor substrate of thin first conduction type, then deposited metal material is to form bottom electrode.The present invention is by by zanjon
Groove electrode is set to two-part structures different up and down, while the oxidated layer thickness of certain second groove is ensured, realizes
The increase of the distance between deep trench electrode, so as to be conducive to the preparation of follow-up component, simplifies production technology, reduces
Prepare cost；The present invention uses longitudinally disposed grid region, because actual area coverage is small, effectively reduces grid electric charge (Qg) and grid
Charge leakage (Qgd), so as to improve switching speed, in addition, the electrode district set in the wall deep trench of side, due to its Electric Field Modulated and
Charge-compensation effects so that it is higher that the doping concentration of drift region can be done, so as to effectively reduction drain-source conducting resistance
(Rdson)。
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (13)
1. the preparation method of a kind of pair of trench field-effect pipe, it is characterised in that the preparation method comprises the following steps：
1) Semiconductor substrate of the first conduction type is provided, in the doping of the semiconductor substrate surface the first conduction type of formation
Layer；
2) spaced two deep trench plot structures are made in the doped layer, the deep trench plot structure is included close to institute
The the second groove area for stating the first groove area of doped layer upper surface and being connected with the first groove area lower section, the first groove area table
Face has the first oxide layer of first thickness, and the second groove area surface has the second oxide layer of second thickness, wherein, it is described
The width in the first groove area is less than the width in the second groove area, and the second thickness is more than the first thickness；
3) in depositing conductive material in the deep trench plot structure to form deep trench electrode；
4) in the doped layer between the deep trench electrode make trench gate plot structure, and the trench gate plot structure with
There is default spacing between the deep trench electrode；
5) the second conductive type layer is formed in the surface of the doped layer of first conduction type；
6) the first conductive type layer is formed in the surface of second conductive type layer；
7) in step 6) obtained by body structure surface formation separation layer, and etch the separation layer with expose the deep trench electrode with
And the region of source contact electrode to be prepared, then deposited metal material is to form Top electrode；
8) Semiconductor substrate of first conduction type is thinned, then deposited metal material is to form bottom electrode.
2. the preparation method of according to claim 1 pair of trench field-effect pipe, it is characterised in that step 1) include step：
The Semiconductor substrate of first conduction type is provided, it is conductive in semiconductor substrate surface formation first by epitaxy technique
The doped layer of type；
Or：
Semi-conductive substrate is provided, the doping process formation first that different levels of doping twice is carried out to the Semiconductor substrate is led
The doped layer of the Semiconductor substrate of electric type and the first conduction type.
3. the preparation method of according to claim 1 pair of trench field-effect pipe, it is characterised in that step 2) in, make institute
Stating deep trench plot structure includes step：
2-1) in the doping layer surface formation insulating barrier, and by photo etching process in the insulating barrier and the doping
Layer is to form the first groove of the first depth；
2-2) the first oxide layer and mask layer of first thickness are sequentially formed in the first groove side wall of first depth；
2-3) continue to perform etching the doped layer to form the second groove of the second depth based on the mask layer；
2-4) second groove to second depth is aoxidized to form the second oxide layer of second thickness, and removes described
Mask layer, to form deep trench plot structure.
4. the preparation method of according to claim 3 pair of trench field-effect pipe, it is characterised in that first depth is 1
~2 μm, second depth is 400~800 μm.
5. the preparation method of according to claim 1 pair of trench field-effect pipe, it is characterised in that step 2) in, described
Two thickness are 0.4~0.8 μm.
6. the preparation method of according to claim 1 pair of trench field-effect pipe, it is characterised in that step 4) in, make institute
Stating trench gate plot structure includes step：
The region between the deep trench electrode 4-1) is etched to form grid region groove；
4-2) in grid region flute surfaces formation grid oxide layer；
4-3) in filling grid material in the grid oxide layer, to form the trench gate plot structure.
7. the preparation method of according to claim 1 pair of trench field-effect pipe, it is characterised in that step 4) in, formed
The trench gate plot structure depth be less than the deep trench electrode depth.
8. the preparation method of according to claim 1 pair of trench field-effect pipe, it is characterised in that step 5) in, pass through
The injection of two conductive type ions is with the second conductive type layer of the surface of the doped layer of first conduction type formation.
9. the preparation method of according to claim 1 pair of trench field-effect pipe, it is characterised in that step 6) in, pass through
The injection of one conductive type ion is with the first conductive type layer of the surface of second conductive type layer formation.
10. the preparation method of according to claim 1 pair of trench field-effect pipe, it is characterised in that step 7) in, the source
Area contact the distance between electrode and described trench gate plot structure be more than the source contact electrode and the deep trench electrode it
Between distance.
11. a kind of pair of trench field-effect pipe, it is characterised in that described pair of trench field-effect pipe includes：
The drain region of first conduction type；
The drift region of first conduction type, is incorporated on the drain region；
The channel region of second conduction type, is incorporated on the drift region；
The source region of first conduction type, is incorporated on the channel region；
Trench gate plot structure, including in the middle part of the source region and extend to the grid region ditch with predetermined depth of the drift region
Groove, the grid material for being incorporated into the grid oxide layer of the grid region flute surfaces and being filled in the grid oxide layer；
Deep trench electrode, including be located at the trench gate plot structure both sides respectively and extend longitudinally to the deep trench of the drift region
Plot structure, and the conductive material being filled in the deep trench plot structure, the deep trench plot structure are included close to the source
The first groove area in area and the second groove area being connected with the first groove area second groove, the first groove area surface have the
First oxide layer of one thickness, the second groove area surface has the second oxide layer of second thickness, wherein, the first groove area
Width be less than the second groove area width, and the second thickness be more than the first thickness；
Separation layer, is incorporated into the source region, the deep trench electrode and the trench gate plot structure surface, and with corresponding to institute
State the electrode through hole of source region and the deep trench electrode；
Top electrode, is covered in the insulation surface and by the electrode through hole and the source region and the deep trench electrode phase
Even；
Bottom electrode, is incorporated into another surface relative with the drift region of first conductivity type drain region.
12. according to claim 11 pair of trench field-effect pipe, it is characterised in that the depth in the first groove area is 1~2
μm, the depth in the second groove area is 400~800 μm, and the second thickness is 0.4~0.8 μm.
13. according to claim 11 pair of trench field-effect pipe, it is characterised in that led for the first of heavy doping in the drain region
Electric type of semiconductor material, the drift region is the first conductive type semiconductor material being lightly doped.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107731732A (en) * | 2017-11-03 | 2018-02-23 | 上海新储集成电路有限公司 | A kind of deep trench isolation structure |
| CN109830526A (en) * | 2019-02-27 | 2019-05-31 | 中山汉臣电子科技有限公司 | A kind of power semiconductor and preparation method thereof |
| CN111446168A (en) * | 2020-03-16 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Process method for generating double-groove transistor by using silicon nitride isolation layer |
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| CN104078503A (en) * | 2013-03-25 | 2014-10-01 | 株式会社东芝 | Semiconductor device |
| CN104362091A (en) * | 2014-09-30 | 2015-02-18 | 无锡同方微电子有限公司 | Double-trench field-effect transistor manufacturing method |
| WO2017007584A1 (en) * | 2015-07-08 | 2017-01-12 | Vishay-Siliconix | Semiconductor device with non-uniform trench oxide layer |
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| CN104078503A (en) * | 2013-03-25 | 2014-10-01 | 株式会社东芝 | Semiconductor device |
| CN104362091A (en) * | 2014-09-30 | 2015-02-18 | 无锡同方微电子有限公司 | Double-trench field-effect transistor manufacturing method |
| WO2017007584A1 (en) * | 2015-07-08 | 2017-01-12 | Vishay-Siliconix | Semiconductor device with non-uniform trench oxide layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107731732A (en) * | 2017-11-03 | 2018-02-23 | 上海新储集成电路有限公司 | A kind of deep trench isolation structure |
| CN109830526A (en) * | 2019-02-27 | 2019-05-31 | 中山汉臣电子科技有限公司 | A kind of power semiconductor and preparation method thereof |
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