CN104658901A - Preparation method for split gate trench MOSFET(metal-oxide-semiconductor-field-effect-transistor) - Google Patents
Preparation method for split gate trench MOSFET(metal-oxide-semiconductor-field-effect-transistor) Download PDFInfo
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Abstract
The invention provides a preparation method for a split gate trench MOSFET (metal-oxide-semiconductor-field-effect-transistor). The preparation method comprises the following steps: (1) providing a substrate, and growing an epitaxial layer on the surface of the substrate; (2) etching the epitaxial layer to form a trench with a first depth, depositing a nitride layer on the surface of the trench, then corroding off the nitride layer at the bottom of the trench, and retaining the nitride layer on the side wall; (3) continuously etching the epitaxial layer material at the bottom of the trench to reach a second depth, and thermally growing an oxide layer attached to the side wall and the bottom of the trench which is not covered by the nitride layer; (4) filling the lower part of the trench with a first conductive material, removing the nitride layer on the side wall, and manufacturing an isolating layer on the surface of the first conductive material; (5) growing a gate oxide layer covering the exposed side wall of the upper part of the trench, and filling the upper part of the trench with a second conductive material to form the split gate trench MOSFET with the narrower upper part and the wider lower part. The device structure prepared by the preparation method disclosed by the invention can acquire a larger source region area and a larger source region contact hole; the avalanche characteristic is enhanced; furthermore, the density of the trench can be increased, and lower RSP can be obtained.
Description
Technical field
The present invention relates to the preparation of semiconductor device, particularly relate to a kind of preparation method dividing grid-type groove MOSFET.
Background technology
For the semiconductor device be usually used in power electronic system and power management, power metal oxide semiconductor field-effect transistor MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), or isolated-gate field effect transistor (IGFET), extensively introduced.
Groove type power MOS FET is efficient, the device for power switching that new development is got up after MOSFET, and it adopts groove type grid structure field effect transistor, and it is high by (>=10 that it not only inherits metal-oxide-semiconductor field effect transistor input impedance
8Ω), the advantage of drive current little (0.1 μ about A), good characteristics such as also there is withstand voltage height, operating current is large, power output is high, transconductance linearity is good, switching speed is fast.Roll into one just because of its advantage by electron tube and power transistor, therefore in the circuit such as Switching Power Supply, inverter, voltage amplifier, power amplifier, obtain extensive use.Therefore, high-breakdown-voltage, big current, low on-resistance are the most key indexs of power MOSFET.
At present, the structure of power groove MOS device has been applicable in the application of most of power MOSFET, and the one dimension of the characteristic of device constantly close to silicon materials limits (theory relation describing puncture voltage when device drift region specific on-resistance and OFF state).Reduce the proposition of surface field Reduced Surface Field (RESURF) technology, puncture voltage can be made to be the one dimension restriction that the power groove MOS device of 600V exceedes silicon materials.Division grid-type groove Split-Gate Trench MOS device structure, can exceed the one dimension restriction of silicon materials under the low pressure of about the 30V of scaled down.Therefore, division grid-type groove MOS device, in low, middle pressure (20 ~ 200V) scope, has lower forward conduction resistance, occupies obvious advantage.
But the groove of existing division grid-type groove MOSFET be all upper wider, bottom is narrower, this will cause the area in source region little, and avalanche characteristic is low, and in the device of this structure, the density of groove is also low, R
sPhigher.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of preparation method dividing grid-type groove MOSFET, little for solving source contact area in the device prepared in prior art, the problems such as snowslide poor performance, groove density are low.
For achieving the above object and other relevant objects, the invention provides a kind of preparation method dividing grid-type groove MOSFET, described preparation method at least comprises:
1) substrate is provided, grows an epitaxial loayer at described substrate surface;
2) etch described epitaxial loayer, form the groove with first degree of depth, at described flute surfaces deposition of nitride layer, erode the nitride layer of channel bottom afterwards, retain the nitride layer of sidewall;
3) continue epitaxial film materials to the second degree of depth of the described channel bottom of etching, and thermally grown oxide layer is attached to the trenched side-wall and bottom that are not covered by nitride layer;
4) fill the first electric conducting material at described lower trench, remove the nitride layer on sidewall, make one deck separator at described first conductive material surface;
5) grow gate oxide, be covered on the exposed sidewall in groove top, and fill full second electric conducting material on groove top, form up-narrow and down-wide division grid-type groove MOSFET.
Divide the scheme of a kind of optimization of the preparation method of grid-type groove MOSFET as the present invention, the scope of described first degree of depth is 0.8 ~ 2 μm.
Divide the scheme of a kind of optimization of the preparation method of grid-type groove MOSFET as the present invention, described nitride layer thickness scope is 800 ~ 1200 dusts.
Divide the scheme of a kind of optimization of the preparation method of grid-type groove MOSFET as the present invention, the scope of described second degree of depth is 2 ~ 5 μm.
Divide the scheme of a kind of optimization of the preparation method of grid-type groove MOSFET as the present invention, described step 3) in the thickness of oxide skin(coating) be 3000 ~ 6000 dusts.
The scheme of a kind of optimization of the preparation method of grid-type groove MOSFET is divided as the present invention, described step 4) in, comprise step: the first electric conducting material of deposition, cover epi-layer surface, and be filled in groove, return and carve below described first electric conducting material to epi-layer surface 1 ~ 2 μm, retain the first electric conducting material of lower trench, after removing the nitride layer on sidewall, deposit isolated material, return and carve isolated material to apart from the first electric conducting material upper surface 2000 ~ 3000 dust, form one deck separator.
Divide the scheme of a kind of optimization of the preparation method of grid-type groove MOSFET as the present invention, described first electric conducting material and the second electric conducting material are polysilicon.
Divide the scheme of a kind of optimization of the preparation method of grid-type groove MOSFET as the present invention, the material of described nitride layer is silicon nitride.
The scheme of a kind of optimization of the preparation method of grid-type groove MOSFET is divided as the present invention, described step 2) comprise step: form hard mask layer in described epi-layer surface, by hard mask layer etch described epitaxial loayer formed there is the groove of first degree of depth, afterwards in step 4) remove nitride layer while remove this hard mask layer.
As mentioned above, the preparation method of division grid-type groove MOSFET of the present invention, comprises step: 1) provide a substrate, grows an epitaxial loayer at described substrate surface; 2) etch described epitaxial loayer, form the groove with first degree of depth, at described flute surfaces deposition of nitride layer, erode the nitride layer of channel bottom afterwards, retain the nitride layer of sidewall; 3) continue epitaxial film materials to the second degree of depth of the described channel bottom of etching, and thermally grown oxide layer is attached to the trenched side-wall and bottom that are not covered by nitride layer; 4) fill the first electric conducting material at described lower trench, remove the nitride layer on sidewall, make one deck separator at described first conductive material surface; 5) grow gate oxide, be covered on the exposed sidewall in groove top, and fill full second electric conducting material on groove top, form up-narrow and down-wide division grid-type groove MOSFET.The device architecture utilizing preparation method of the present invention to prepare can obtain wider source region area, larger source contact hole, promotes avalanche characteristic, also contributes to increasing groove density, obtains lower R
sP.
Accompanying drawing explanation
Fig. 1 is the step 1 that the present invention divides the preparation method of grid-type groove MOSFET) structural representation that presents.
Fig. 2 ~ Fig. 4 is the step 2 that the present invention divides the preparation method of grid-type groove MOSFET) structural representation that presents.
Fig. 5 ~ Fig. 6 is the step 3 that the present invention divides the preparation method of grid-type groove MOSFET) structural representation that presents.
Fig. 7 ~ Figure 10 is the step 4 that the present invention divides the preparation method of grid-type groove MOSFET) structural representation that presents.
Figure 11 is the step 5 that the present invention divides the preparation method of grid-type groove MOSFET) structural representation that presents.
Element numbers explanation
101 substrates
102 epitaxial loayers
103 hard mask layers
104 grooves
105 nitride layers
106 oxide skin(coating)s
107 first electric conducting materials
108 isolated materials
109 gate oxides
110 second electric conducting materials
D1 first degree of depth
D2 second degree of depth
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
The invention provides a kind of preparation method dividing grid-type groove MOSFET, described preparation method at least comprises the following steps:
First step 1 is performed), refer to accompanying drawing 1, a substrate 101 is provided, at described substrate 101 superficial growth one epitaxial loayer 102.
Described substrate 101 can be a heavy doping N+ type substrate, and described epitaxial loayer 102 can for mixing the lighter lightly doped n-type epitaxial loayer of concentration, at described epitaxial loayer 102 surface deposition one deck hard mask layer 103.Described hard mask layer 103 can be silicon dioxide, does not limit at this.
Then step 2 is performed), refer to accompanying drawing 2 ~ Fig. 4, etch described epitaxial loayer 102, form the groove 104 with first degree of depth, at described groove 104 and hard mask layer surface deposition nitride layer 105, erode bottom groove 104 afterwards and the nitride layer 105 on hard mask layer surface, retain the nitride layer 105 of sidewall.
As shown in Figure 2, step 1 described in patterning) in hard mask layer 103, form opening, by this hard mask layer 103, adopt dry etch process to etch described epitaxial loayer 102, in epitaxial loayer 102, form multiple groove 104 with the first degree of depth D1.Described first degree of depth D1 can control within the scope of 0.8 ~ 2 μm.In the present embodiment, described first degree of depth D1 is 1 μm.
Again as shown in Figure 3, chemical vapor deposition method can be adopted at the sidewall of described groove 104, the nitride layer 105 that hard mask layer is surperficial and bottom deposit one deck is thin, this nitride layer 105 can be silicon nitride, certainly, also can be other suitable nitride materials.The thickness of this nitride layer 105 is 800 ~ 1200 dusts.In the present embodiment, the thickness of described nitride layer 105 elects 1000 dusts temporarily as.
Then as shown in Figure 4, adopt anisotropic etch mode, the nitride layer 105 of hard mask layer surface and groove 104 horizontal direction (bottom) is eroded, only retains the nitride layer 105 in vertical direction (sidewall).
Then step 3 is performed), refer to accompanying drawing 5 ~ Fig. 6, continue epitaxial loayer 102 material to the second degree of depth D2 bottom the described groove 104 of etching, and thermally grown oxide layer 106 is attached to the trenched side-wall and bottom that are not covered by nitride layer 105.
As shown in Figure 5, adopt dry etching mode to etch described channel bottom, etching depth D2 is preferably 2 ~ 5 μm.In the present embodiment, described second degree of depth D2 is 3 μm.
As shown in Figure 6, in the sidewall of groove and bottom by thermal oxidation technology grown oxide layer 106.It should be noted that, groove upper portion side wall, owing to there being the protection of nitride layer 105, cannot grow, therefore oxide skin(coating) 106 only grows the lower trench exposed, and eats into trenched side-wall certain thickness owing to being oxidized.The oxide skin(coating) 106 of growth is thicker, is preferably 3000 ~ 6000 dusts.In the present embodiment, the oxide skin(coating) 106 of growth is 5000 dusts.
Perform step 4 again), refer to Fig. 7 ~ Figure 10, fill the first electric conducting material 107 at described lower trench, remove the nitride layer 105 on sidewall, make one deck separator on described first electric conducting material 107 surface.
Such as, can by the method depositing first conductive material 107 of chemical vapour deposition (CVD), this electric conducting material can be polysilicon, also can be other any suitable electric conducting materials.As shown in Figure 7, the first electric conducting material 107 of deposition covers the surface of epitaxial loayer 102, is also filled in whole groove simultaneously.Then as shown in Figure 8, the method for dry method or wet etching can be adopted to go back to following 1 ~ 2 μm of electric conducting material 107 to epitaxial loayer 102 at quarter first surface, retain the first electric conducting material 107 of lower trench, remove the nitride layer 105 of groove upper portion side wall simultaneously.
Refer to Fig. 9 again, by method growth and depositing isolation material 108 to the groove top of chemical vapour deposition (CVD), such as, prepare silicon oxide layer, this isolated material 108 is also covered in epitaxial loayer 102 surface while filling full groove top.In fact, isolated material 108 and oxide skin(coating) 106 are analogs of same material, and when growing isolated material 108, the interface between isolated material 108 and the oxide skin(coating) 106 of lower trench sidewalls is almost fusion together, and interface is no longer obvious.Afterwards, as shown in Figure 10, return and carve isolated material to apart from the first electric conducting material upper surface 2000 ~ 3000 dust, form one deck separator.
Finally perform step 5), refer to accompanying drawing 11, growth gate oxide 109, is covered on the exposed sidewall in groove top, and fills full second electric conducting material 110 on groove top, forms up-narrow and down-wide division grid-type groove MOSFET.
Such as, grow thin gate oxide 109 by thermal oxidation process, now, gate oxide 109 covers on the exposed sidewall in groove top, is also covered on the surface of epitaxial loayer 102 simultaneously.Afterwards, can by the second electric conducting material 110 of chemical vapour deposition (CVD), this second electric conducting material 110 can be polysilicon.Second electric conducting material 110 is filled among the top of groove, is also covered in the surface of the gate oxide 109 on epitaxial loayer 102 surface simultaneously.Subsequently, by dry etching or wet-etching technology, the gate oxide on epitaxial loayer 102 surface and the second electric conducting material are removed, makes the surface of the upper surface of the second electric conducting material 110 in groove and epitaxial loayer 102 substantially flush.As can be seen from Figure 11, the division grid-type groove that prepared by the present invention has up-narrow and down-wide planform.Certainly, complete MOSFET element structure be formed, also need to carry out follow-up technique, such as carry out ion implantation in epi-layer surface and form body layer etc.Follow-up is Conventional process steps, and this is no longer going to repeat them.
In sum, the invention provides a kind of preparation method of division grid-type groove MOSFET, comprise step: 1) provide a substrate, grow an epitaxial loayer at described substrate surface; 2) etch described epitaxial loayer, form the groove with first degree of depth, at described flute surfaces deposition of nitride layer, erode the nitride layer of channel bottom afterwards, retain the nitride layer of sidewall; 3) continue epitaxial film materials to the second degree of depth of the described channel bottom of etching, and grown oxide layer is attached to the trenched side-wall and bottom that are not covered by nitride layer; 4) fill the first electric conducting material at described lower trench, remove the nitride layer on sidewall, make one deck separator at described first conductive material surface; 5) grow gate oxide, be covered on the exposed sidewall in groove top, and fill full second electric conducting material on groove top, form up-narrow and down-wide division grid-type groove MOSFET.The device architecture utilizing preparation method of the present invention to prepare can obtain wider source region area, larger source contact hole, promotes avalanche characteristic, also contributes to increasing groove density, obtains lower R
sP.
So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (9)
1. divide a preparation method for grid-type groove MOSFET, it is characterized in that, described preparation method at least comprises:
1) substrate is provided, grows an epitaxial loayer at described substrate surface;
2) etch described epitaxial loayer, form the groove with first degree of depth, at described flute surfaces deposition of nitride layer, erode the nitride layer of channel bottom afterwards, retain the nitride layer of sidewall;
3) continue epitaxial film materials to the second degree of depth of the described channel bottom of etching, and thermally grown oxide layer is attached to the trenched side-wall and bottom that are not covered by nitride layer;
4) fill the first electric conducting material at described lower trench, remove the nitride layer on sidewall, make one deck separator at described first conductive material surface;
5) grow gate oxide, be covered on the exposed sidewall in groove top, and fill full second electric conducting material on groove top, form up-narrow and down-wide division grid-type groove MOSFET.
2. the preparation method of division grid-type groove MOSFET according to claim 1, is characterized in that: the scope of described first degree of depth is 0.8 ~ 2 μm.
3. the preparation method of division grid-type groove MOSFET according to claim 1, is characterized in that: described nitride layer thickness scope is 800 ~ 1200 dusts.
4. the preparation method of division grid-type groove MOSFET according to claim 1, is characterized in that: the scope of described second degree of depth is 2 ~ 5 μm.
5. the preparation method of division grid-type groove MOSFET according to claim 1, is characterized in that: described step 3) in the thickness of oxide skin(coating) be 3000 ~ 6000 dusts.
6. the preparation method of division grid-type groove MOSFET according to claim 1, it is characterized in that: described step 4) in, comprise step: the first electric conducting material of deposition, cover epi-layer surface, and be filled in groove, return and carve below described first electric conducting material to epi-layer surface 1 ~ 2 μm, retain the first electric conducting material of lower trench, after removing the nitride layer on sidewall, deposit isolated material, return and carve isolated material to apart from the first electric conducting material upper surface 2000 ~ 3000 dust, form one deck separator.
7. the preparation method of division grid-type groove MOSFET according to claim 1, is characterized in that: described first electric conducting material and the second electric conducting material are polysilicon.
8. the preparation method of division grid-type groove MOSFET according to claim 1, is characterized in that: the material of described nitride layer is silicon nitride.
9. the preparation method of division grid-type groove MOSFET according to claim 1, it is characterized in that: described step 2) comprise step: form hard mask layer in described epi-layer surface, by hard mask layer etch described epitaxial loayer formed there is the groove of first degree of depth, afterwards in step 4) remove nitride layer while remove this hard mask layer.
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| CN107785426A (en) * | 2016-08-31 | 2018-03-09 | 无锡华润上华科技有限公司 | A kind of semiconductor devices and its manufacture method |
| CN109872950A (en) * | 2019-02-28 | 2019-06-11 | 北京燕东微电子科技有限公司 | A kind of manufacturing method of groove separation grate MOS device |
| WO2021082158A1 (en) * | 2019-10-28 | 2021-05-06 | 苏州东微半导体有限公司 | Semiconductor power device terminal structure |
| CN113053738A (en) * | 2019-12-27 | 2021-06-29 | 华润微电子（重庆）有限公司 | Split gate type groove MOS device and preparation method thereof |
| CN113838917A (en) * | 2021-09-23 | 2021-12-24 | 电子科技大学 | Three-dimensional split gate groove charge storage type IGBT and manufacturing method thereof |
| CN113838915A (en) * | 2021-09-23 | 2021-12-24 | 电子科技大学 | Trench gate charge storage type IGBT and manufacturing method thereof |
| WO2022082902A1 (en) * | 2020-10-20 | 2022-04-28 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107785426A (en) * | 2016-08-31 | 2018-03-09 | 无锡华润上华科技有限公司 | A kind of semiconductor devices and its manufacture method |
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| WO2022082902A1 (en) * | 2020-10-20 | 2022-04-28 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device |
| CN113838917A (en) * | 2021-09-23 | 2021-12-24 | 电子科技大学 | Three-dimensional split gate groove charge storage type IGBT and manufacturing method thereof |
| CN113838915A (en) * | 2021-09-23 | 2021-12-24 | 电子科技大学 | Trench gate charge storage type IGBT and manufacturing method thereof |
| CN113838915B (en) * | 2021-09-23 | 2023-03-28 | 电子科技大学 | Trench gate charge storage type IGBT and manufacturing method thereof |
| CN113838917B (en) * | 2021-09-23 | 2023-03-28 | 电子科技大学 | Three-dimensional separation gate groove charge storage type IGBT and manufacturing method thereof |
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