CN113053738A - Split gate type groove MOS device and preparation method thereof - Google Patents
Split gate type groove MOS device and preparation method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The invention provides a split gate type groove MOS device and a preparation method thereof, comprising the following steps: 1) providing a semiconductor substrate; 2) forming a plurality of grooves by using a first mask plate, forming a first oxidation layer, and depositing source electrode polycrystalline silicon in the grooves; 3) defining an active area and a terminal area by using a second mask plate, depositing a light resistance layer on the surface of the semiconductor substrate in the terminal area, etching the first oxidation layer, forming an opening in the groove, and removing the light resistance layer and the first oxidation layer; 4) forming a second oxide layer on the opening, and depositing grid polysilicon; 5) forming a body region in the semiconductor substrate, and forming a source region by using a third mask plate; 6) depositing a dielectric layer, and forming an electrode contact hole by using a fourth mask plate; 7) and depositing a metal layer, and separating the source electrode and the terminal electrode by using a fifth mask plate. The preparation method of the split-gate type groove MOS device provided by the invention simplifies the process by saving the photoetching process.
Description
Technical Field
The invention belongs to the technical field of information electronic materials and devices, and particularly relates to a split gate type groove MOS device and a preparation method thereof.
Background
The groove type power MOSFET is a high-efficiency and power switch device newly developed after the MOSFET, adopts a groove type grid structure field effect transistor, inherits the advantages of high input impedance and small driving current of the MOS field effect transistor, and has the excellent characteristics of high withstand voltage, large working current, high output power, good transconductance linearity, high switching speed and the like. The advantages of the electronic tube and the power transistor are integrated, so that the electronic tube and the power transistor are widely applied to circuits such as a switching power supply, an inverter, a voltage amplifier, a power amplifier and the like. Therefore, the power MOSFET with high breakdown voltage, large current and low conduction resistance wire has the most key indexes.
Currently, the structure of power MOS devices has been adapted for most power MOSFET applications, and the device characteristics are constantly approaching the one-dimensional limit of silicon materials. The proposal of the technology for reducing the surface electric field can enable the power trench MOS device with the breakdown voltage of 600V to exceed the one-dimensional limit of silicon materials. The split-gate trench MOS device structure can exceed the one-dimensional limit of silicon materials under the low pressure of about 30V which is reduced in equal proportion. Therefore, the split-gate trench MOS device has lower forward on-resistance in the low and medium voltage (20-200V) ranges, and has obvious advantages. However, the common split-gate trench MOS device has both source polysilicon and gate polysilicon, so the manufacturing process is more complicated and the number of layers of the photomask is more than that of the common trench MOS device.
Therefore, how to reduce the number of mask layers and simplify the process has become a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a split-gate trench MOS device and a method for manufacturing the same, which are used to solve the problems of the prior art that the process of manufacturing the split-gate trench MOS device is complicated and the number of mask layers is large.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a split-gate trench MOS device, including the steps of:
1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate base plate and an epitaxial layer positioned above the substrate base plate, and the semiconductor substrate is of a first doping type;
2) forming a plurality of grooves with first depth in the epitaxial layer by using a first mask plate, forming a first oxidation layer on the bottom surface and the side wall of the grooves and the surface of the semiconductor substrate, and depositing source polycrystalline silicon in the grooves to fill the grooves;
3) defining an active area and a terminal area by using a second mask plate, depositing a light resistance layer on the surface of the semiconductor substrate of the terminal area, sequentially etching source electrode polycrystalline silicon in a groove of the active area and the first oxidation layer positioned on the side wall of the groove and the surface of the semiconductor substrate, forming an opening with a second depth in the groove, and then removing the light resistance layer and the first oxidation layer on the surface of the semiconductor substrate, wherein the second depth is smaller than the first depth;
4) forming a second oxide layer on the side wall and the bottom surface of the opening and the surface of the semiconductor substrate, and depositing grid polysilicon to fill the opening;
5) performing ion implantation of a second doping type in a region of the semiconductor substrate adjacent to the upper part of the groove to form a body region, and performing ion implantation of a first doping type in the body region of the active region by using a third mask plate to form a source region with the first doping type, wherein the third mask plate shields the terminal region;
6) depositing a dielectric layer on the surface of the device formed in the step 5), and forming an electrode contact hole by using a fourth mask plate through an etching process;
7) depositing a metal layer on the surface of the device formed in the step 6), filling the electrode contact hole and covering the dielectric layer, and separating the source electrode and the terminal electrode by using a fifth mask plate).
Optionally, the method for manufacturing the split-gate trench MOS device further includes a step of performing surface passivation by using a sixth mask after the step 7).
Optionally, the second depth is 1/3-1/2 of the first depth.
Optionally, the specific process of step 2) includes:
2-1) forming a hard mask layer on the surface of the epitaxial layer;
2-2) etching the hard mask layer through a first mask plate to form a graphical hard mask layer;
2-3) continuing etching, and forming a plurality of grooves with first depth in the epitaxial layer;
2-4) forming a first oxidation layer on the bottom surface and the side wall of the groove and the surface of the semiconductor substrate;
2-5) depositing source polycrystalline silicon in the groove, wherein the groove is filled with the source polycrystalline silicon and the first oxidation layer is covered with the source polycrystalline silicon;
2-6) removing the source electrode polycrystalline silicon outside the groove by adopting a chemical mechanical planarization process.
Optionally, the specific process of step 3) includes:
3-1) defining an active area and a terminal area by using a second mask plate, and depositing a light resistance layer on the surface of the terminal area;
3-2) removing the source electrode polycrystalline silicon in the active area groove to a second depth by adopting a dry etching process;
3-2) removing the first oxide layer exposed on the side wall of the groove and the surface of the semiconductor substrate by adopting a wet etching process, and forming an opening with a second depth in the groove of the active region;
3-4) removing the photoresist layer and the first oxide layer on the surface of the semiconductor substrate.
Optionally, the specific process of step 4) includes:
4-1) forming a second oxide layer on the side wall and the bottom surface of the opening and the surface of the semiconductor substrate;
4-2) depositing grid polysilicon, wherein the grid polysilicon fills the opening and covers the second oxidation layer;
4-3) removing the grid polysilicon outside the groove, and etching the grid polysilicon in the active region groove and the source polysilicon in the terminal region groove until the grid polysilicon and the source polysilicon are flush with the surface of the semiconductor substrate.
Optionally, the first doping type is one of an N type or a P type, and the second doping type is the other of the N type or the P type.
The invention also provides a split gate type trench MOS device, comprising;
the semiconductor substrate comprises a substrate base plate and an epitaxial layer positioned above the substrate base plate, and the semiconductor substrate is of a first doping type; the semiconductor substrate comprises an active region and a terminal region, wherein the terminal region is positioned at the periphery of the active region;
the plurality of trench split gates are positioned in the active area and comprise upper trench split gate portions with second depths and lower trench split gate portions corresponding to the upper trench split gate portions, the upper trench split gate portions comprise gate polycrystalline silicon and second oxidation layers positioned on the side walls and the bottom face of the upper trench split gate portions, and the lower trench split gate portions comprise source polycrystalline silicon and first oxidation layers positioned on the side walls and the bottom face of the lower trench split gate portions;
the termination trench is positioned in the termination region and comprises source electrode polycrystalline silicon and a first oxidation layer positioned on the side wall and the bottom surface of the termination trench;
the body region is positioned in the epitaxial layer, is adjacent to the groove split gate and is terminated to the upper part of the groove, and is of a second doping type;
the source region is positioned in a body region of the active region and is of the first doping type; and
and the source electrode and the terminal electrode are respectively connected with the active region and the terminal region.
Optionally, the first doping type is one of an N type or a P type, and the second doping type is the other of the N type or the P type.
Optionally, the semiconductor substrate comprises a heavily doped substrate base plate and a lightly doped epitaxial layer located above the heavily doped substrate base plate.
Optionally, the thickness of the first oxide layer is greater than the thickness of the second oxide layer.
Optionally, the second depth is 1/3-1/2 of the first depth.
As described above, the split-gate trench MOS device and the method for manufacturing the same of the present invention have the following advantageous effects: when the source electrode polycrystalline silicon is etched back, both dry etching and wet etching are completed in the same photoetching process, so that the photoetching process is saved, and the process is simplified; when the body region injection is carried out, a masking layer is not needed, so that the photoetching process is saved, and the process is simplified.
Drawings
Fig. 1 shows a schematic flow chart of a method for manufacturing a split-gate trench MOS device according to the present invention.
Fig. 2 is a schematic structural view of a semiconductor substrate according to the present invention.
FIG. 3 is a schematic diagram of a hard mask layer formation structure according to the present invention.
Fig. 4 is a schematic structural view of a trench formed in a semiconductor substrate according to the present invention.
Fig. 5 is a schematic structural diagram illustrating the formation of the first oxide layer according to the present invention.
Fig. 6 is a schematic structural diagram illustrating the formation of source polysilicon according to the present invention.
Fig. 7 shows a schematic structural view of removing the source polysilicon outside the trench according to the present invention.
FIG. 8 is a schematic diagram of a structure for forming a photoresist layer according to the present invention.
Fig. 9 shows a schematic structural diagram of etching the source polysilicon in the trench of the active region according to the present invention.
Fig. 10 is a schematic structural diagram illustrating the formation of a trench opening according to the present invention.
FIG. 11 is a schematic structural view of the photoresist layer and the first oxide layer removed according to the present invention.
Fig. 12 is a schematic structural view illustrating formation of a second oxide layer according to the present invention.
Fig. 13 shows a schematic structural view of the gate polysilicon deposition provided by the present invention.
Fig. 14 shows a schematic structural diagram after etching the gate polysilicon provided by the present invention.
Fig. 15 is a schematic structural diagram illustrating the formation of a body region by performing ion implantation of a second doping type according to the present invention.
Fig. 16 is a schematic structural diagram illustrating a source region formed by performing ion implantation of a first doping type according to the present invention.
FIG. 17 is a schematic structural diagram of a deposited dielectric layer provided in the present invention.
FIG. 18 is a schematic view of the structure for forming electrode contact holes according to the present invention.
FIG. 19 is a schematic structural diagram of a deposited metal layer provided by the present invention.
Fig. 20 is a schematic structural view illustrating the formation of source and terminal electrodes according to the present invention.
Description of the element reference numerals
11 semiconductor substrate
111 substrate
112 epitaxial layer
113 hard mask layer
12 grooves
12a trench split gate
121a trench split gate upper portion
122a trench split gate lower portion
12b termination trench
13 first oxide layer
14 source polysilicon
15 photo resist layer
16 opening
17 second oxide layer
18 gate poly
19 body region
20 source region
21 dielectric layer
22 electrode contact hole
23 Metal layer
23a source electrode
23b terminal electrode
S1-S7
a active region
b terminal area
d1 first depth
d2 second depth
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 20. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
The embodiment provides a method for manufacturing a split-gate trench MOS device, as shown in fig. 1, the method at least includes the following steps:
1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate base plate and an epitaxial layer positioned above the substrate base plate, and the semiconductor substrate is of a first doping type;
2) forming a plurality of grooves with first depth in the epitaxial layer by using a first mask plate, forming a first oxidation layer on the bottom surface and the side wall of the grooves and the surface of the semiconductor substrate, and depositing source polycrystalline silicon in the grooves to fill the grooves;
3) defining an active area and a terminal area by using a second mask plate, depositing a light resistance layer on the surface of the semiconductor substrate of the terminal area, sequentially etching source electrode polycrystalline silicon in a groove of the active area and the first oxidation layer positioned on the side wall of the groove and the surface of the semiconductor substrate, forming an opening with a second depth in the groove, and then removing the light resistance layer and the first oxidation layer on the surface of the semiconductor substrate, wherein the second depth is smaller than the first depth;
4) forming a second oxide layer on the side wall and the bottom surface of the opening and the surface of the semiconductor substrate, and depositing grid polysilicon to fill the opening;
5) performing ion implantation of a second doping type in a region of the semiconductor substrate adjacent to the upper part of the groove to form a body region, and performing ion implantation of a first doping type in the body region of the active region by using a third mask plate to form a source region with the first doping type, wherein the third mask plate shields the terminal region;
6) depositing a dielectric layer on the surface of the device formed in the step 5), and forming an electrode contact hole by using a fourth mask plate through an etching process;
7) depositing a metal layer on the surface of the device formed in the step 6), filling the electrode contact hole and covering the dielectric layer, and separating the source electrode and the terminal electrode by using a fifth mask plate.
The following describes the method for manufacturing the split-gate trench MOS device provided by the present invention in detail with reference to the accompanying drawings.
Step 1) is performed, as shown in fig. 2, a semiconductor substrate 11 is provided, which includes a substrate base 111 and an epitaxial layer 112 located above the substrate base, wherein the semiconductor substrate 11 is of a first doping type.
As an example, as shown in fig. 2, the semiconductor substrate 11 may be a heavily doped substrate base plate 111 of the first doping type and a lightly doped epitaxial layer 112 of the first doping type over the heavily doped substrate base plate 111. The first doping type may be one of N-type or P-type. In the present embodiment, the semiconductor substrate 11 has a structure of a heavily doped N + type substrate base 111 and a lightly doped N type epitaxial layer 112 with a lower doping concentration on the heavily doped N + type substrate base.
Step 2) is performed, as shown in fig. 3 to 7, a plurality of trenches 12 with a first depth d1 are formed in the epitaxial layer 112 by using a first mask, a first oxide layer 13 is formed on the bottom and the sidewall of the trenches 12 and the surface of the semiconductor substrate 11, and source polysilicon 14 is deposited in the trenches 12 to fill the trenches 12.
Specifically, the step 2) comprises the following steps:
2-1) forming a hard mask layer 113 on the surface of the epitaxial layer, as shown in fig. 3;
2-2) etching the hard mask layer 113 through a first mask plate to form a patterned hard mask layer 113;
2-3) continuing to etch, and forming a plurality of trenches 12 with a first depth d1 in the epitaxial layer 111, as shown in fig. 4;
2-4) removing the hard mask layer 103, and forming a first oxide layer 13 on the bottom surface and the side wall of the trench 12 and the surface of the semiconductor substrate 11, as shown in fig. 5;
2-5) depositing a source polysilicon 14, wherein the source polysilicon 14 fills the trench 12 and covers the first oxide layer 13, as shown in fig. 6;
2-6) removing the source polysilicon 14 outside the trench 12 using a chemical mechanical planarization process, as shown in fig. 7.
As an example, as shown in fig. 3, the material of the hard mask layer 113 may be silicon dioxide, which is not limited herein.
As an example, as shown in fig. 5, the method of forming the first oxide layer 13 includes a thermal oxidation process, a chemical vapor deposition process, a plasma chemical vapor deposition process, or the like, and in the present embodiment, the first oxide layer 13 is formed by a thermal oxidation process, and the temperature of the thermal oxidation is, for example, 900 ℃ to 1300 ℃.
As an example, as shown in fig. 6, when depositing the source polysilicon 14, the source polysilicon may be formed by one or more depositions, in which the rate of the subsequent deposition step is less than the previous deposition step, so that the deposition rate gradually decreases. In the trench filling process, the slower the deposition rate, the better the filling effect, the more difficult the trench bottom filling is than the trench top filling, so that in the case of multiple filling, the deposition rate of the front side needs to be less than that of any subsequent deposition.
And step 3) is executed, as shown in fig. 8 to 11, an active region a and a terminal region b are defined by using a second mask, a photoresist layer 15 is deposited on the surface of the terminal region b, the source polysilicon 14 in the trench 12 of the active region a and the first oxide layer 13 on the sidewall of the trench 12 and the surface of the semiconductor substrate 11 are sequentially etched, an opening 16 with a second depth d2 is formed in the trench 12, and then the photoresist layer 15 and the first oxide layer 13 on the surface of the semiconductor substrate are removed, wherein the second depth d is smaller than the first depth d 1.
Specifically, the step 3) comprises the following steps:
3-1) defining an active area a and a terminal area b by using a second mask plate, and depositing a photoresist layer 15 on the surface of the terminal area, as shown in fig. 8;
3-2) etching the source polysilicon 14 inside the trench 12 of the active area a to a second depth d2 by using a dry etching process, as shown in fig. 9;
3-3) removing the first oxide layer 13 exposed on the side wall of the trench 12 and the surface of the semiconductor substrate 11 by using a wet etching process, and forming an opening 16 with a second depth d2 in the active region trench, as shown in fig. 10;
3-4) removing the photoresist layer 15 and the first oxide layer 13 on the surface of the semiconductor substrate, as shown in fig. 11.
As an example, in the present embodiment, the step 3) employs a two-step etching method, the first step employs dry etching to remove the source polysilicon 14 with respect to the first oxide layer 13, and etch the source polysilicon 14 to the second depth d 2; in a first step, wet etching is used to remove the exposed trench sidewalls and the first oxide layer 13 on the semiconductor substrate with respect to the source polysilicon 14, and an opening 16 with a depth d2 is formed in the active region trench 12. In this embodiment, the same PHOTO process is adopted, so that the source polysilicon 14 is removed by dry etching, the first oxide layer 13 is removed by wet etching, one PHOTO process is saved, and the process flow is simplified.
As an example, as shown in FIG. 10, the second depth d2 is 1/3-1/2 of the first depth d1, i.e., 1/3-1/2 of the opening depth and the trench depth.
And 4) performing step 4), as shown in fig. 12 to 14, forming a second oxide layer 17 on the side wall and the bottom surface of the opening and the surface of the semiconductor substrate, and depositing gate polysilicon 18 to fill the opening 16.
Specifically, the step 4) comprises the following steps:
4-1) and forming a second oxide layer 17 on the sidewall and the bottom surface of the opening 16 and the surface of the semiconductor substrate 11, as shown in fig. 12;
4-2) depositing a gate polysilicon 18, said gate polysilicon 18 filling said opening 16 and covering said second oxide layer 17, as shown in fig. 13;
4-3) etch to remove the gate polysilicon 18 outside the trench 12 and the second oxide layer of the termination region so that the polysilicon in the trench is level with the epitaxial layer, as shown in fig. 14.
As an example, as shown in fig. 12, the method of forming the second oxide layer 17 includes a process such as thermal oxidation, chemical vapor deposition, or plasma chemical vapor deposition, and in the present embodiment, the second oxide layer 17 is formed by a thermal oxidation method, and the temperature of the thermal oxidation is, for example, 900 ℃ to 1300 ℃.
As an example, the thickness of the second oxide layer 17 is smaller than the thickness of the first oxide layer 13.
As an example, as shown in fig. 13, when depositing the gate polysilicon 18, the gate polysilicon may be formed using one or more depositions, where the rate of subsequent deposition steps is less than the previous deposition step, such that the deposition rate gradually decreases. In the trench filling process, the slower the deposition rate, the better the filling effect, the more difficult the trench bottom filling is than the trench top filling, so that in the case of multiple filling, the deposition rate of the front side needs to be less than that of any subsequent deposition.
Step 5) is executed, as shown in fig. 15 to 16, ion implantation of the second doping type is performed in the region of the semiconductor substrate adjacent to the trench to form a body region 19, and ion implantation of the first doping type is performed in the body region of the active region by using a third mask plate to form a source region 20 having the first doping type, wherein the fourth mask plate shields the terminal region.
As an example, the first doping type is one of an N-type and a P-type, and the second doping type is the other of the N-type and the P-type. In this embodiment, the first doping type is N-type, and the second doping type is P-type. The implantation depth of the body and source regions may be defined by the energy of the ion implantation.
By way of example, in forming body region 19, the dopant employed is B11 or BF2Alternatively, the implantation of B11 may be performed first and then BF may be performed2The implantation energy is 20-100 Kev, the implantation dose is 1E 14-1E 16, and the thermal annealing temperature is 500-1000 ℃. When the source region 20 is formed, the adopted dopant is P + or AS +, the implantation energy is 60-150 Kev, the implantation dose is 1E 14-1E 16, and the thermal annealing temperature is 800-1100 ℃.
It should be noted that, in the ordinary MOS structure, a termination voltage ring needs to be formed at the periphery. It is necessary to have a pattern at the termination for masking during the implantation. The split gate MOS is isolated by a groove at the periphery, so that a PN junction is not required to be used as a voltage-resistant isolation. Thereby eliminating a PHOTO process. So that the process flow is simplified.
And 6) performing step 6), as shown in fig. 17-18, depositing a dielectric layer deposition dielectric layer 21 on the surface of the device formed in the step 5), and forming an electrode contact hole 22 by using a fourth mask plate and adopting an etching process.
As an example, the material of the dielectric layer 21 may be at least one of silicon dioxide, silicon nitride, and silicon oxynitride, or may be a plurality of materials to form a stacked structure. In the embodiment, the dielectric layer is a stacked structure of Undoped Silicate Glass (USG) and borophosphosilicate glass (BPSG).
As an example, the electrode contact hole 22 is formed using a dry etching process, and the sidewall of the electrode contact hole 22 is inclined such that the bottom width of the electrode contact hole 22 is smaller than the top width. The electrode contact hole 22 is inclined at an angle, so that the subsequent filling of a conductive material is facilitated, and the problems of defects and the like caused by gap filling are reduced.
And 7) performing step 7), as shown in fig. 19 to 20, depositing a metal layer 23 on the surface of the device formed in step 6), filling the electrode contact hole 22 and covering the dielectric layer 21, and separating the source electrode 23a and the terminal electrode 23b by using a fifth mask.
For example, the material of the metal layer 23 may be any one of Ti, TiN, TiSi, W, Al, and Ni, or an alloy thereof. A metal layer 23 is deposited and patterned to form a source electrode 23a and a terminal electrode 23b, as shown in fig. 20, the source electrode 23a and the terminal electrode 23b being isolated from each other.
After the step 7), metallization of the split-gate trench MOS device is already achieved, and further, according to the product requirement, passivation layer protection can be added through a sixth mask plate, so that the processing of the front surface structure of the power semiconductor device is completed. And finally realizing the split gate type groove MOS device through a series of subsequent processes such as thinning, back gold, scribing and the like.
By the method for the split-gate type groove MOS device, when the polysilicon of the source electrode is etched back, both dry etching and wet etching are completed in the same photoetching process, so that the photoetching process is saved, and the process is simplified; when the body region injection is carried out, a masking layer is not needed, so that the photoetching process is saved, and the process is simplified.
Example two
The present embodiment provides a split-gate trench MOS device, as shown in fig. 20, including:
a semiconductor substrate 11 comprising a substrate base plate 111 and an epitaxial layer 112 located above the substrate base plate 11, the semiconductor substrate 11 being of a first doping type; the semiconductor substrate 11 comprises an active region a and a termination region b, wherein the termination region b is positioned at the periphery of the active region a;
the plurality of trench split gates 12a are located in the active region a, and include a trench split gate upper portion 121a having a second depth d2 and a trench split gate lower portion 122a corresponding to the trench split gate upper portion, the trench split gate upper portion includes gate polysilicon 18 and a second oxide layer 17 located on sidewalls and a bottom surface of the trench split gate upper portion, and the trench split gate lower portion includes source polysilicon 14 and a first oxide layer 13 located on sidewalls and a bottom surface of the trench split gate lower portion;
a termination trench 12b in the termination region b, including source polysilicon 14 and a first oxide layer 13 on sidewalls and a bottom surface of the termination trench 12 b;
a body region 19 located in the epitaxial layer, wherein the body region 19 is adjacent to the trench split gate 12a and the upper part of the termination trench 12b, and is of a second doping type;
a source region 20 located in the body region 20 of the active region a, wherein the source region 20 is of the first doping type; and
and a source electrode 23a and a terminal electrode 23b connected to the active region a and the terminal region b, respectively.
As an example, the first doping type is one of an N-type or a P-type, and the second doping type is the other of an N-type or a P-type.
As an example, the semiconductor substrate 11 may be a heavily doped substrate base 111 of the first doping type and a lightly doped epitaxial layer 112 of the first doping type over the heavily doped substrate base 111. The first doping type may be one of N-type or P-type. In the present embodiment, the semiconductor substrate 11 has a structure of a heavily doped N + type substrate base and a lightly doped N type epitaxial layer 112 with a lower doping concentration on the heavily doped N + type substrate base.
As an example, the thickness of the first oxide layer 13 is greater than the thickness of the second oxide layer 17.
By way of example, the second depth d2 is 1/3-1/2 of the first depth d 1.
In summary, the present invention provides a split-gate trench MOS device and a method for manufacturing the same, where the method for manufacturing the split-gate trench MOS device includes: 1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate base plate and an epitaxial layer positioned above the substrate base plate, and the semiconductor substrate is of a first doping type; 2) forming a plurality of grooves with first depth in the epitaxial layer by using a first mask plate, forming a first oxidation layer on the bottom surface and the side wall of the grooves and the surface of the semiconductor substrate, and depositing source polycrystalline silicon in the grooves to fill the grooves; 3) defining an active area and a terminal area by using a second mask plate, depositing a light resistance layer on the surface of the semiconductor substrate of the terminal area, sequentially etching source electrode polycrystalline silicon in a groove of the active area and the first oxidation layer positioned on the side wall of the groove and the surface of the semiconductor substrate, forming an opening with a second depth in the groove, and then removing the light resistance layer and the first oxidation layer on the surface of the semiconductor substrate, wherein the second depth is smaller than the first depth; 4) forming a second oxide layer on the side wall and the bottom surface of the opening and the surface of the semiconductor substrate, and depositing grid polysilicon to fill the opening; 5) performing ion implantation of a second doping type in a region of the semiconductor substrate adjacent to the upper part of the groove to form a body region, and performing ion implantation of a first doping type in the body region of the active region by using a third mask plate to form a source region with the first doping type, wherein the third mask plate shields the terminal region; 6) depositing a dielectric layer on the surface of the device formed in the step 5), and forming an electrode contact hole by using a fourth mask plate through an etching process; 7) depositing a metal layer on the surface of the device formed in the step 6), filling the electrode contact hole and covering the dielectric layer, and separating the source electrode and the terminal electrode by using a fifth mask plate. The preparation method of the split-gate type groove MOS device provided by the invention simplifies the process flow as much as possible under the condition of ensuring that the electrical property of the product is not changed. Under the condition that the domestic continuous demand of the split-gate type groove MOS device is large at present, the simplification of the process flow also reduces the manufacturing cost of the product and improves the competitiveness.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A preparation method of a split gate type groove MOS device is characterized by at least comprising the following steps:
1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate base plate and an epitaxial layer positioned above the substrate base plate, and the semiconductor substrate is of a first doping type;
2) forming a plurality of grooves with first depth in the epitaxial layer by using a first mask plate, forming a first oxidation layer on the bottom surface and the side wall of the grooves and the surface of the semiconductor substrate, and depositing source polycrystalline silicon in the grooves to fill the grooves;
3) defining an active area and a terminal area by using a second mask plate, depositing a light resistance layer on the surface of the semiconductor substrate of the terminal area, sequentially etching source electrode polycrystalline silicon in a groove of the active area and the first oxidation layer positioned on the side wall of the groove and the surface of the semiconductor substrate, forming an opening with a second depth in the groove, and then removing the light resistance layer and the first oxidation layer on the surface of the semiconductor substrate, wherein the second depth is smaller than the first depth;
4) forming a second oxide layer on the side wall and the bottom surface of the opening and the surface of the semiconductor substrate, and depositing grid polysilicon to fill the opening;
5) performing ion implantation of a second doping type in a region of the semiconductor substrate adjacent to the upper part of the groove to form a body region, and performing ion implantation of a first doping type in the body region of the active region by using a third mask plate to form a source region with the first doping type, wherein the third mask plate shields the terminal region;
6) depositing a dielectric layer on the surface of the device formed in the step 5), and forming an electrode contact hole by using a fourth mask plate through an etching process;
7) depositing a metal layer on the surface of the device formed in the step 6), filling the electrode contact hole and covering the dielectric layer, and separating the source electrode and the terminal electrode by using a fifth mask plate.
2. The method for manufacturing a split-gate trench MOS device according to claim 1, further comprising a step of performing surface passivation using a sixth mask after the step 7).
3. The method of claim 1, wherein the second depth is 1/3-1/2 of the first depth.
4. The method for preparing the split-gate trench MOS device according to claim 1, wherein the specific process of the step 2) comprises:
2-1) forming a hard mask layer on the surface of the epitaxial layer;
2-2) etching the hard mask layer through a first mask plate to form a graphical hard mask layer;
2-3) continuing etching, and forming a plurality of grooves with first depth in the epitaxial layer;
2-4) forming a first oxidation layer on the bottom surface and the side wall of the groove and the surface of the semiconductor substrate;
2-5) depositing source polycrystalline silicon in the groove, wherein the groove is filled with the source polycrystalline silicon and the first oxidation layer is covered with the source polycrystalline silicon;
2-6) removing the source electrode polycrystalline silicon outside the groove by adopting a chemical mechanical planarization process.
5. The method for preparing the split-gate trench MOS device according to claim 1, wherein the specific process of the step 3) comprises:
3-1) defining an active area and a terminal area by using a second mask plate, and depositing a light resistance layer on the surface of the terminal area;
3-2) removing the source electrode polycrystalline silicon in the active area groove to a second depth by adopting a dry etching process;
3-3) removing the first oxide layer exposed on the side wall of the groove and the surface of the semiconductor substrate by adopting a wet etching process, and forming an opening with a second depth in the groove of the active region;
3-4) removing the photoresist layer and the first oxide layer on the surface of the semiconductor substrate.
6. The method for preparing the split-gate trench MOS device according to claim 1, wherein the specific process of the step 4 includes:
4-1) forming a second oxide layer on the side wall and the bottom surface of the opening and the surface of the semiconductor substrate;
4-2) depositing grid polysilicon, wherein the grid polysilicon fills the opening and covers the second oxidation layer;
4-3) removing the grid polysilicon outside the groove, and etching the grid polysilicon in the active region groove and the source polysilicon in the terminal region groove until the grid polysilicon and the source polysilicon are flush with the surface of the semiconductor substrate.
7. The method of claim 1, wherein the semiconductor substrate comprises a heavily doped substrate base plate and a lightly doped epitaxial layer over the heavily doped substrate base plate.
8. The method of claim 1-7, wherein the first doping type is one of N-type or P-type, and the second doping type is the other of N-type or P-type.
9. A split gate trench MOS device, comprising;
the semiconductor substrate comprises a substrate base plate and an epitaxial layer positioned above the substrate base plate, and the semiconductor substrate is of a first doping type; the epitaxial layer comprises an active region and a terminal region, and the terminal region is positioned at the periphery of the active region;
the plurality of trench split gates are positioned in the active area and comprise upper trench split gate portions with second depths and lower trench split gate portions corresponding to the upper trench split gate portions, the upper trench split gate portions comprise gate polycrystalline silicon and second oxidation layers positioned on the side walls and the bottom face of the upper trench split gate portions, and the lower trench split gate portions comprise source polycrystalline silicon and first oxidation layers positioned on the side walls and the bottom face of the lower trench split gate portions;
the termination trench is positioned in the termination region and comprises source electrode polycrystalline silicon and a first oxidation layer positioned on the side wall and the bottom surface of the termination trench;
the body region is positioned in the epitaxial layer, is adjacent to the groove split gate and is terminated to the upper part of the groove, and is of a second doping type;
the source region is positioned in a body region of the active region and is of the first doping type; and
and the source electrode and the terminal electrode are respectively connected with the active region and the terminal region.
10. The split-gate trench MOS device of claim 9, wherein the first doping type is one of N-type or P-type and the second doping type is the other of N-type or P-type.
11. The split-gate trench MOS device of claim 9, wherein the semiconductor substrate comprises a heavily doped substrate base plate and a lightly doped epitaxial layer over the heavily doped substrate base plate.
12. The split-gate trench MOS device of claim 9, wherein a thickness of the first oxide layer is greater than a thickness of the second oxide layer.
13. The split-gate trench MOS device of claim 9, wherein the second depth is 1/3 to 1/2 of the first depth.
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