CN210628318U

CN210628318U - Split Gate-IGBT structure and device

Info

Publication number: CN210628318U
Application number: CN201921743997.4U
Authority: CN
Inventors: 徐守一; 陈思凡; 蔡铭进
Original assignee: Xiamen Xindamao Microelectronics Co ltd
Current assignee: Xiamen Xindamao Microelectronics Co ltd
Priority date: 2019-10-17
Filing date: 2019-10-17
Publication date: 2020-05-26
Anticipated expiration: 2029-10-17

Abstract

The utility model provides a Split Gate-IGBT structure and a device, wherein the Split Gate-IGBT structure comprises a Split Gate structure and a Trench Gate structure; one or more Trench Gate structures are arranged between the Split Gate structures. The utility model provides a Split Gate-IGBT structure, through set up one or more Trench Gate structures in the middle of the Split Gate structure, when possessing faster switching speed, still can further improve device cell density, reduce the saturation pressure drop; meanwhile, the switching performance of the IGBT is optimized by conveniently controlling the number of the Trench gates. The utility model provides a device in addition, but wide application in fields such as industry heating, converter, lighting circuit, new energy automobile.

Description

Split Gate-IGBT structure and device

Technical Field

The utility model relates to a semiconductor power device field, in particular to Split Gate-IGBT structure and device.

Background

An IGBT (insulated gate bipolar transistor) is a composite fully-controlled-voltage-driven-power semiconductor device composed of BJT (bipolar junction transistor) and MOS (insulated gate field effect transistor), and has the advantages of high input impedance and low conduction voltage drop. Its basic function can be seen simply as a non-on-off switch. The converter is widely applied to converter systems with direct-current voltage of 600V or more, such as alternating-current motors, inverters, lighting circuits, traction drives and the like. However, the IGBT is currently generally applied to a Trench Gate (Trench Gate) structure, which forms a compact cell distribution due to a vertical conductive channel, but the switching speed of the device is relatively low due to the capacitance between the Trench Gate and the substrate and between the underlying drift regions.

Split Gate structures are currently used in MOSFETs (metal oxide semiconductor field effect transistors) and have the characteristics of enabling MOSFETs to have faster switching speeds, higher breakdown voltages and lower on-resistances. The application of Split Gate structure to IGBT (insulated Gate bipolar transistor) also makes it possible to have faster switching speed. However, in order to reduce the output capacitance and ensure the reliability of the lower oxide layer, the split gate structure generally has a thicker insulating medium around the lower polysilicon field plate, and since the higher aspect ratio of the trench is limited by the process conditions during etching and filling, the width of the lower polysilicon field plate cannot be small, which limits the cell size due to the process conditions and the reliability of the device dielectric layer, thereby limiting the cell density of the device.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems mentioned in the background art, the utility model provides a Split Gate-IGBT structure and a device, wherein, the Split Gate-IGBT structure comprises a Split Gate structure and a Trench Gate structure; one or more Trench Gate structures are arranged between the SplitGate structures;

the second Trench depth d2 of the Split Gate structure is greater than the first Trench depth d1 of the Trench Gate structure;

a first oxide layer and first polycrystalline silicon are arranged at the bottom of a second groove of the Split Gate structure from outside to inside; gate oxide layers are arranged in the first oxide layer, the second grooves in the first polycrystalline silicon and the first grooves in the Trench Gate structures; and a second polycrystalline silicon layer is arranged on the gate oxide layer.

Furthermore, a PW area, an N + emission area, an ILD area, a Metal area and a passivation area are sequentially connected to the Split Gate structure and the Trench Gate structure.

Furthermore, a structure for reducing grid charge is arranged on the Split Gate structure.

Further, the gate charge reduction structure includes a third trench; and the third groove is arranged between two ends of the SplitGate structure and the connection of the emitting electrode.

The utility model provides a device in addition, adopt as above arbitrary the Split Gate-IGBT structure.

The utility model provides a Split Gate-IGBT structure, through set up one or more Trench Gate structures in the middle of the Split Gate structure, combine the advantage of the two, when possessing faster switching speed, still can further improve device cell density, reduce the saturation pressure drop; in addition, the switching performance of the IGBT can be optimized by controlling the number of the Trench gates. The utility model provides a device in addition, but wide application in fields such as industry heating, converter, lighting circuit, new energy automobile.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a first trench, a first trench and a third trench;

FIG. 2 is a schematic structural view of a first trench, a first trench and a third trench with polysilicon on the bottom;

FIG. 3 is a diagram of an embodiment of a Split Gate-IGBT structure provided by the present invention;

fig. 4 is a diagram of another embodiment of the Split Gate-IGBT structure provided by the present invention.

Reference numerals:

10 first trench 20 second trench 30 third trench

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The terms "couple" or "couples" and the like are not restricted to physical or mechanical connections, but may include electrical connections, optical connections, and the like, whether direct or indirect.

The embodiment of the utility model provides a Split Gate-IGBT structure and device, wherein, the Split Gate-IGBT structure, including Split Gate structure, Trench Gate structure; one or more Trench Gate structures are arranged between the Split Gate structures.

In specific implementation, as shown in fig. 1, fig. 2, fig. 3 and fig. 4, the Split Gate-IGBT structure includes a Split Gate structure and a Trench Gate structure; one (shown in figure 3) or a plurality of (shown in figure 4) Trench Gate structures are arranged between the Split Gate structures; the purpose of reducing the cell density is achieved by two different structures. And under the same area, the smaller the number of the Trench Gate structures is, the more the number of the Split Gate structures is, and the faster the switching speed is, so that the purpose of optimizing the switching performance of the IGBT can be achieved by adjusting according to actual requirements.

A first oxide layer and first polycrystalline silicon are arranged at the bottom of the second groove 20 of the Split Gate structure from outside to inside; gate oxide layers are arranged in the first oxide layer, the second groove 20 on the first polycrystalline silicon and the first groove 10 of the Trench Gate structure; a second polycrystalline silicon layer is arranged on the gate oxide layer; the Split Gate structure and the Trench Gate structure are sequentially connected with a PW area, an N + emission area, an ILD area, a Metal area and a passivation area.

The utility model provides a Split Gate-IGBT structure, through set up one or more Trench Gate structures in the middle of the Split Gate structure, combine the advantage of the two, when possessing faster switching speed, still can further improve device cell density, reduce the saturation pressure drop; in addition, the switching performance of the IGBT can be optimized by controlling the number of the Trench gates.

Preferably, the second Trench 20 depth d2 of the Split Gate structure is greater than the first Trench 10 depth d1 of the Trench Gate structure; in the present embodiment, the cell density is reduced by the structure in which the depths of the first trench and the second trench are not the same.

Preferably, a structure for reducing grid charge is arranged on the Split Gate structure. In particular implementation, the reducing gate charge includes a third trench 30; the third trench 30 is provided with front and rear ends of the second recess 20 (separated from the second trench 20 for convenience of description and understanding of the reader), and the poly at the bottom of the second trench is connected to the source through the third trench 30 to reduce Qgd (gate charge). The third trench 30 is provided with a first oxide layer and a first polysilicon layer from outside to inside.

The utility model discloses the device that provides in addition adopts as above wantonly Split Gate-IGBT structure, but wide application in fields such as industrial heating, converter, lighting circuit, new energy automobile.

The utility model discloses still provide the preparation method of the Split Gate-IGBT structure as above arbitrary, preparation method specifically as follows:

s10, forming a Guard Ring (Guard Ring) pattern on the front surface of the wafer with the N-concentration of 7E13 through photoetching, implanting B11/130Kev/8E12, and then annealing at a high temperature of 1175C/80min to form the Guard Ring (Guard Ring); removing the photoresist after forming a guard ring (GuardRing), growing an Oxide layer Field Oxide with the thickness of 0.5-1.5 mu m on the surface, and reserving part of the Oxide layer Field Oxide through photoetching; preferably, the thickness of the Oxide layer Field Oxide is 1 μm;

s20, growing an Oxide layer on the surface of the whole wafer, wherein the surface of the whole wafer comprises a Field Oxide surface and a silicon surface, and removing the Oxide and the wafer through photoetching to form a first groove 10 serving as a Trench Gate (the depth is d 1);

s30, etching after covering a part of the first groove 10 through the photoresist PR to form a second groove 20 and a third groove 30; the second trench 20 acts as a Split Gate (depth d 2); the structure of the cell region is shown in fig. 1 (for the convenience of observing and understanding the device structure, the groove part where the two ends of the Split Gate are connected with the emitter is taken as a third groove 30 in the figure, and actually, the position of the third groove 30 in the cross section is coincident with the second groove 20); after the second trench 20 and the third trench 30 are etched, removing the photoresist and the rest of all oxide layers;

s40, depositing an oxide layer (with a thickness of 4000A) and polysilicon in the first trench 10, the second trench 20 and the third trench 30, and then etching the polysilicon in the first trench 10, the second trench 20 and the third trench 30 to a P1 position as shown in fig. 2; continuing to etch the polysilicon in the first trench 10 and the second trench 20 to the position P2 as shown in fig. 2 by covering the third trench 30 with photoresist, so that the polysilicon in the first trench 10 is completely removed; then removing the photoresist covering the third trench 30, and etching to remove the oxide layer on the third trench 30;

s50, growing a gate oxide layer (with a thickness of 1000A) on the polysilicon in the first trench 10 and the second trench 20; depositing polycrystalline silicon on the gate oxide layer; after the polysilicon deposition is completed, photoetching and etching part of the polysilicon to a position P1 shown in FIG. 2 as a grid;

s60, implanting B11/40Kev/1.4E13, B11/90Kev/1.1E13 and B11/120Kev/1.4E13 on the surface of the wafer provided with the grid, and then annealing at high temperature of 11750C/80min to form a P well PW region; performing photoetching implantation on the PW region with As75/60Kev/8E15, and then annealing at a high temperature of 950C/30min to form an N + emitting region; growing an ILD layer with the thickness of 0.2-0.6 μm on the surface of the N + emission region; performing photoetching on the ILD layer, implanting B11/20Kev/2E15 and B11/35Kev/5E13, and annealing at high temperature of 1000C/0.25min to form a contact region (contact); then plating a Ti/TiN layer, depositing tungsten, and etching the tungsten to the surface of the ILD layer; finally, depositing metal, forming a metal emitter and a metal grid through photoetching, and depositing a passivation layer to finish the front process; preferably, the ILD layer is grown to a thickness of 0.4 μm;

s70, grinding the back of the wafer to the required thickness; then, carrying out ion implantation on the whole surface to form an N + cut-off region; then, ion implantation is carried out on the whole to form a P + collector region; and performing laser annealing, polishing, cleaning, evaporating and alloying the P + collector region to form back metal as a collector.

Although terms such as first trench, second trench, third trench, etc. are used more often herein, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed in a manner that is inconsistent with the spirit of the invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A Split Gate-IGBT structure is characterized in that: comprises a Split Gate structure and a Trench Gate structure; one or more Trench Gate structures are arranged between the Split Gate structures;

2. The Split Gate-IGBT structure of claim 1, wherein: the Split Gate structure and the Trench Gate structure are sequentially connected with a PW area, an N + emission area, an ILD area, a Metal area and a passivation area.

3. The Split Gate-IGBT structure of claim 1, wherein: and a structure for reducing grid charge is arranged on the Split Gate structure.

4. The Split Gate-IGBT structure of claim 3, wherein: the gate charge reduction structure comprises a third trench; and the third groove is arranged between two ends of the Split Gate structure and the connection of the emitter.

5. A device, characterized by: a Split Gate-IGBT structure according to any of claims 1 to 4 is used.