CN114497201A - Field effect transistor of integrated body relay diode, preparation method thereof and power device - Google Patents
Field effect transistor of integrated body relay diode, preparation method thereof and power device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
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- 238000003892 spreading Methods 0.000 claims description 14
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- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 description 21
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention provides a field effect transistor of an integrated body relay diode, a preparation method thereof and a power device. The field effect transistor device comprises a substrate, a functional body, a gate medium, a gate and an outer electrode, wherein the functional body comprises a drift epitaxial region, a well region, a source region, a trench shielding region and a first gate shielding region, a gate trench and an electrode trench are arranged in the functional body, notches are positioned on the surface of one side, far away from the substrate, of the functional body, a first gate shielding region and a part of drift epitaxial region are sequentially arranged between the gate trench and the electrode trench in the first partition wall, and the drift epitaxial region in the first partition wall is electrically connected with the outer electrode in the electrode trench. The field effect device realizes that the body diode is integrated in the field effect device under the condition of basically not increasing the area of the device, which is equivalent to reducing the area required by a chip actually prepared.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a field effect transistor of an integrated body relay diode, a preparation method thereof and a power device.
Background
A power semiconductor device is an electronic device that may be used in power conversion and control circuits for electrical power equipment. The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has the advantages of high switching speed, high input impedance, good thermal stability, small required driving power, simple driving circuit, high working frequency and the like, and is a semiconductor power device with wide application. MOSFETs have either a lateral or vertical structure. In a lateral structure MOSFET, the electrodes (source and drain) of the device are on the same surface of the device. Whereas in a vertical MOSFET the electrodes are arranged on opposite surfaces of the device, respectively. Vertical MOSFETs have a lower on-resistance due to the absence of Junction Field Effect Transistors (JFETs).
A trench MOSFET is a common vertical MOSFET. A drift region, a base region and a source region are generally arranged in an epitaxial layer of a traditional trench type MOSFET device, the doping type of the base region is different from that of the drift region and the source region, and the base region forms a channel between the drift region and the source region. A trench MOSFET device as shown in fig. 1 includes a substrate 110, a drift region 120 disposed on the substrate 110, a base region 130, a source region 140, a gate dielectric 151, a gate 152, a gate insulating layer 153, a source electrode 160, and a drain electrode 170. The mode of operation of the device can be described as follows: when the device is in the blocking state, there are few electrons in the base region 130 and electrons cannot flow from the source region 140 to the drift region 120. Typically the drift region 120 and source region 140 are n-type doped and the base region 130 is p-type doped so that no electrons are present in the channel when blocking. When a voltage greater than a threshold value is applied to the gate electrode 132, a layer having a large electron concentration is formed in the base region 130, and the source region 140 and the drift region 120 can be connected to each other.
However, there are some problems in the conventional trench MOSFET, such as the high electric field applied to the bottom of the gate dielectric, which causes the gate dielectric to break down, and the conventional technology usually adopts the shielding region to shield the high electric field at the bottom of the gate dielectric, which in turn causes the trench MOSFET to use more chip area when integrating the body diode.
Disclosure of Invention
In view of the above, it is desirable to provide an integrated body-relay diode field effect transistor capable of shielding the electric field at the bottom of the gate dielectric and reducing the required chip area, and correspondingly, a method for manufacturing the field effect transistor device and a power device.
According to one embodiment of the present invention, a field effect transistor integrated with a bulk relay diode includes a substrate, a functional body, a gate dielectric, a gate electrode, and an outer electrode;
the functional main body comprises a drift epitaxial region, a well region, a source region, a groove shielding region and a first grid shielding region, the doping types of the drift epitaxial region and the source region are first doping types, the doping types of the well region, the first grid shielding region and the groove shielding region are second doping types opposite to the first doping types, the drift epitaxial region is arranged on the substrate in a stacked mode, the groove shielding region and the well region are arranged on one side surface, far away from the substrate, of the drift epitaxial region in a stacked mode, and the source region is arranged on one side surface, far away from the drift epitaxial region, of the well region in a stacked mode;
the functional main body is provided with a grid groove and an electrode groove, notches of the grid groove and the electrode groove are positioned on the surface of one side far away from the substrate, the grid groove and the electrode groove are arranged at intervals, the grid medium and the grid are arranged in the grid groove, and the outer electrode is arranged in the electrode groove;
the bottom wall of the electrode groove is provided with the groove shielding region, the groove shielding region is electrically connected with the outer electrode, two sides of the grid groove are provided with a first partition wall and a second partition wall which are opposite, the first partition wall is positioned between the grid groove and the electrode groove and is along the direction from the second partition wall to the first partition wall, the first grid shielding region and part of the drift epitaxial region are sequentially arranged in the first partition wall, the drift epitaxial region positioned in the first partition wall is electrically connected with the outer electrode in the electrode groove, and the source region and the well region are arranged in the second partition wall.
In one embodiment, a side of the second partition wall remote from the gate trench is also provided with the electrode trench and the trench shielding region.
In one embodiment, there are a plurality of gate trenches, the gate trenches are arranged side by side at intervals, and the first partition, the electrode trench, and the second partition are sequentially arranged between two adjacent gate trenches.
In one embodiment, the trench shielding region further extends from a bottom wall of the electrode trench to a portion of the second partition wall adjacent to the electrode trench on a side of the second partition wall away from the gate trench.
In one embodiment, the semiconductor device further includes a second gate shielding region having the second doping type, the second gate shielding region is disposed under the gate trench and contacts the gate dielectric, and the second gate shielding region is connected to the first gate shielding region.
In one embodiment, the bottom wall of the electrode trench is flush with the bottom wall of the gate trench.
In one embodiment, a drift layer and a current spreading layer are arranged in the drift epitaxial region, the drift layer is arranged on the substrate in a stacked mode, the current spreading layer is arranged on the drift layer in a stacked mode, the interface of the drift layer and the current spreading layer is below the bottom face of the gate trench, and the doping concentration of the current spreading layer is higher than that of the drift layer.
In one embodiment, the substrate of the functional body is silicon carbide.
In one embodiment, the substrate has a thickness of 100 μm to 500 μm, and/or
The thickness of the drift epitaxial region is 5-100 mu m.
Correspondingly, the preparation method of the field effect transistor of the integrated body relay diode comprises the following steps:
preparing a functional body precursor on a substrate having a first doping type, the functional body precursor comprising a drift epitaxial region having the first doping type, which is arranged on the substrate in a stack;
etching the functional body precursor to form a gate trench and an electrode trench, wherein the functional body precursor is provided with a first partition wall and a second partition wall which are opposite and positioned at two sides of the gate trench, and the first partition wall is positioned between the gate trench and the electrode trench;
forming a first gate shielding region with a second doping type in the first partition wall, wherein the second doping type is different from the first doping type, a trench shielding region with the second doping type is formed below the electrode trench, the drift epitaxial region is formed between the first gate shielding region and the electrode trench, and a well region and a source region which are sequentially stacked are formed in the second partition wall, so that a functional body is formed by a functional body precursor, the doping type of the source region is the second doping type, and the doping type of the well region is the first doping type;
forming a gate dielectric and a gate in the gate trench;
forming an outer electrode in the electrode trench, electrically connected to the trench shielding region and the drift epitaxial region.
In one embodiment, in the step of forming the first gate shielding region, a second gate shielding region located below the gate trench is formed at the same time as the first gate shielding region by using an oblique ion implantation.
In one embodiment, in the step of forming the first gate shield region, the first gate shield region and the trench shield region are formed simultaneously.
Further, a power device comprising the field effect transistor integrated with the bulk relay diode according to any of the above embodiments, or comprising the field effect transistor prepared by the method for preparing the field effect transistor integrated with the bulk relay diode according to any of the above embodiments.
The field effect transistor device in the present invention has the following advantageous effects.
The field effect transistor device comprises a first grid shielding region and a groove shielding region, and the grid shielding region and the groove shielding region effectively protect a grid medium. On the basis of protecting the gate dielectric, the outer electrode is further arranged on the groove shielding region, the drift epitaxial region is further arranged between the first gate shielding region and the groove shielding region, and the drift epitaxial region and the outer electrode form a Schottky junction, so that the body diode is integrated in the field effect transistor device under the condition that the area of the device is not increased basically. Meanwhile, the positions of the first grid shielding region and the groove shielding region are skillfully utilized, so that the high electric field born by the Schottky junction can be shielded, and the leakage current of the device is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a trench MOSFET device;
fig. 2 is a schematic cross-sectional structure of a first field effect device according to an embodiment of the invention;
fig. 3 is a schematic cross-sectional structure diagram of a second field effect device according to yet another embodiment of the invention;
fig. 4 is a schematic cross-sectional structure diagram of a third field effect device according to yet another embodiment of the invention.
Detailed Description
In order that the invention may be more fully understood, reference will now be made to the following description. Preferred embodiments of the present invention are presented herein. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. As used herein, "plurality" includes two and more than two items. As used herein, "above a certain number" should be understood to mean a certain number and a range greater than a certain number.
The invention provides a field effect transistor integrated with a body diode, which comprises a substrate, a functional main body, a gate medium, a gate and an outer electrode, wherein the functional main body is arranged on the substrate; the functional main body comprises a drift epitaxial region, a well region, a source region, a groove shielding region and a first grid shielding region, the doping types of the drift epitaxial region and the source region are first doping types, the doping types of the well region, the first grid shielding region and the groove shielding region are second doping types opposite to the first doping types, the drift epitaxial region is arranged on a substrate in a stacked mode, the groove shielding region and the well region are arranged on one side surface, far away from the substrate, of the drift epitaxial region in a stacked mode, and the source region is arranged on one side surface, far away from the drift epitaxial region, of the well region in a stacked mode.
A grid electrode groove and an electrode groove with notches positioned on the surface of one side far away from the substrate are arranged in the functional main body, the grid electrode groove and the electrode groove are arranged at intervals, a grid medium and a grid electrode are arranged in the grid electrode groove, and an outer electrode is arranged in the electrode groove; the bottom wall of the electrode groove is provided with a groove shielding region which is electrically connected with an external electrode, two sides of the grid groove are provided with a first partition wall and a second partition wall which are opposite, the first partition wall is positioned between the grid groove and the electrode groove, the first grid shielding region and a part of drift epitaxial region are sequentially arranged in the first partition wall along the direction from the second partition wall to the first partition wall, the drift epitaxial region positioned in the first partition wall is electrically connected with the external electrode in the electrode groove, and the second partition wall is provided with a source region and a well region.
To understand the specific structure of the fet, please refer to fig. 2, which shows a schematic cross-sectional structure diagram of the first fet device 200 in one embodiment. The first field effect device includes a substrate 210, a drift epitaxial region 220, a well region 231, a source region 232, a first gate shield region 241, a second gate shield region 242, a trench shield region 250, a gate 261, a gate dielectric 262, a gate insulating layer 263, a source electrode 271, and a drain electrode 280. The drift epitaxial region 220, the well region 231, the source region 232, the first gate shielding region 241, the second gate shielding region 242 and the trench shielding region 250 together constitute a functional body. In this first field effect device, the source electrode 271 is the outer electrode in the above-described embodiment.
It can be understood that in a semiconductor device, different regions are usually doped with different types or different concentrations based on an intrinsic semiconductor, and the intrinsic semiconductor is doped with a heteroatom to form a doped semiconductor. The doping may be classified into N-type doping and P-type doping according to the kind of doping atoms, and correspondingly, the doped semiconductor may be classified into N-type semiconductor and P-type semiconductor. The carriers in the N-type semiconductor are mainly electrons, the N-type semiconductor mainly relies on electrons to conduct electricity, the carriers in the P-type semiconductor are mainly holes, and the P-type semiconductor mainly relies on holes to conduct electricity. In the present embodiment, the source region 232 and the drift epitaxial region 220 have a first doping type, and the well region 231, the first gate 261 shield region and the trench shield region 250 have a second doping type opposite to the first doping type. Optionally, the first doping type is N-type doping, and the second doping type is P-type doping. Further, the substrate 210 may also have an N-type doping. The functional body may be formed by further processing an epitaxial layer after forming the epitaxial layer on the substrate 210. The functional body is named as a whole after the epitaxial layer is processed, and does not imply that the functional body can realize certain specific functions, and the functional body is a semiconductor.
The well region 231 is stacked on the drift epitaxial region 220, and the source region 232 is stacked on a surface of the well region 231 on a side away from the drift epitaxial region 220. Wherein the source region 232 is electrically contacted to the source 271. When the bias voltage applied to the gate electrode 261 is less than the threshold voltage, the channel has substantially no carriers that can move, the source electrode 271 and the drain electrode 280 cannot be turned on, and the device is closed. When the bias voltage applied to the gate 261 is greater than the threshold voltage, a layer of carriers is generated in the channel, so that conduction can be conducted between the source 271 and the drain 280, and the device is turned on.
In the first field effect device of this embodiment, the gate trench 260 and the electrode trench 270 having notches at a side surface away from the substrate 210 are provided in the functional body, and the gate trench 260 and the electrode trench 270 are provided at intervals. A gate dielectric 262 and a gate electrode 261 are disposed in the gate trench 260, and a source electrode 271 is disposed in the electrode trench 270. It will be appreciated that the gate dielectric 262 is disposed between the functional body and the gate 261 for insulating the regions separating the gate 261 and the functional body, the gate dielectric 262 should have insulating properties. A gate insulating layer 263 insulating both of the spacers is also disposed between the gate electrode 261 and the source electrode 271.
Further, the bottom wall of the electrode trench 270 is disposed with the trench shielding region 250, and the source 271 is disposed in the electrode trench 270 to be directly electrically contacted to the trench shielding region 250. The gate trench 260 has opposite first and second barrier ribs, the first barrier rib being located between the gate trench 260 and the electrode trench 270. Referring to fig. 2, the first barrier ribs are positioned at the right side of the gate trenches 260, and the second barrier ribs are positioned at the left side of the gate trenches 260. The first gate 261 shield region and a portion of the drift extension region 220 are sequentially disposed in the first barrier along a direction from the second barrier to the first barrier, i.e., from left to right.
The shielding region of the first gate 261 and the trench shielding region 250 work together to shield an electric field applied to the gate dielectric 262, thereby increasing the breakdown voltage of the field effect transistor device. And, the shielding region of the first gate 261 is directly contacted with the gate dielectric 262, the right side of the shielding region of the first gate 261 is further provided with a partial drift epitaxial region 220, one side of the drift epitaxial region 220 away from the shielding region of the first gate 261 is provided with a source 271 located in the electrode trench 270, and in turn, the source 271 is also electrically contacted with the drift epitaxial region 220. The source 271 may be a conductive material such as a metal, the drift epitaxial region 220 is a semiconductor material, and a schottky junction is formed between the source 271 and the drift epitaxial region 220. In this way, a body diode is integrated in the field effect transistor device, which can act as a freewheeling diode in the application. Meanwhile, as the first gate 261 shielding region and the trench shielding region 250 are respectively arranged on two sides of the body diode, the electric field near the body diode can be shielded under the combined action of the first gate 261 shielding region and the trench shielding region 250, and the leakage current of the field effect transistor device is reduced. In the conventional technology, the channel is disposed on both sides of the gate electrode 261, and the above-mentioned fet skillfully forms a schottky junction by using the drift epitaxial region 220 and the source electrode 271 in the electrode trench 270, so that a body diode can be integrated in the device without substantially increasing the area of the device.
Referring to fig. 2, a side of the second partition wall away from the gate trench 260, i.e., a left side of the second partition wall, is also provided with the electrode trench 270 and the trench shielding region 250, so that both sides of the gate electrode 261 are provided with the trench shielding region 250, and the trench shielding regions 250 on both sides can further effectively weaken the high electric field sustained by the gate dielectric 262.
Referring to fig. 2, the first field effect device further includes a second gate 261 shield region, the second gate 261 shield region having the second doping type, the second gate 261 shield region being disposed below the gate trench 260 and the second gate 261 shield region contacting the gate dielectric 262, the second gate 261 shield region being connected to the first gate 261 shield region. Specifically, the second gate 261 shield region is located in the bottom wall of the gate trench 260, the first gate 261 shield region is located in the first partition wall of the gate trench 260, and the second gate 261 shield region extends from the bottom wall of the gate trench 260 to be connected to the first gate 261 shield region; the shielding region of the second gate 261 is connected with the shielding region of the first gate 261 to form an L-shape. The shielding region of the second gate 261 can further shield the high electric field at the bottom of the gate dielectric 262, and meanwhile, the shielding region of the second gate 261 can be formed simultaneously with the shielding region of the first gate 261 by means of oblique ion implantation, so that the breakdown voltage of the device can be improved without increasing the number of manufacturing processes.
In one specific example, the substrate of the functional body is a semiconductor, such as a silicon carbide semiconductor. The regions of the functional body may have different types or concentrations of doping.
In one specific example, substrate 210 has a thickness of 100 μm to 500 μm, such as substrate 210 having a thickness of 200 μm to 400 μm, and such as substrate 210 having a thickness of 250 μm to 350 μm.
In one specific example, the thickness of drift epitaxial region 220 is 5 μm to 100 μm, for example, the thickness of drift epitaxial region 220 is 10 μm to 80 μm, and for example, the thickness of drift epitaxial region 220 is 20 μm to 50 μm.
Fig. 3 shows a second field effect device which is further optimized on the basis of the first field effect device shown in fig. 2. Specifically, the second field effect device is mainly different from the first field effect device in that a drift layer 221 and a current spreading layer 222 are further provided in the second field effect device. The drift layer 221 is stacked on the substrate 210, the current spreading layer 222 is stacked on the drift layer 221, an interface of the drift layer 221 and the current spreading layer 222 is below a bottom surface of the gate trench 260, and a doping concentration in the current spreading layer 222 is higher than that of the drift layer 221. The arrangement can effectively reduce the on-resistance of the field effect transistor device.
Fig. 4 shows a third field effect device which is further optimized on the basis of the second field effect device shown in fig. 3. Specifically, there are a plurality of gate trenches 260 in the third field effect transistor device, and the plurality of gate trenches 260 are arranged side by side at intervals.
A first partition wall of one of the gate trenches 260, an electrode trench 270 and a second partition wall of the other gate trench 260 are sequentially disposed between two adjacent gate trenches 260, but the sequential disposition is not particularly limited to a specific orientation. For example, in fig. 3, the first barrier rib of the previous gate trench 260, the electrode trench 270, and the second barrier rib of the next gate trench 260 are formed in order from left to right, and the second barrier rib of the previous gate trench 260, the electrode trench 270, and the first barrier rib of the next gate trench 260 are formed from right to left. It can be understood that the electrode trench 270 between two adjacent gate trenches 260 and the trench shielding region 250 located at the bottom wall of the electrode trench 270 can simultaneously shield the electric field borne by the gate dielectric 262 in the previous gate trench 260 and also shield the electric field borne by the gate dielectric 262 in the next gate trench 260, so that one electrode trench 270 and the trench shielding region 250 are designed to be shared between two adjacent gate trenches 260, and the area occupied by the device can be effectively saved.
Further, in one specific example, in the electrode trench 270 and the trench shield region 250 located on the side of the second partition wall away from the gate trench 260, the trench shield region 250 also extends from the bottom wall of the electrode trench 270 to a portion of the second partition wall next to the electrode trench 270. The trench shield region 250 is designed to facilitate the simultaneous fabrication of the trench shield region 250 with the first gate 261 shield region and the second gate 261 shield region. Specifically, when the shielding regions of the first gate electrode 261 and the second gate electrode 261 are prepared by using the tilted ion implantation method, the electrode trench 270 is exposed, and the trench shielding region 250 is formed at the same time on the bottom and the side of the electrode trench 270, thereby simplifying the preparation process of the device. Meanwhile, although the portion of the trench shielding region 250 beside the electrode trench 270 may occupy the portion originally belonging to the well 231, since the trench shielding region 250 also has the second conductivity type, it does not affect the formation of the channel and the normal turn-on of the device.
In one specific example, the interface between the well region 231 and the drift epitaxial region 220 is above the bottom surface of the electrode trench 270. Further, the bottom surface of the electrode trench 270 is flush with the bottom surface of the gate trench 260, which mainly enables the electrode trench 270 and the gate trench 260 to be formed through the same etching process, and further simplifies the manufacturing process of the device.
In the field effect device in the above embodiments, the first doping type is n-type doping and the second doping type is p-type doping, although other suitable doping types may be used.
In the field effect device in the above embodiments, the doping concentration of the drift epitaxial region may be 1 × 10, although other suitable doping concentrations may be used15～9×1017/cm3(ii) a Further, the doping concentration of the drift layer may be 1 × 1015～9×1017/cm3The doping concentration of the current spreading layer may be 2 × 1015～1×1018/cm3. The doping concentration of the well region may be 5 × 1015～1×1018/cm3. The doping concentration of the source region may be 1 × 1018～1×1021/cm3. The doping concentration of the first gate shielding region may be 1 × 1017～1×1019/cm3The doping concentration of the trench shield region may be1×1017～1×1019/cm3。
Yet another embodiment of the present invention further provides a method for manufacturing a body diode integrated field effect transistor device, which includes the following steps.
Step S1, a functional body precursor is prepared on the substrate having the first doping type, the functional body precursor including a drift epitaxial region having the first doping type.
The base semiconductor of the functional host precursor may be silicon carbide. The functional body precursor may be prepared on the substrate by epitaxial growth, and impurity atoms may be doped simultaneously when the functional body precursor is epitaxially grown, so that a drift epitaxial region having the first doping type is formed in the functional body precursor.
Alternatively, a drift layer stacked on the substrate and a current spreading layer stacked on the drift layer may be further formed in the drift epitaxial region by controlling the amount of impurity atoms doped at different stages in the epitaxial growth process.
Step S2, etching a functional body precursor to form a gate trench and an electrode trench, where the functional body precursor has a first spacer and a second spacer opposite to the gate trench, and the first spacer of the gate trench is located between the gate trench and the electrode trench.
Wherein, a specific manner of etching the functional body precursor may be dry etching.
And when the current expansion layer is arranged in the drift epitaxial region, controlling the etching depth so that the bottom surfaces of the gate trench and the electrode trench are both in the current expansion layer.
Although the gate trench and the electrode trench may be separately etched, in order to simplify a specific manufacturing process, the gate trench and the electrode trench may be simultaneously etched, and the bottom surfaces of the gate trench and the electrode trench thus formed are leveled.
In step S3, a first gate shielding region having a second doping type different from the first doping type is formed in the first barrier rib, and a trench shielding region having the second doping type is formed under the electrode trench.
Optionally, in the step of forming the first gate shielding region, a second gate shielding region located below the gate trench is formed at the same time as the first gate shielding region is formed by using an oblique ion implantation method.
Optionally, during the tilted ion implantation, the electrode trench is exposed together, so that a trench shielding region is formed on the bottom wall of the electrode trench. It will be appreciated that this will also result in a simultaneous formation of trench shield regions in the portions of the second spacer walls immediately adjacent to the electrode trenches.
In step S4, a well region and a source region are formed in the second partition wall so as to be stacked in this order.
The well region has the second doping type, and the source region has the first doping type. Correspondingly, a deeper well region may be formed by a higher energy ion implantation, and a shallower source region may be formed by a lower energy ion implantation.
It is understood that in other embodiments, the specific order of formation of the well region, the source region, the first gate shield region, the second gate shield region, and the trench shield region may be suitably adjusted. In this embodiment, the well region and the source region may be formed later, considering that the simultaneous formation of the first gate shielding region, the second gate shielding region and the trench shielding region by the oblique ion implantation also affects the second partition walls of the gate trench.
In step S5, an outer electrode electrically connected to the trench shield region and the drift epitaxial region is formed in the electrode trench such that the outer electrode extends to be electrically connected to the source region.
Wherein the outer electrode is a source electrode. The source is electrically connected to the source region. Further, the source may also be electrically connected to the first gate shield region.
In particular, the source electrode may be obtained by depositing an entire layer of conductive material directly on the surface of the functional body, it being understood that in this case it is also necessary to form a gate insulating layer on the gate electrode before the conductive material is prepared, in order to insulate the spacer gate electrode from the subsequently formed source electrode.
In step S6, external electrodes electrically connected to the substrate are formed on the surface of the substrate on the side away from the functional body. Wherein the outer electrode is a drain electrode. It is understood that in other embodiments, the step of forming the drain may be performed before the other steps.
Through the steps S1 to S6 and the selection of the specific manner, the field effect transistor of the integrated body relay diode in each of the above embodiments can be completed.
The field effect transistor device can be used for preparing a power device. Specifically, the power device includes the field effect transistor of the integrated body relay diode in any of the above embodiments, or includes the field effect transistor manufactured by the manufacturing method of the field effect transistor of the integrated body relay diode in any of the above embodiments.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (13)
1. A field effect transistor of an integrated body relay diode is characterized by comprising a substrate, a functional main body, a gate dielectric, a gate electrode and an outer electrode;
the functional main body comprises a drift epitaxial region, a well region, a source region, a groove shielding region and a first grid shielding region, the doping types of the drift epitaxial region and the source region are first doping types, the doping types of the well region, the first grid shielding region and the groove shielding region are second doping types opposite to the first doping types, the drift epitaxial region is arranged on the substrate in a stacked mode, the groove shielding region and the well region are arranged on one side surface, far away from the substrate, of the drift epitaxial region in a stacked mode, and the source region is arranged on one side surface, far away from the drift epitaxial region, of the well region in a stacked mode;
the functional main body is provided with a grid groove and an electrode groove, notches of the grid groove and the electrode groove are positioned on the surface of one side far away from the substrate, the grid groove and the electrode groove are arranged at intervals, the grid medium and the grid are arranged in the grid groove, and the outer electrode is arranged in the electrode groove;
the bottom wall of the electrode groove is provided with the groove shielding region, the groove shielding region is electrically connected with the outer electrode, two sides of the grid groove are provided with a first partition wall and a second partition wall which are opposite, the first partition wall is positioned between the grid groove and the electrode groove and is along the direction from the second partition wall to the first partition wall, the first grid shielding region and part of the drift epitaxial region are sequentially arranged in the first partition wall, the drift epitaxial region positioned in the first partition wall is electrically connected with the outer electrode in the electrode groove, and the source region and the well region are arranged in the second partition wall.
2. The bulk relay diode-integrated field effect transistor according to claim 1, wherein a side of the second partition wall remote from the gate trench is also provided with the electrode trench and the trench shielding region.
3. The bulk relay diode-integrated field effect transistor according to claim 2, wherein the gate trench is provided in plurality, the plurality of gate trenches are arranged side by side at intervals, and the first partition, the electrode trench, and the second partition are sequentially arranged between two adjacent gate trenches.
4. The bulk-relay-diode-integrated field effect transistor of claim 2, wherein the trench shielding region further extends from a bottom wall of the electrode trench to a portion of the second partition wall proximate to the electrode trench on a side of the second partition wall remote from the gate trench.
5. The integrated body relay diode field effect transistor according to any one of claims 1 to 4, further comprising a second gate shield region having the second doping type, the second gate shield region being disposed below the gate trench and contacting the gate dielectric, the second gate shield region being connected to the first gate shield region.
6. The bulk relay diode-integrated field effect transistor of claim 5, wherein a bottom wall of the electrode trench is flush with a bottom wall of the gate trench.
7. The integrated body relay diode field effect transistor according to any one of claims 1 to 4 and 6, wherein a drift layer and a current spreading layer are arranged in the drift epitaxial region, the drift layer is arranged on the substrate in a stacked manner, the current spreading layer is arranged on the drift layer in a stacked manner, an interface of the drift layer and the current spreading layer is below a bottom surface of the gate trench, and a doping concentration in the current spreading layer is higher than that in the drift layer.
8. The field effect transistor of an integrated body relay diode according to any one of claims 1 to 4 and 6, wherein the substrate of the functional body is silicon carbide.
9. The integrated body relay diode field effect transistor according to any of claims 1 to 4 and 6, wherein the thickness of the substrate is 100 μm to 500 μm, and/or
The thickness of the drift epitaxial region is 5-100 mu m.
10. A preparation method of a field effect transistor of an integrated body relay diode is characterized by comprising the following steps:
preparing a functional body precursor on a substrate having a first doping type, the functional body precursor comprising a drift epitaxial region having the first doping type, which is arranged on the substrate in a stack;
etching the functional body precursor to form a gate trench and an electrode trench, wherein the functional body precursor is provided with a first partition wall and a second partition wall which are opposite and positioned at two sides of the gate trench, and the first partition wall is positioned between the gate trench and the electrode trench;
forming a first gate shielding region with a second doping type in the first partition wall, wherein the second doping type is different from the first doping type, a trench shielding region with the second doping type is formed below the electrode trench, the drift epitaxial region is formed between the first gate shielding region and the electrode trench, and a well region and a source region which are sequentially stacked are formed in the second partition wall, so that a functional body is formed by a functional body precursor, the doping type of the source region is the second doping type, and the doping type of the well region is the first doping type;
forming a gate dielectric and a gate in the gate trench;
forming an outer electrode in the electrode trench, electrically connected to the trench shielding region and the drift epitaxial region.
11. The method as claimed in claim 10, wherein the step of forming the first gate shielding region further comprises forming a second gate shielding region under the gate trench simultaneously with the first gate shielding region by tilted ion implantation.
12. The method of claim 11, wherein the step of forming the first gate shield region is performed simultaneously with the step of forming the trench shield region.
13. A power device comprising the field effect transistor of the integrated body relay diode according to any one of claims 1 to 9, or the field effect transistor produced by the method for producing the field effect transistor of the integrated body relay diode according to any one of claims 10 to 12.
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