CN114725219B - Silicon carbide trench gate transistor and method of manufacturing the same - Google Patents

Silicon carbide trench gate transistor and method of manufacturing the same Download PDF

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CN114725219B
CN114725219B CN202210651597.0A CN202210651597A CN114725219B CN 114725219 B CN114725219 B CN 114725219B CN 202210651597 A CN202210651597 A CN 202210651597A CN 114725219 B CN114725219 B CN 114725219B
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trench
gate
silicon carbide
epitaxial layer
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CN114725219A (en
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崔京京
章剑锋
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Ruineng Semiconductor Technology Co ltd
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Ruineng Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The application discloses a silicon carbide trench gate transistor and a manufacturing method thereof, and relates to the field of semiconductor devices. The silicon carbide trench gate transistor includes: a silicon carbide substrate comprising a first surface; an epitaxial layer of a first doping type is arranged on the first surface; a plurality of second doping type body regions arranged at intervals are embedded in the epitaxial layer; the body region includes a bottom region and a side region connected to one end of the bottom region; the epitaxial layer is formed on the surface, far away from the first surface, of the epitaxial layer, and the plurality of gate groove structures, the plurality of source groove structures, the plurality of planar gate structures and the plurality of well regions are formed on the surface; and forming a second doping area of the first doping type in the well area close to the side face of the grid electrode groove structure and the well area positioned outside the source electrode groove structure. According to the embodiment of the application, the on-resistance can be reduced, so that the chip area is reduced, and the chip cost is reduced.

Description

Silicon carbide trench gate transistor and method of manufacturing the same
Technical Field
The application belongs to the field of semiconductor devices, and particularly relates to a silicon carbide trench gate transistor and a manufacturing method thereof.
Background
A power MOSFET has three pins, which are a Gate (Gate), a Drain (Drain) and a Source (Source). The power MOSFET is a voltage type control device, has simple driving circuit, small driving power, high switching speed and high working frequency. Commonly used MOSFET structures include Lateral Double-Diffused MOS (LDMOS), Planar Double-Diffused MOS (Planar MOS), and Trench Double-Diffused MOS (Trench MOS).
The existing silicon carbide groove double-diffused field effect transistor surrounds a middle gate groove structure through a deep PN junction, and due to the limitation of the process, the cell size (pitch) cannot be further reduced, so that the problems of large chip area and high cost exist.
Disclosure of Invention
Embodiments of the present application provide a silicon carbide trench gate transistor and a manufacturing method thereof, which can reduce on-resistance, thereby reducing a chip area and reducing a chip cost.
In a first aspect, an embodiment of the present application provides a silicon carbide trench gate transistor, including:
a silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface; an epitaxial layer of a first doping type is arranged on the first surface;
a plurality of second doping type body regions arranged at intervals are embedded in the epitaxial layer; the body region includes a bottom region and a side region connected to one end of the bottom region;
a plurality of gate trench structures, a plurality of source trench structures, a plurality of planar gate structures and a plurality of well regions formed on the surface of the epitaxial layer away from the first surface; wherein the source trench structure is in contact with the side region and a portion of the bottom region; the grid groove structure is positioned between the adjacent body regions; the planar gate structure is positioned on the outer side of the source electrode groove structure; the grid layer of the plane grid structure is electrically connected with the grid layer in the grid groove structure; the well region of the second doping type is arranged in the interval region between the grid groove structure and the source groove structure and is connected with one end of the side region; forming a second doping area of the first doping type in the well area close to the side face of the grid electrode groove structure and the well area positioned on the outer side of the source electrode groove structure;
the first doping type is opposite to the second doping type.
In an alternative embodiment, an embedded structure is provided on the side of the source trench structure remote from the side region.
In an alternative embodiment, the embedded structure forms a schottky contact for the epitaxial layer and the source of the source trench structure.
In an alternative embodiment, the embedded structure is formed by forming an ohmic contact between the epitaxial layer and the source of the source trench structure, the distance between the well region and the body region in the direction perpendicular to the silicon carbide substrate is less than or equal to a first preset distance, and the distance between the body regions on two sides of the planar gate structure in the direction parallel to the silicon carbide substrate is less than a second preset distance.
In an alternative embodiment, the silicon carbide substrate further comprises a second surface opposite the first surface, the second surface being provided with the drain structure.
In an alternative embodiment, the gate layer in the gate trench structure is connected to the gate layer of the planar gate structure at a predetermined crystal plane of the gate trench structure.
In a second aspect, an embodiment of the present application provides a method for manufacturing a silicon carbide trench gate transistor, including:
providing a silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface; an epitaxial layer of a first doping type is arranged on the first surface;
carrying out ion doping of a second doping type on the surface, far away from the first surface, of the epitaxial layer to form a plurality of first doping regions of the second doping type, which are arranged at intervals and embedded in the epitaxial layer;
performing trench etching on the surface of the epitaxial layer far away from the first surface, so that the first doping region forms a body region comprising a bottom region and a side region connected with one end of the bottom region, forms a first trench contacting with the side region and part of the bottom region of the body region, and forms a second trench positioned between adjacent body regions;
carrying out ion doping of a second doping type on the surface, far away from the first surface, of the epitaxial layer to form a well region of the second doping type;
forming a second doping area of the first doping type in the well area close to the side face of the second groove and the well area positioned at the outer side of the first groove;
forming a grid groove structure in the second groove and forming a plane grid structure in a surface area, away from the first surface, of the epitaxial layer on the outer side of the first groove; the grid layer of the planar grid structure is electrically connected with the grid layer in the grid groove structure;
and filling a metal material into the first trench to form a source trench structure.
In some optional embodiments, before filling the metal material into the first trench to form the source trench structure, the method further includes:
an embedded structure is formed on a side of the first trench away from the side region.
In some optional embodiments, the embedded structure forms a schottky contact for the epitaxial layer and the source of the source trench structure.
In some optional embodiments, the embedded structure forms an ohmic contact between the epitaxial layer and the source of the source trench structure, the distance between the well region and the body region in the direction perpendicular to the silicon carbide substrate is less than or equal to a first preset distance, and the distance between the body regions on two sides of the planar gate structure in the direction parallel to the silicon carbide substrate is less than or equal to a second preset distance.
The silicon carbide trench gate transistor of the embodiment of the present application, the silicon carbide trench gate transistor includes: the semiconductor device comprises a plurality of gate groove structures, a plurality of source groove structures, a plurality of plane gate structures and a plurality of well regions, wherein the gate groove structures, the source groove structures, the plane gate structures and the well regions are formed on the surface, far away from the first surface, of the epitaxial layer. And the planar gate structure is located at the periphery of the gate trench structure and is electrically connected with the gate trench structure, that is, the planar gate structure surrounds the gate trench structure. The mode that the planar gate structure surrounds the gate groove structure increases a current conduction path, and then reduces the on-resistance, thereby reducing the area of a chip and reducing the cost of the chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of one configuration of an embodiment of a silicon carbide trench-gate transistor provided herein;
FIG. 2 is a schematic structural view of an embodiment of a cross-sectional view along the direction A-A in FIG. 1;
FIG. 3 is a flow chart illustrating a schematic diagram of an embodiment of a method of fabricating a silicon carbide trench-gate transistor provided herein;
FIG. 4 is a schematic cross-sectional structural view of a silicon carbide substrate of a first doping type as provided herein;
FIG. 5 is a schematic cross-sectional view of a first doped region of a second doping type formed according to the present application;
FIG. 6 is a schematic cross-sectional structure of the body region, the first trench and the second trench provided herein;
fig. 7 is a schematic cross-sectional structure diagram of a well region formed with a second doping type provided in the present application;
FIG. 8 is a schematic cross-sectional view of a second doped region of a first doping type formed according to the present application;
FIG. 9 is a schematic cross-sectional structure diagram of a gate trench structure and a planar gate structure formed as provided herein;
fig. 10 is a schematic cross-sectional structure diagram of forming an embedded structure provided herein.
The figures are numbered:
1: a silicon carbide substrate; 11: a first surface; 12: a second surface;
2: an epitaxial layer; 21: a body region; 211: a bottom region; 212: a side region; 22: a gate trench structure; 221: a gate layer; 222: an oxide layer; 23: a source trench structure; 24: a planar gate structure; 25: a well region; 251: a second doped region; 26: an embedded structure; 27: a first trench; 28: a second trench; 29: a first doped region;
3: and a drain structure.
In the drawings, like parts are provided with like reference numerals. The figures are not drawn to scale.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the dimensions of some of the structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The following description will be given with the directional terms as they are shown in the drawings, and the present invention is not limited to the specific structure of the silicon carbide MOSFET semiconductor device and the method for manufacturing the silicon carbide MOSFET semiconductor device. In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be directly connected or indirectly connected. The specific meaning of the above terms in this application can be understood as appropriate by one of ordinary skill in the art.
In order to solve the problems in the prior art, embodiments of the present application provide a silicon carbide trench gate transistor and a manufacturing method thereof. The following first describes a silicon carbide trench gate transistor provided in an embodiment of the present application.
Figure 1 shows a schematic diagram of one configuration of an embodiment of a silicon carbide trench-gate transistor as provided herein.
As shown in fig. 1, fig. 1 shows a schematic diagram of the structure of four cells (pitch) of a silicon carbide trench gate transistor.
In this embodiment, the unit cell refers to the smallest repeating unit of the conductive structure of the active region of the silicon carbide trench transistor. The structural schematic diagram in the application is a schematic diagram on the structural principle, and the actual size, the detail position and the like of each part contained in the power device can be adjusted according to the actual situation. In fig. 1, the silicon carbide trench-gate transistor includes four cells as an example, but not limited thereto, and the number of the cells included in the silicon carbide trench-gate transistor may be set according to practical situations, and is not limited herein.
Alternatively, the shape of the unit cell is a "loop" shape as shown in fig. 1.
Referring to fig. 2 and fig. 10 together, fig. 2 is a schematic structural diagram of an embodiment of a cross-sectional view along a-a direction in fig. 1. As shown in fig. 2, an embodiment of the present application provides a silicon carbide trench gate transistor including:
a silicon carbide substrate 1 of a first doping type, said silicon carbide substrate 1 comprising a first surface 11; an epitaxial layer 2 of a first doping type is arranged on the first surface 11;
a plurality of second doping type body regions 21 arranged at intervals are embedded in the epitaxial layer 2; the body region 21 includes a bottom region 211 and a side region 212 connected to one end of the bottom region 211;
a plurality of gate trench structures 22, a plurality of source trench structures 23, a plurality of planar gate structures 24, and a plurality of well regions 25 formed on a surface of the epitaxial layer 2 away from the first surface 11; wherein the source trench structure 23 is in contact with the side region 212 and a portion of the bottom region 211; the gate trench structure 22 is located between adjacent body regions 21; the planar gate structure 24 is located outside the source trench structure 23; the gate layer 221 of the planar gate structure 24 is electrically connected to the gate layer 221 of the gate trench structure 22; the well region 25 of the second doping type is disposed in the gap region between the gate trench structure 22 and the source trench structure 23, and is connected to one end of the side region 212; forming a second doped region 251 of the first doping type in the well region 25 near the side of the gate trench structure 22 and in the well region 25 outside the source trench structure 23;
the first doping type is opposite to the second doping type.
The silicon carbide trench gate transistor of the embodiment of the present application, the silicon carbide trench gate transistor includes: the semiconductor device comprises a plurality of gate groove structures, a plurality of source groove structures, a plurality of plane gate structures and a plurality of well regions, wherein the gate groove structures, the source groove structures, the plane gate structures and the well regions are formed on the surface, far away from the first surface, of the epitaxial layer. And the planar gate structure is located at the periphery of the gate trench structure and is electrically connected with the gate trench structure, that is, the planar gate structure surrounds the gate trench structure. The mode that the planar gate structure surrounds the gate groove structure increases a current conduction path, and then reduces the on-resistance, thereby reducing the area of a chip and reducing the cost of the chip.
In this embodiment, the first doping type is N-type, and the second doping type is P-type. The silicon carbide substrate 1 of the first doping type may be an N-type silicon carbide substrate 1. The epitaxial layer 2 of the first doping type may be an N-type epitaxial layer 2.
The epitaxial layer 2 may be at least one epitaxial layer 2. For example, the epitaxial layer 2 may be formed of at least one semiconductor material such as silicon carbide. In the present embodiment, taking the epitaxial layer 2 as a silicon carbide epitaxial layer as an example, silicon carbide can have a wider band gap than silicon, and thus can maintain stability at high temperature compared to silicon; in addition, since the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can also stably operate at a high temperature as compared with silicon.
The gate trench structure 22 and the source trench structure 23 may have a square, rectangular parallelepiped, or the like. The depth of the gate trench structure 22 and the depth of the source trench structure 23 in the direction perpendicular to the silicon carbide substrate 1 may be the same or different, and is not limited herein.
The gate trench structure 22 and the planar gate structure 24 may each include a gate layer 221 and an oxide layer 222. The gate layer 221 may include polysilicon, a metal material, or the like. The oxide layer 222 may be an oxide such as silicon dioxide.
The gate layer 221 of the planar gate structure 24 is electrically connected to the gate layer 221 of the gate trench structure 22, and can simultaneously apply signals to the planar gate structure 24 and the gate trench structure 22.
In order to make the current conduction more uniform, in some alternative embodiments, the gate layer 221 in the gate trench structure 22 may be connected to the gate layer 221 of the planar gate structure 24 in the predetermined crystal plane of the gate trench structure 22.
The predetermined crystal plane may be a crystal plane having the smallest channel mobility. The gate trench structure 22 generally has a crystal plane (e.g., -1-120) with the smallest channel mobility, and if the channel on this crystal plane is conducted simultaneously with the channels on other crystal planes, a current imbalance problem may be caused, and instead of providing a contact with the source trench structure 23 above the source of the crystal plane with the smallest channel mobility in the gate trench structure 22, polysilicon in the gate trench structure 22 is connected to the planar gate structure 24, so that the electron distribution on the channels of different crystal planes can be balanced, and the current conduction is more balanced.
In some alternative embodiments, the silicon carbide substrate 1 may further include a second surface 12 opposite to the first surface 11, and the second surface 12 may be provided with the drain structure 3.
The well 25 of the second doping type may be a P-type well 25. An N-type second doped region 251 is formed in the well region 25 near the side of the gate trench structure 22 and in the well region 25 outside the source trench structure 23.
As an example, when the sic trench gate transistor is in a forward mode, the drain structure 3 applies a high voltage, and the source trench structure 23 has a potential of 0V, a voltage Vds between the drain structure 3 and the source trench structure 23 is > 0, and N + in the second doped region 251 and the epitaxial layer 2 are not conducted through the well region 25, and no current flows. When a voltage of 15V is applied to the gate trench structure 22 and the planar gate structure 24, the surface of the well region 25 facing the gate trench structure 22 and the surface facing the planar gate structure 24 change from P-type to N-type, and electrons flow to the drain structure 3 through the gate trench structure 22 and the planar gate structure 24.
The first doping type is opposite to the second doping type, and the first doping type is N-type and the second doping type is P-type.
In order to protect the oxide layer 222 of the gate trench structure 22, in some alternative embodiments, an embedded structure 26 may be disposed on a side of the source trench structure 23 away from the side region 212.
The embedded structure 26 reduces the turn-on voltage of the silicon carbide MOSFET when it is turned on in the reverse direction.
In some alternative embodiments, the embedded structure 26 may form a schottky contact for the epitaxial layer 2 and the source of the source trench structure 23.
In this embodiment, the embedded structure 26 may be disposed on the planar gate structure 24 portion of the cell, and the source trench structure 23 may be disposed on a side surface away from the side region 212. In practical process, since the electric field at the corner of the oxide layer 222 of the gate trench structure 22 is large, and the oxide layer 222 of the gate trench structure 22 needs to be protected, the distance between the body regions 21 at the two sides of the gate trench structure 22 is small, so that the JFET resistance in the gate trench structure 22 is large, and if the embedded structure 26 is disposed on the side surface of the side region 212, the on-resistance of the embedded structure 26 is increased. The distance between the body regions 21 on both sides of the planar gate structure 24 is greater than the distance between the body regions 21 on both sides of the gate trench structure 22, so that the JFET resistance in the planar gate structure 24 is small, and the embedded structure 26 is provided on the side of the source trench structure 23 away from the side region 212 and on the side of the side region 212 with respect to the embedded structure 26, so that the on-resistance of the embedded structure 26 can be reduced.
For example, the embedded structure 26 may be a Junction-Barrier Schottky Rectifier (JBS). The on-state voltage of the embedded structure 26 is 1V, and the on-state turn-on voltage of the silicon carbide PN diode is 2.6V, so that the embedded structure 26 can be turned on under the condition of 1V in the reverse mode, thereby effectively reducing the on-state voltage of the silicon carbide MOSFET structure in the reverse direction. In addition, the embedded structure 26 is a unipolar device structure, and almost no reverse recovery time exists when the device is turned off, so that the turn-off speed can be increased.
Alternatively, the embedded structure 26 may be disposed vertically with respect to the first surface 11, which may save a lateral area of the sic trench transistor compared to a case where the embedded structure 26 is disposed parallel with respect to the first surface 11.
In some alternative embodiments, the embedded structure 26 may form an ohmic contact between the epitaxial layer 2 and the source of the source trench structure 23, a distance between the well region 25 and the bottom region 211 of the body region in a direction perpendicular to the silicon carbide substrate 1 is less than or equal to a first predetermined distance, and a distance between the body region 21 on both sides of the planar gate structure 24 in a direction parallel to the silicon carbide substrate 1 is less than or equal to a second predetermined distance.
The first preset distance and the second preset distance may be equal or unequal, and are not limited herein.
Since the distance between the well region 25 and the bottom region 211 of the body region in the direction perpendicular to the silicon carbide substrate 1 is less than or equal to a first predetermined distance, the distance between the body regions 21 on both sides of the gate trench structure 22 in the direction parallel to the silicon carbide substrate 1 is less than or equal to a second predetermined distance. The distance between the well region 25 and the bottom region 211 of the body region in the direction perpendicular to the silicon carbide substrate 1 is short, so that a significant pinch-off barrier can be formed, and further, since the distance between the body region 21 on both sides of the gate trench structure 22 in the direction parallel to the silicon carbide substrate 1 is short, the electrical stress borne by the embedded structure 26 when the silicon carbide MOSFET is forwardly blocked is further shielded, even if the embedded structure 26 is a pure resistive structure, the embedded structure 26 is an ohmic contact formed by the epitaxial layer 2 and the source of the source trench structure 23, and can not become a current leakage channel when the silicon carbide MOSFET is forwardly blocked, and at the same time, in a reverse mode of the silicon carbide MOSFET, becomes a current conduction channel, so that a reverse conduction voltage drop is reduced, and almost no reverse recovery time is left when the silicon carbide MOSFET is turned off, so that the turn-off speed can be improved.
It is noted that the first doping type is N-type and the second doping type is P-type in the present embodiment. However, in actual practice, the silicon carbide substrate 1 is not limited to N-type but may be P-type. When the silicon carbide substrate 1 is of the P-type, the conductivity types of the structures of the epitaxial layer 2, the body region 21, the well region 25, the second doped region 251, and the like also change accordingly.
Based on the silicon carbide trench gate transistor provided in the above embodiments, the present application also provides a method for manufacturing a silicon carbide trench gate transistor. A method of fabricating the above-described silicon carbide trench gate transistor will be described below.
Fig. 3 is a schematic flow chart diagram of an embodiment of a method for manufacturing a silicon carbide trench-gate transistor provided by the present application.
As shown in fig. 3, the method of manufacturing a silicon carbide trench-gate transistor includes steps S310 to S370. Please refer to fig. 4-10. Fig. 4-10 are schematic cross-sectional views of a series of processes for manufacturing a silicon carbide trench gate transistor according to the present invention.
S310, providing a silicon carbide substrate 1 of a first doping type, wherein the silicon carbide substrate 1 comprises a first surface 11; an epitaxial layer 2 of the first doping type is provided on the first surface 11.
In the present embodiment, the silicon carbide substrate 1 of the first doping type is an N-type silicon carbide substrate 1.
As shown in fig. 4, an N-type silicon carbide substrate 1 is first provided, and then a first epitaxy is performed on the silicon carbide substrate 1 to form an N-type epitaxial layer 2.
S320, performing ion doping of a second doping type on the surface of the epitaxial layer 2 away from the first surface 11 to form a plurality of first doping regions 29 of the second doping type embedded in the epitaxial layer 2 and spaced apart from each other.
As shown in fig. 5, the ion doping of P is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a plurality of spaced P-type first doped regions 29 embedded in the epitaxial layer 2, which may specifically include:
p-type first doping regions 29 formed on the surface of the epitaxial layer 2 at a plurality of intervals by doping ions of P into the surface of the epitaxial layer 2 away from the first surface 11;
and performing second epitaxy on the surface of the epitaxial layer 2 to form a plurality of spaced P-type first doped regions 29 embedded in the epitaxial layer 2.
And S330, performing groove etching on the surface of the epitaxial layer 2 far away from the first surface 11, so that the first doped region 29 forms a body region 21 comprising a bottom region 211 and a side region 212 connected with one end of the bottom region 211, forms a first groove 27 in contact with the side region 212 and a part of the bottom region 211 of the body region 21, and forms a second groove 28 located between adjacent body regions 21.
As shown in fig. 6, the performing trench etching on the surface of the epitaxial layer 2 away from the first surface 11 to form the first doped region 29 into a body region 21 including a bottom region 211 and a side region 212 connected to one end of the bottom region 211, and form a first trench 27 contacting the side region 212 and a part of the bottom region 211 of the body region 21, and form a second trench 28 located between adjacent body regions 21 may specifically include:
performing a first trench etching on the surface of the epitaxial layer 2 away from the first surface 11 to form a plurality of first trenches 27 and a plurality of second trenches 28;
a second trench etch is performed from top to bottom in the first doped region 29 to form a bottom region 211 and a side region 212 of the body region 21.
In an alternative embodiment, the first doped region 29 may be a bottom region 211 of the body region 21;
the performing of the trench etching on the surface of the epitaxial layer 2 away from the first surface 11 to form the body region 21 including the bottom region 211 and the side region 212 connected to one end of the bottom region 211 in the first doped region 29, and form the first trench 27 in contact with the side region 212 and a part of the bottom region 211 of the body region 21, and the second trench 28 located between adjacent body regions 21 may specifically include:
performing trench etching on the surface of the epitaxial layer 2 away from the first surface 11 to form a plurality of first trenches 27 and a plurality of second trenches 28;
p + type ion doping is implanted in a side of each of the first trenches 27 close to the second trench 28, thereby forming a side region 212 of the body region 21.
It is to be noted that, in the above embodiment, the plurality of first trenches 27 and the plurality of second trenches 28 are formed first, and then the P + -type ion doping is implanted to form the side region 212 as an example, in other embodiments, the P + -type ion doping may be implanted first, and then the plurality of first trenches 27 and the plurality of second trenches 28 are formed, which is not limited herein.
S340, performing ion doping of the second doping type on the surface of the epitaxial layer 2 away from the first surface 11 to form a well region 25 of the second doping type.
As shown in fig. 7, P + type ion doping is implanted into the surface of the epitaxial layer 2 away from the first surface 11 to form a P-type well region 25.
S350, forming a second doped region 251 of the first doping type in the well region 25 near the side of the second trench 28 and in the well region 25 outside the first trench 27.
As shown in fig. 8, the forming of the second doping region 251 of the first doping type in the well region 25 near the side surface of the second trench 28 and the well region 25 outside the first trench 27 may specifically include:
n + type ion doping is implanted into the well region 25 near the side surface of the second trench 28 and the well region 25 located outside the first trench 27, thereby forming an N type second doped region 251.
S360, forming a gate trench structure 22 in the second trench 28 and forming a planar gate structure 24 in a surface region of the epitaxial layer 2, which is far away from the first surface 11, outside the first trench 27; the gate layer 221 of the planar gate structure 24 is electrically connected with the gate layer 221 in the gate trench structure 22.
As shown in fig. 9, the forming of the gate trench structure 22 in the second trench 28 and the forming of the planar gate structure 24 in the surface region of the epitaxial layer 2 outside the first trench 27 and away from the first surface 11 may specifically include:
forming an oxide layer of a target region on the epitaxial layer 2;
forming a gate layer 221 in the second trench 28 to form a gate trench structure 22, and forming a gate layer 221 in a surface region of the epitaxial layer 2 outside the first trench 27 away from the first surface 11 to form a planar gate structure 24.
In some embodiments, the oxide layer forming the target region on the epitaxial layer 2 may be formed by oxidizing the epitaxial layer 2 with a mask placed on a predetermined region on the epitaxial layer 2.
Alternatively, in some embodiments, the forming of the oxide layer in the target region on the epitaxial layer 2 may specifically include:
oxidizing the epitaxial layer 2 to obtain an oxide layer of the epitaxial layer 2;
and removing the oxide layer in the preset area on the epitaxial layer 2 to obtain the oxide layer in the target area.
The target region may include an inner surface of the gate trench structure 22, an inner surface of the planar gate structure 24, and an outer surface of the planar gate structure 24.
The preset area may be an area other than the target area.
The gate layer 221 of the planar gate structure 24 is electrically connected to the gate layer 221 of the gate trench structure 22, and can simultaneously apply signals to the planar gate structure 24 and the gate trench structure 22.
S370, filling a metal material into the first trench 27 to form a source trench structure 23.
The source trench structure 23 is formed as shown in fig. 9.
In order to protect the oxide layer of the gate trench structure, in some embodiments, before filling the first trench 27 with a metal material to form the source trench structure 23, the method further includes:
an embedded structure 26 is formed on the side of the first trench 27 remote from the side region 212.
The resulting embedded structure 26 is shown in fig. 10.
In some embodiments, the embedded structure 26 may form a schottky contact between the epitaxial layer 2 and the source of the source trench structure 23.
Specifically, an embedded structure 26 is placed on the side of the first trench 27 away from the side region 212.
For example, the embedded structure 26 may be a Junction-Barrier Schottky Rectifier (JBS). The turn-on voltage of the embedded structure 26 is 1V, and the turn-on voltage of the silicon carbide PN diode is 2.6V, so that the embedded structure 26 can be turned on under the condition of 1V in the reverse mode, thereby effectively reducing the turn-on voltage when the silicon carbide MOSFET structure is turned on in the reverse direction. In addition, the embedded structure 26 is a unipolar device structure, and almost no reverse recovery time exists when the device is turned off, so that the turn-off speed can be increased.
Alternatively, the embedded structure 26 may be disposed vertically with respect to the first surface 11, which may save a lateral area of the sic trench transistor compared to a case where the embedded structure 26 is disposed parallel with respect to the first surface 11.
In some embodiments, the embedded structure 26 may form an ohmic contact between the epitaxial layer 2 and the source of the source trench structure 23, a distance between the well region 25 and the bottom region 211 of the body region in a direction perpendicular to the silicon carbide substrate 1 is less than or equal to a first predetermined distance, and a distance between the body region 21 on both sides of the planar gate structure 24 in a direction parallel to the silicon carbide substrate 1 is less than or equal to a second predetermined distance.
The first preset distance and the second preset distance may be equal or unequal, and are not limited herein.
Since the distance between the well region 25 and the bottom region 211 of the body region in the direction perpendicular to the silicon carbide substrate 1 is less than or equal to a first predetermined distance, the distance between the body regions 21 on both sides of the gate trench structure 22 in the direction parallel to the silicon carbide substrate 1 is less than or equal to a second predetermined distance. The distance between the well region 25 and the bottom region 211 of the body region in the direction perpendicular to the silicon carbide substrate 1 is short, so that a significant pinch-off barrier can be formed, and further, since the distance between the body region 21 on both sides of the gate trench structure 22 in the direction parallel to the silicon carbide substrate 1 is short, the electrical stress borne by the embedded structure 26 when the silicon carbide MOSFET is forwardly blocked is further shielded, even if the embedded structure 26 is a pure resistive structure, the embedded structure 26 is an ohmic contact formed by the epitaxial layer 2 and the source of the source trench structure 23, and can not become a current leakage channel when the silicon carbide MOSFET is forwardly blocked, and at the same time, in a reverse mode of the silicon carbide MOSFET, becomes a current conduction channel, so that a reverse conduction voltage drop is reduced, and almost no reverse recovery time is left when the silicon carbide MOSFET is turned off, so that the turn-off speed can be improved.
In some embodiments, the silicon carbide substrate 1 may further include a second surface 12 opposite the first surface 11, and the second surface 12 may be provided with the drain structure 3.
In order to make the current conduction more uniform, in some embodiments, the gate layer 221 of the gate trench structure 22 is connected to the gate layer 221 of the planar gate structure 24 at the predetermined crystal plane of the gate trench structure 22.
The predetermined crystal plane may be a crystal plane having the smallest channel mobility. The gate trench structure 22 generally has the crystal plane with the smallest channel mobility (for example, the < -1 > plane to the 120> plane), and if the channel on this crystal plane is conducted simultaneously with the channels on other crystal planes, the current imbalance problem may be caused, and instead of disposing the source above the crystal plane with the smallest channel mobility in the gate trench structure 22 and contacting the source trench structure 23, disposing the polysilicon in the gate trench structure 22 and connecting the polysilicon to the planar gate structure 24 may balance the electron distribution on the channels of different crystal planes, so as to make the current conduction more uniform.
It is noted that the first doping type is N-type and the second doping type is P-type in this embodiment. However, in actual practice, the silicon carbide substrate 1 is not limited to the N-type, and may be the P-type. When the silicon carbide substrate 1 is of a P-type, the conductivity types of the structures of the epitaxial layer 2, the body region 21, the well region 25, the second doped region 251, and the like also change accordingly.
While the application has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the application. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. The present application is not intended to be limited to the particular embodiments disclosed herein but is to cover all embodiments that may fall within the scope of the appended claims.

Claims (3)

1. A silicon carbide trench gate transistor, comprising:
a silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface; an epitaxial layer of a first doping type is arranged on the first surface;
a plurality of second doping type body regions arranged at intervals are embedded in the epitaxial layer; the body region includes a bottom region and a side region connected to one end of the bottom region;
a plurality of gate trench structures, a plurality of source trench structures, a plurality of planar gate structures, and a plurality of well regions formed on a surface of the epitaxial layer away from the first surface; wherein the source trench structure is in contact with the side region and a portion of the bottom region; the grid groove structure is positioned between the adjacent body regions; the planar gate structure is positioned on one side of the source electrode groove structure far away from the gate electrode groove structure; the gate layer of the planar gate structure is electrically connected with the gate layer in the gate groove structure; the well region of the second doping type is arranged in a spacing region between the grid electrode groove structure and the source electrode groove structure and is connected with one end of the side region; forming a second doping region of the first doping type in the well region close to the side face of the grid electrode groove structure and the well region on one side of the source electrode groove structure far away from the grid electrode groove structure;
the first doping type is opposite to the second doping type;
an embedded structure is arranged on the side face, far away from the side area, of the source electrode groove structure;
the embedded structure is formed by Schottky contact between the epitaxial layer and the source electrode of the source electrode groove structure;
or the embedded structure is that the epitaxial layer and a source electrode of the source electrode groove structure form ohmic contact, the distance between the well region and the body region in the direction vertical to the silicon carbide substrate is smaller than or equal to a first preset distance, and the distance between the body regions on two sides of the planar gate structure in the direction parallel to the silicon carbide substrate is smaller than or equal to a second preset distance.
2. The silicon carbide trench gate transistor of claim 1, wherein the silicon carbide substrate further comprises a second surface opposite the first surface, the second surface being provided with a drain structure.
3. A method of manufacturing a silicon carbide trench-gate transistor, comprising:
providing a silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface; an epitaxial layer of a first doping type is arranged on the first surface;
carrying out ion doping of a second doping type on the surface, far away from the first surface, of the epitaxial layer to form a plurality of first doping regions of the second doping type, which are arranged at intervals and buried in the epitaxial layer;
performing groove etching on the surface of the epitaxial layer far away from the first surface, so that the first doping region forms a body region comprising a bottom region and a side region connected with one end of the bottom region, forms a first groove in contact with the side region and part of the bottom region of the body region, and forms a second groove between adjacent body regions;
carrying out ion doping of the second doping type on the surface, far away from the first surface, of the epitaxial layer to form a well region of the second doping type;
forming a second doping area of the first doping type in the well area close to the side face of the second groove and the well area on the side, far away from the second groove, of the first groove;
forming a gate trench structure in the second trench and forming a planar gate structure in a surface region, away from the first surface, of the epitaxial layer on one side, away from the second trench, of the first trench; the gate layer of the planar gate structure is electrically connected with the gate layer in the gate trench structure;
filling a metal material into the first trench to form a source trench structure;
before filling a metal material into the first trench to form a source trench structure, the method further includes:
forming an embedded structure on a side of the first trench away from the side region;
the embedded structure is formed by Schottky contact between the epitaxial layer and the source electrode of the source electrode groove structure;
or the embedded structure is that the epitaxial layer and a source electrode of the source electrode groove structure form ohmic contact, the distance between the well region and the body region in the direction vertical to the silicon carbide substrate is smaller than or equal to a first preset distance, and the distance between the body regions on two sides of the planar gate structure in the direction parallel to the silicon carbide substrate is smaller than or equal to a second preset distance.
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CN108538910A (en) * 2018-02-13 2018-09-14 株洲中车时代电气股份有限公司 Igbt chip with composite grid
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