CN107863378B - Super junction MOS device and manufacturing method thereof - Google Patents
Super junction MOS device and manufacturing method thereof Download PDFInfo
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- CN107863378B CN107863378B CN201710826804.0A CN201710826804A CN107863378B CN 107863378 B CN107863378 B CN 107863378B CN 201710826804 A CN201710826804 A CN 201710826804A CN 107863378 B CN107863378 B CN 107863378B
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Abstract
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a super junction MOS device and a manufacturing method thereof. According to the invention, the grid polycrystalline region and the P-type region are vertically arranged, when reverse bias voltage is applied to the drain electrode, PN junctions formed by the P-type region and the N-type region are reversely biased, charges compensate each other to form a depletion layer, so that the P-type region and the N-type region can be completely depleted as long as the doping concentration and the size of the P-type region and the N-type region are reasonably selected, the field intensity is distributed to the whole depletion layer region to form an evenly distributed electric field, and therefore, the voltage withstand capability of the device is greatly improved, and the doping concentration of the drift region is not limited by breakdown voltage at the moment, so that the on resistance of the device can be greatly reduced, and the introduction of the N-type epitaxial layer can effectively improve the anti-interference capability of the super junction MOSFET; the manufacturing process method of the invention can be completely compatible with the existing super junction MOSFET process, has low cost, novel structure and good electrical characteristics, anti-interference capability and reliability.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a super junction MOS device and a manufacturing method thereof.
Background
Among power devices, power MOSFETs have found very wide application due to their superior performance. The power MOSFET energy loss mainly includes switching loss and on-state loss, which is relatively small because it is a multi-sub conductive unipolar device; on-state power consumption is relatively high, and on-state internal resistance Ron must be reduced to reduce on-state loss; the direction of development of power MOSFETs is therefore how to effectively reduce the on-resistance. However, the breakdown voltage and on-resistance in power MOSFETs are contradictory, because the high withstand voltage has a low concentration and a thicker drift region; and as the thickness of the drift region increases and the concentration decreases, the resistance of the drift region, which is the main part of the on-resistance of the device, increases, resulting in a large increase in the on-resistance. In general, the on-resistance increases with breakdown voltage about 2.5 times; on the other hand, the characteristic on-resistance of the power MOSFET device structure according to the traditional theory is limited by breakdown voltage, and the silicon limit is limited, so that the silicon limit can be only infinitely accessed but cannot be broken through, and a plurality of novel device structures are continuously developed.
The early 90 s at the end of the 80 s of the 20 th century put forward a new concept of "superjunction" by the stars bond, which breaks the limitation of "silicon limit" theoretically. With the continued development of semiconductor technology, the first power MOSFET in the world based on the superjunction concept was manufactured by siemens in 1998 and named CoolMOS, and then commercialized by the semiconductor company intel. Although each of the international companies hereafter introduced its own superjunction power MOSFET products such as MDmesh from ST company, superMOS, superFET from Fairchild company, etc. However, since CoolMOS is the first superjunction-based power MOSFET in the world, and is causing a very large bombard internationally at that time; therefore, coolMOS is hereafter referred to as a term for superjunction MOSFETs, and superjunction-based power MOSFETs are collectively referred to as CoolMOS.
The revolutionary breakthrough of CoolMOS is that the contradiction between breakdown voltage and on-resistance is greatly relieved, so that the relation between the on-resistance and the breakdown voltage is greatly improved, and the traditional 2.5 power relation is changed into a linear relation. Therefore, on-resistance can be reduced by more than 80% on the same chip area, the traditional silicon limit is broken at one time, and the on-resistance control method has the advantage of high switching speed.
Compared with the traditional VDMOS structure, the super-junction structure is inserted into the P-type region in the epitaxial layer, namely, a structure in which the P-type region and the N-type region alternately appear in the drift region is formed. Therefore, the high-voltage power supply has the characteristics of low on-resistance and high switching speed, so that the on-loss and the switching loss are greatly reduced. But this also presents challenges for application engineers, such fast turn-off speeds can cause oscillations in the switching and thus EMI overscaling, thus requiring improvements and optimization in layout and current design
Disclosure of Invention
In view of the above, the present invention is mainly directed to a super junction MOS device and a method for manufacturing the same.
The embodiment of the invention provides a super-junction MOS device, which consists of at least one single cell device, wherein each single cell device comprises a drain electrode region, an N+ monocrystalline silicon substrate, an N-epitaxial layer, a P-type region, an N-type epitaxial layer, a P-type well region layer, an N+ source region layer, an insulating medium layer and a source metal region layer, wherein the N+ monocrystalline silicon substrate and the N-epitaxial layer are positioned above the drain electrode region, the P-type region is positioned above the N-epitaxial layer, the N-type epitaxial layer is positioned above the P-type epitaxial layer, the P-type well region layer is positioned above the N+ well region layer, the N+ source region layer is positioned above the insulating medium layer, and the source metal region layer is positioned above the insulating medium layer, and the super-junction MOS device further comprises:
a gate oxide layer in contact with the n+ source region layer and the P-type well region layer;
the polysilicon layer is contacted with the gate oxide layer, and the top and the side wall are respectively contacted with the insulating medium layer;
the contact hole penetrates through the insulating medium layer and extends to the N-type epitaxial layer, is in contact with the N-type epitaxial layer, the N+ source electrode region layer and the P-type well region layer, is filled with metal, and the top end of the metal is connected with the source electrode metal region layer;
the bottom of the grid polycrystalline region is contacted with the N+ source region layer and is alternately contacted with the P-type region and the N-epitaxial layer, and the top and the side wall are respectively contacted with the insulating medium layer.
In the above scheme, the doping concentration and the size of the P-type region are matched with those of the N-epitaxial layer for achieving charge balance.
In the above scheme, the gate polycrystalline region is perpendicularly intersected with the P-type region.
In the above scheme, the N-type epitaxial layer is located above the P-type region and the N-epitaxial layer.
In the above scheme, the bottom of the gate polycrystalline region is in contact with the n+ source region layer and is alternately in contact with the P-type region and the N-epitaxial layer.
In the above scheme, the top and the side wall of the gate polycrystalline region are in contact with the insulating medium layer.
In the above scheme, the polysilicon layer is N-type heavily doped polysilicon.
The embodiment of the invention also provides a manufacturing method of the super junction MOS device according to any one of the schemes, which is characterized by comprising the following steps:
growing an N-epitaxial layer with low doping concentration of the first conductivity type on an N+ monocrystalline silicon substrate with high doping concentration of the first conductivity type;
after a first dielectric layer grows on the surface of the N-epitaxial layer, photoetching exposure is carried out on the first dielectric layer, and a deep groove region pattern is defined;
removing the first dielectric layer which is not protected by the photoresist by dry etching, exposing the N-epitaxial layer corresponding to the pattern of the deep trench region, and removing the photoresist, wherein the first dielectric layer which is reserved is used as a first hard mask;
forming deep trenches on the surface of the N-epitaxial layer by taking the first hard mask as a blocking layer, and then forming the P-type region through a backfilling and back etching process;
growing an N-type epitaxial layer with the thickness of about 5um on the surfaces of the N-epitaxial layer and the P-type region;
growing a gate oxide layer on the surface of the N-type epitaxial layer through an oxidation process, and depositing a polysilicon layer through an LPCVD process;
exposing the polycrystalline silicon layer through a photoetching process to define a grid polycrystalline layer region, removing polycrystalline silicon which is not protected by photoresist through dry etching to expose an N-type epitaxial layer corresponding to a source region, and removing the photoresist to form the grid polycrystalline layer region; wherein the gate poly region vertically crosses the P-type region;
defining a P-type well region injection region through a photoetching process, implanting doping elements through ions, activating impurities through annealing push-well and forming a P-type well region;
defining an N+ source region injection region through a photoetching process, implanting doping elements through ions, activating impurities through annealing and forming an N+ electrode source region;
depositing an insulating medium layer on the surface of the N+ source electrode region layer, wherein the insulating medium layer is a silicon dioxide layer, a silicon nitride layer or a composite layer of the silicon dioxide layer and the silicon nitride layer;
carrying out dry etching on the insulating dielectric layer above the N+ source electrode region layer, penetrating the insulating dielectric layer, extending to the P-type well region and the source electrode region, and forming a contact hole;
firstly depositing a metal titanium bonding layer, depositing a titanium nitride barrier layer on the metal titanium bonding layer, then depositing a tungsten metal layer and an aluminum metal layer, wherein the side surface end of the contact hole is in contact with the insulating medium layer, and the metal titanium bonding layer and the titanium nitride barrier layer which are positioned at the bottom surface end of the contact hole form an N+ source electrode ohmic contact layer and a P-type well ohmic contact layer with the N+ source electrode region layer and the P-type well region;
forming a source metal region layer by depositing metal on the upper surface of the insulating medium layer, wherein the contact hole is connected with the source metal region layer by contacting the source metal region layer to form a source metal electrode;
photoetching is carried out on the source metal area layer, and a source metal electrode area of the MOS tube unit cell array area and a grid metal electrode area at the periphery of the MOS tube unit cell array area are protected by photoresist, namely a source metal electrode area and a grid metal electrode area pattern are defined;
selectively removing the source metal region layer which is not protected by the photoresist by adopting a dry etching method, exposing the third dielectric layer which is used as an insulating dielectric layer, removing the photoresist, forming a MOS tube source metal electrode by the left source metal region layer positioned in the unit cell array region, and forming a MOS tube gate metal electrode by the left source metal region layer positioned at the periphery of the unit cell array region;
and depositing a metal layer on the bottom surface of the N+ monocrystalline silicon substrate to form a drain region, wherein the metal layer forms a metal layer of the drain region on the back surface of the MOS tube.
In the above scheme, the metal is deposited on the upper surface of the insulating dielectric layer to form the source metal region layer, specifically: and depositing metal tungsten on the upper surface of the insulating dielectric layer, filling the contact hole with the metal tungsten, selectively removing the metal tungsten by adopting a dry etching method to expose the dielectric layer serving as the insulating dielectric layer, filling tungsten in the contact hole, and then depositing an aluminum layer, or an aluminum layer doped with copper and silicon.
In the above scheme, the metal is deposited on the upper surface of the insulating dielectric layer to form the source metal region layer, specifically: and depositing an aluminum layer or an aluminum layer doped with copper and silicon on the upper surface of the insulating dielectric layer, and filling the contact hole.
Compared with the prior art, the grid polycrystalline region and the P-type region are vertically arranged, when the reverse bias voltage is applied to the drain electrode, PN junctions formed by the P-type region and the N-type region are reversely biased, charges compensate each other, a depletion layer is formed, the P-type region and the N-type region can be completely depleted as long as the doping concentration and the size of the P-type region and the N-type region are reasonably selected (namely, the charge balance is achieved), the field intensity is distributed to the whole depletion layer region, and an evenly distributed electric field is formed, so that the voltage withstand capability of the device is greatly improved; the doping concentration of the drift region is not limited by breakdown voltage, so that the on-resistance of the device can be greatly reduced, and the introduction of the N-type epitaxial layer can effectively improve the anti-interference capability of the super-junction MOSFET; the manufacturing process method of the invention can be completely compatible with the existing super junction MOSFET process, has low cost, novel structure and good electrical characteristics, anti-interference capability and reliability.
Drawings
Fig. 1 to 3 are schematic plan and cross-sectional (X, Y direction) structures of the present invention.
Wherein 1 is an N+ monocrystalline silicon substrate; 2 is an N-epitaxial layer; 3 is a deep trench; 4 is a P-type region; 5 is an N-type epitaxial layer; 6 is a gate oxide layer; 7 is a polysilicon layer; 8 is a source region; 9 is a P-type well region layer; 10 is an insulating dielectric oxide layer; 11 is a contact hole; 12 is a metal contact layer; 13 is a source region metal region layer; and 14 is a backside drain region metal layer.
Fig. 4-16 are schematic views of the process steps of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The embodiment of the invention provides a super junction MOS device, as shown in figures 1-3, which consists of at least one single cell device, wherein each single cell device comprises a drain region, an N+ monocrystalline silicon substrate, an N-epitaxial layer, a P-type region, an N-type epitaxial layer, a P-type well region layer, an N+ source region layer, an insulating medium layer and a source metal region layer, wherein the N+ monocrystalline silicon substrate is positioned above the drain region, the P-type region is positioned above the N-epitaxial layer, the P-type epitaxial layer is positioned above the P-type epitaxial layer, the P-type well region layer is positioned above the P-type well region layer, the N+ source region layer is positioned above the N+ source region layer, the source metal region layer is positioned above the insulating medium layer, and the super junction MOS device further comprises:
a gate oxide layer in contact with the n+ source region layer and the P-type well region layer;
the polysilicon layer is contacted with the gate oxide layer, and the top and the side wall are respectively contacted with the insulating medium layer;
the contact hole penetrates through the insulating medium layer and extends to the N-type epitaxial layer, is in contact with the N-type epitaxial layer, the N+ source electrode region layer and the P-type well region layer, is filled with metal, and the top end of the metal is connected with the source electrode metal region layer;
the bottom of the grid polycrystalline region is contacted with the N+ source region layer and is alternately contacted with the P-type region and the N-epitaxial layer, and the top and the side wall are respectively contacted with the insulating medium layer.
The doping concentrations and dimensions of the P-type region and the N-epi layer must be chosen to be reasonable (i.e., to achieve charge balance), so that complete depletion of both can be achieved, and the field strength is distributed throughout the depletion region, forming a uniformly distributed electric field.
The gate poly region perpendicularly crosses the P-type region.
The N-type epitaxial layer is located above the P-type region and the N-epitaxial layer.
And growing a layer of N-type epitaxial layer with about 5um on the surfaces of the N-epitaxial layer and the P-type region, wherein the doping concentration of the N-type epitaxial layer is higher than that of the N-epitaxial layer, so that the anti-interference capability of the device can be effectively improved.
And the bottom of the grid polycrystalline region is contacted with the N+ source electrode region layer and is alternately contacted with the P-type region and the N-epitaxial layer.
The top and the side wall of the grid polycrystalline region are in contact with the insulating medium layer.
The polysilicon layer is N-type heavily doped polysilicon.
The embodiment of the invention provides a manufacturing method of a super junction MOS device, which comprises the following specific implementation steps as shown in figures 4-16:
1. the epitaxial wafer structure comprises an N-type heavily doped semiconductor substrate 1 and an N-type lightly doped epitaxial layer 2;
2. deep trenches 3 are formed on the surface of the N-type lightly doped epitaxial layer, and then a P-type epitaxial layer is formed through backfill back etching process
A shaped region 4;
3. growing an N-type epitaxial layer 5 on the surfaces of the N-type epitaxial layer and the P-type region;
4. growing a gate oxide layer 6 on the surface of the N-type epitaxial layer;
5. depositing an N-type heavily doped polysilicon layer 7 on the surface of the gate oxide layer;
6. defining a polycrystalline grid region by photoetching, opening the region to be etched by exposing, and removing the polycrystalline silicon layer and the grid oxide layer on the top of the epitaxial wafer by dry etching;
7. forming a P-type well region layer 9 on the surface of the N-type epitaxial layer by ion implantation in a photoetching mode, and activating doping elements by an annealing process;
8. defining a source region by photoetching, forming a source region 8 by ion implantation, and activating doping elements by an annealing process;
9. forming an insulating dielectric oxide layer 10 on the surface of the N-type epitaxial layer by depositing silicon dioxide; forming a contact hole 11 by dry etching;
10. then depositing a metallic titanium bonding layer, depositing a titanium nitride barrier layer on the metallic titanium bonding layer, and then depositing a tungsten metal layer; a metal contact layer 12 is formed in the contact hole by annealing.
11. Finally, a dry etching method is adopted to selectively remove the source metal region layer 13 which is not protected by photoresist, so as to form a metal electrode layer of the source region of the MOS tube and a metal electrode of the gate electrode of the MOS tube, which is formed by the source metal region layer positioned at the periphery of the unit cell array region; and depositing a metal layer on the bottom surface of the N+ monocrystalline silicon substrate to form a drain region, wherein the metal layer forms a metal layer 14 of the drain region on the back surface of the MOS tube.
In the traditional high-voltage device, the on-resistance mainly comes from the resistance of the drift region, and meanwhile, the drift region is also a voltage-resistant layer of the device; in order to improve the withstand voltage of the device, the thickness of the drift region must be increased and the concentration of the drift region reduced, and the principle of superjunction theory is to use a plurality of alternative PN structures appearing in the drift region as a high-voltage drift layer, so as to improve the doping concentration of the drift region, greatly reduce the on-resistance, and not change the breakdown voltage of the device.
According to the invention, the grid polycrystalline region and the P-type region are vertically arranged, when reverse bias voltage is applied to the drain electrode, PN junctions formed by the P-type region and the N-type region are reversely biased, charges compensate each other, a depletion layer is formed, and as long as the doping concentration and the size of the P-type region and the N-type region are reasonably selected (namely, the charge balance is achieved), the two regions can be completely depleted, the field intensity is distributed to the whole depletion layer region, and an evenly distributed electric field is formed, so that the voltage-withstanding capability of the device is greatly improved. Since the doping concentration of the drift region is not limited by the breakdown voltage at this time, the on-resistance of the device can be greatly reduced. The manufacturing process method of the invention can be completely compatible with the existing super junction MOSFET process, has low cost, novel structure and good electrical characteristics, anti-interference capability and reliability.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (3)
1. The manufacturing method of the super junction MOS device is characterized by comprising the following steps:
growing an N-epitaxial layer with low doping concentration of the first conductivity type on an N+ monocrystalline silicon substrate with high doping concentration of the first conductivity type;
after a first dielectric layer grows on the surface of the N-epitaxial layer, photoetching exposure is carried out on the first dielectric layer, and a deep groove region pattern is defined;
removing the first dielectric layer which is not protected by the photoresist by dry etching, exposing the N-epitaxial layer corresponding to the pattern of the deep trench region, and removing the photoresist, wherein the first dielectric layer which is reserved is used as a first hard mask;
forming deep trenches on the surface of the N-epitaxial layer by taking the first hard mask as a blocking layer, and then forming the P-type region through a backfilling and back etching process;
growing a layer of N-type epitaxial layer with the thickness of 5um on the surfaces of the N-epitaxial layer and the P-type region;
growing a gate oxide layer on the surface of the N-type epitaxial layer through an oxidation process, and depositing a polysilicon layer through an LPCVD process;
exposing the polycrystalline silicon layer through a photoetching process to define a grid polycrystalline layer region, removing polycrystalline silicon which is not protected by photoresist through dry etching to expose an N-type epitaxial layer corresponding to a source region, and removing photoresist to form a grid polycrystalline layer region, wherein the grid polycrystalline layer region and the P-type region are vertically crossed;
defining a P-type well region injection region through a photoetching process, implanting doping elements through ions, activating impurities through annealing push-well and forming a P-type well region;
defining an N+ source region injection region through a photoetching process, doping elements through ion injection, activating impurities through annealing and forming an N+ source region;
depositing an insulating medium layer on the surface of the N+ source electrode region layer, wherein the insulating medium layer is a silicon dioxide layer, a silicon nitride layer or a composite layer of the silicon dioxide layer and the silicon nitride layer;
carrying out dry etching on the insulating dielectric layer above the N+ source electrode region layer, penetrating the insulating dielectric layer, extending to the P-type well region and the source electrode region, and forming a contact hole;
firstly depositing a metal titanium bonding layer, depositing a titanium nitride barrier layer on the metal titanium bonding layer, then depositing a tungsten metal layer and an aluminum metal layer, wherein the side surface end of the contact hole is in contact with the insulating medium layer, and the metal titanium bonding layer and the titanium nitride barrier layer which are positioned at the bottom surface end of the contact hole form an N+ source ohmic contact layer and an N+ source ohmic contact layer of a P-type well together with the N+ source region layer and the P-type well region;
depositing metal on the upper surface of the insulating medium layer to form a source metal region layer, wherein the contact hole is connected with the source metal region layer;
photoetching is carried out on the source metal area layer, and a source metal electrode area of the MOS tube unit cell array area and a grid metal electrode area at the periphery of the MOS tube unit cell array area are protected by photoresist, namely a source metal electrode area and a grid metal electrode area pattern are defined;
selectively removing the source metal region layer which is not protected by the photoresist by adopting a dry etching method, exposing the third dielectric layer which is used as an insulating dielectric layer, removing the photoresist, forming a MOS tube source metal electrode by the left source metal region layer positioned in the unit cell array region, and forming a MOS tube gate metal electrode by the left source metal region layer positioned at the periphery of the unit cell array region;
and depositing a metal layer on the bottom surface of the N+ monocrystalline silicon substrate to form a drain region, wherein the metal layer forms a metal layer of the drain region on the back surface of the MOS tube.
2. The method of claim 1, wherein depositing metal on the upper surface of the insulating dielectric layer forms a source metal region layer, specifically:
and depositing metal tungsten on the upper surface of the insulating dielectric layer, filling the contact hole with the metal tungsten, selectively removing the metal tungsten by adopting a dry etching method to expose the dielectric layer serving as the insulating dielectric layer, filling tungsten in the contact hole, and then depositing an aluminum layer, or an aluminum layer doped with copper and silicon.
3. The method of claim 1, wherein depositing metal on the upper surface of the insulating dielectric layer forms a source metal region layer, specifically:
and depositing an aluminum layer or an aluminum layer doped with copper and silicon on the upper surface of the insulating dielectric layer, and filling the contact hole.
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