CN213124446U - Shielding grid power MOS device - Google Patents
Shielding grid power MOS device Download PDFInfo
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- CN213124446U CN213124446U CN202022565876.4U CN202022565876U CN213124446U CN 213124446 U CN213124446 U CN 213124446U CN 202022565876 U CN202022565876 U CN 202022565876U CN 213124446 U CN213124446 U CN 213124446U
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Abstract
The utility model is suitable for a MOS device technical field provides a shielding grid power MOS device, include: the transistor comprises source metal, an interlayer film arranged below the source metal, a source region arranged below the interlayer film, a body region arranged below the source region, an epitaxial layer arranged below the body region, a silicon wafer arranged below the epitaxial layer, drain metal arranged below the silicon wafer and a groove formed by etching; the trench penetrates through the source region and the body region in sequence and is arranged in the epitaxial layer; depositing undoped polysilicon inside the trench and etching to form a shield gate and depositing heavily doped polysilicon to form a gate; the grid electrode is divided into two parts; and a bottom ion implantation area is arranged on the outer side of the bottom of the groove and is electrically connected with the source electrode. The utility model discloses because the grid is divided into two parts and reduces the grid source electric capacity and the miller electric capacity of MOS device. And an interlayer oxide layer is not arranged between the grid electrode and the shielding grid, so that the reliability problem of the grid oxide layer is avoided.
Description
Technical Field
The utility model belongs to the technical field of the MOS device, especially, relate to a shielding grid power MOS device.
Background
In the field of semiconductor power devices, the existing relatively advanced power MOSFET (MOS transistor) with a shielded gate structure brings about a substantial reduction in gate-drain capacitance and a substantial increase in breakdown voltage compared to the conventional trench MOSFET without a shielded gate structure, thereby enabling the device to have lower power consumption and switching speed. The excellent performance of trench MOSFETs with shielded gate structures makes them highly advantageous in applications.
In the existing shielded gate power MOS, on the basis of the structure of the conventional MOS, a shield gate is formed by adding one-time poly deposition and etching under a trench gate, and the shield gate is generally connected to a source potential to shield a capacitance between the gate and an opposite drain, i.e., a miller capacitance. By adopting the shielding grid structure, the Miller capacitance can be greatly reduced, and the switching speed of the device is improved. Meanwhile, the breakdown voltage of the MOS can be obviously improved by utilizing the charge balance effect of the shielding grid, and the on-resistance of the device is reduced. In the actual manufacturing process, when the gate oxide layer is long, the gate oxide layer near the shield gate will grow thinner due to the polysilicon shield gate, which may cause the leakage current of the gate oxide to increase, the withstand voltage to decrease, and the reliability problem of the gate oxide layer to be brought. And the existing grid structure is simpler and has poorer reducing effects on the Miller capacitance and the grid source capacitance.
SUMMERY OF THE UTILITY MODEL
An embodiment of the utility model provides a shielding grid power MOS device aims at solving the problem that exists among the prior art.
The embodiment of the utility model provides a shielding grid power MOS device, include:
the transistor comprises source metal, an interlayer film arranged below the source metal, a source region arranged below the interlayer film, a body region arranged below the source region, an epitaxial layer arranged below the body region, a silicon wafer arranged below the epitaxial layer, drain metal arranged below the silicon wafer and a groove formed by etching;
the groove sequentially penetrates through the source region and the body region and is arranged inside the epitaxial layer;
depositing undoped polysilicon inside the trench and etching to form a shield gate and depositing heavily doped polysilicon to form a gate;
the grid electrode is divided into two parts;
and a bottom ion implantation area is arranged on the outer side of the bottom of the groove and is electrically connected with the source electrode.
Furthermore, an interlayer oxide layer is not arranged between the grid electrode and the shielding grid.
Still further, a contact metal is provided in the middle, and the source metal is connected to the body region through the contact metal through the interlayer film and the source region.
Furthermore, the number of the grooves is two, the grooves are respectively arranged on two sides of the contact metal at intervals, and the arrangement of the two grooves is the same.
Furthermore, a contact implantation region is arranged in each groove and above part of the source region, and the bottom ion implantation region is electrically connected with the source region through the contact implantation region.
The utility model discloses the beneficial effect who reaches: the bottom ion injection region and the current carriers in the epitaxial layer are mutually depleted, and the bottom ion injection region is electrically connected with the source region, so that the depletion of the current carriers is further increased when the epitaxial layer is cut off, and the grid leakage is further shielded, therefore, the grid leakage capacitance is further reduced on the basis of a shielded grid structure, and meanwhile, the source leakage breakdown voltage is further increased. Meanwhile, the grid electrode is divided into two parts, so that the grid source capacitance and the Miller capacitance of the MOS device are further reduced. And an interlayer oxide layer is not arranged between the grid electrode and the shielding grid, so that the reliability problem of the grid oxide layer is avoided.
Drawings
Fig. 1 is a schematic structural diagram of a shielded gate power MOS device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the utility model provides a mutually exhaust through the carrier in bottom ion implantation district and the epitaxial layer, bottom ion implantation district is connected with the source region electricity and is makeed the carrier exhaust further increase and obtain further shielding between the grid leak when ending, therefore makes it further reduce grid leak electric capacity on the basis of band shield bars structure, has further increased source leakage breakdown voltage simultaneously again. Meanwhile, the grid electrode is divided into two parts, so that the grid source capacitance and the Miller capacitance of the MOS device are further reduced. And an interlayer oxide layer is not arranged between the grid electrode and the shielding grid, so that the reliability problem of the grid oxide layer is avoided.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a shielded gate power MOS device according to an embodiment of the present invention.
The shielding grid power MOS device comprises source metal, an interlayer film arranged below the source metal, a source region arranged below the interlayer film, a body region arranged below the source region, an epitaxial layer arranged below the body region, a silicon wafer arranged below the epitaxial layer, drain metal arranged below the silicon wafer and a groove formed by etching. The groove sequentially penetrates through the source region and the body region and is arranged inside the epitaxial layer. And depositing undoped polysilicon inside the groove and etching to form a shielding gate (shielding electrode) and depositing heavily doped polysilicon to form a gate (switching electrode). The grid electrode (switch electrode) is divided into two parts. And a bottom ion implantation area is arranged on the outer side of the bottom of the groove and is electrically connected with the source electrode.
The doping type of the bottom ion implantation area is the same as that of the body area, the doping concentration of the bottom ion implantation area is higher than that of the epitaxial layer, and the bottom ion implantation area is located in the epitaxial layer. The bottom ion implantation region is an impurity diffusion region with medium concentration. The conductivity type of the bottom ion implantation region is the same as that of the body region.
The grid electrode (switch electrode) is divided into two parts, so that the grid source capacitance and the Miller capacitance of the MOS device are further reduced.
In one embodiment of the present invention, there is no interlayer oxide layer between the gate (switching electrode) and the shielding gate (shielding electrode). Therefore, when the gate oxide layer close to the shielding gate (shielding electrode) grows thinner, the problems of increased leakage current and reduced voltage resistance of the gate oxide and reliability of the gate oxide layer are avoided, the problem of reliability of the gate oxide layer caused by the problem is solved, and the manufacturing process of the structure of the shielding gate (shielding electrode) is simplified.
In an embodiment of the present invention, the shielded gate power MOS device further includes a contact metal disposed in the middle, and the source metal passes through the contact metal to pass through the interlayer film and the source region and the body region. This enables the source metal to be connected to the interlayer film, the source region, and the body region, respectively.
The utility model discloses an in the embodiment, the quantity of slot is two, and the interval setting is in respectively contact metal both sides, the setting of two slots is the same. Therefore, the function of the shielding grid (shielding electrode) of the MOS device can be improved doubly, and the performance of the MOS device is further improved.
The utility model discloses an in the embodiment, keep away and partial source region top is provided with the contact implantation district in every ditch inslot, bottom ion implantation district passes through the contact implantation district with the source district electricity is connected. The contact injection region is a high-concentration groove superficial impurity diffusion region and is used for electrically connecting the bottom ion injection region and the source region through a contact hole process in the subsequent process.
The embodiment of the utility model provides an in, mutually exhaust through the carrier in bottom ion implantation district and the epitaxial layer, bottom ion implantation district is connected with the source region electricity and is makeed the carrier exhaust further increase and obtain further shielding between the grid leak when ending, therefore makes it further reduce grid leak electric capacity on the basis of taking shielding grid (shielding electrode) structure, has further increased source leakage breakdown voltage simultaneously again. Meanwhile, the grid electrode (the switch electrode) is divided into two parts, so that the grid source capacitance and the Miller capacitance of the MOS device are further reduced. And an interlayer oxide layer is not arranged between the grid electrode (switch electrode) and the shielding grid electrode (shielding electrode), so that the reliability problem of the grid oxide layer is avoided.
The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (5)
1. A shielded gate power MOS device, comprising: the transistor comprises source metal, an interlayer film arranged below the source metal, a source region arranged below the interlayer film, a body region arranged below the source region, an epitaxial layer arranged below the body region, a silicon wafer arranged below the epitaxial layer, drain metal arranged below the silicon wafer and a groove formed by etching;
the groove sequentially penetrates through the source region and the body region and is arranged inside the epitaxial layer;
depositing undoped polysilicon inside the trench and etching to form a shield gate and depositing heavily doped polysilicon to form a gate;
the grid electrode is divided into two parts;
and a bottom ion implantation area is arranged on the outer side of the bottom of the groove and is electrically connected with the source electrode.
2. The shielded gate power MOS device of claim 1 wherein there is no interlayer oxide between the gate and the shielded gate.
3. The shielded gate power MOS device of claim 1 further comprising a contact metal disposed in the middle, the source metal being connected to the body region through the contact metal through the interlayer film and the source region.
4. The shielded gate power MOS device of claim 3 wherein said trenches are two in number and spaced apart on either side of said contact metal, the two trenches being disposed the same.
5. The shielded gate power MOS device of claim 4 wherein a contact implant region is disposed in each trench above a portion of the source region, the bottom ion implant region being electrically connected to the source region through the contact implant region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022565876.4U CN213124446U (en) | 2020-11-09 | 2020-11-09 | Shielding grid power MOS device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022565876.4U CN213124446U (en) | 2020-11-09 | 2020-11-09 | Shielding grid power MOS device |
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| CN213124446U true CN213124446U (en) | 2021-05-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115863398A (en) * | 2023-02-06 | 2023-03-28 | 苏州锴威特半导体股份有限公司 | Silicon carbide MOSFET and manufacturing method thereof |
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2020
- 2020-11-09 CN CN202022565876.4U patent/CN213124446U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115863398A (en) * | 2023-02-06 | 2023-03-28 | 苏州锴威特半导体股份有限公司 | Silicon carbide MOSFET and manufacturing method thereof |
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