CN217822819U - High-voltage power device - Google Patents
High-voltage power device Download PDFInfo
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- CN217822819U CN217822819U CN202221703868.4U CN202221703868U CN217822819U CN 217822819 U CN217822819 U CN 217822819U CN 202221703868 U CN202221703868 U CN 202221703868U CN 217822819 U CN217822819 U CN 217822819U
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Abstract
The application belongs to the technical field of semiconductors, provides a high-voltage power device, includes: the semiconductor device includes a semiconductor substrate, a plurality of vertical type device unit cells, and an isolation region. The plurality of vertical device unit cells are arranged on the semiconductor substrate and connected in parallel; the isolation region is arranged on the semiconductor substrate, is positioned between the adjacent vertical device unit cells and is used for reducing the parasitic capacitance of the vertical device unit cells. In the embodiment, the withstand voltage characteristic of the high-voltage power device is increased by connecting a plurality of vertical device unit cells in parallel, and the parasitic capacitance of the vertical device unit cells is reduced by arranging an isolation region between the vertical device unit cells, so that the switching speed of the high-voltage power device is increased.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a high-voltage power device.
Background
The groove power device has the characteristics of high integration level, low on-resistance, high switching speed and small switching loss, and is widely applied to various power management and switching conversion. With the development of industry, the climate environment is worse and worse due to global warming, and energy saving, carbon reduction and sustainable development are more and more important in various countries, so that the requirements on the power consumption and the conversion efficiency of power MOS devices are higher and higher, the power consumption mainly comprises conduction loss and switching loss, and the power consumption of the existing devices still has room for improvement.
In the prior art, generally, the voltage withstanding characteristic of the power devices is increased by connecting the power devices in parallel, but after the power devices are connected in parallel, although the high voltage withstanding characteristic of the power devices is improved, the parasitic capacitance of the power devices is also increased, and the switching speed of the power devices is reduced.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, embodiments of the present application provide a high-voltage power device, which can solve the problem of slow switching speed caused by an increase in parasitic capacitance of an existing parallel power device.
A first aspect of an embodiment of the present application provides a high-voltage power device, including:
a semiconductor substrate;
a plurality of vertical device cells arranged on the semiconductor substrate, the plurality of vertical device cells being connected in parallel;
and the isolation region is arranged on the semiconductor substrate, is positioned between the adjacent vertical device unit cells and is used for reducing the parasitic capacitance of the vertical device unit cells.
In one embodiment, the vertical-type device cell includes:
a gate metal layer;
the grid oxide layer is connected with the grid metal layer;
a source region connected to the gate oxide layer;
the source electrode oxidation layer is respectively connected with the source electrode region and the grid electrode oxidation layer;
and the drift layer is arranged on the semiconductor substrate and is connected with the source electrode oxidation layer.
In one embodiment, the vertical device cell is a symmetric structure.
In one embodiment, the depth of the isolation region is less than the thickness of the drift layer and greater than the thickness of the source oxide layer.
In one embodiment, the thickness of the source region is less than the thickness of the source oxide layer.
In one embodiment, a plurality of the vertical device unit cells are arranged in an array, and the isolation region is shaped like a Chinese character 'jing'.
In one embodiment, the material of the semiconductor substrate is silicon carbide or gallium nitride.
In one embodiment, the isolation region is an etched channel.
In one embodiment, the isolation region is a P-type doped region.
In one embodiment, the isolation region is in contact with the gate oxide layer.
Compared with the prior art, the embodiment of the application has the advantages that: there is provided a high voltage power device comprising: the semiconductor device includes a semiconductor substrate, a plurality of vertical type device unit cells, and an isolation region. The plurality of vertical device unit cells are arranged on the semiconductor substrate and connected in parallel; the isolation region is arranged on the semiconductor substrate, is positioned between the adjacent vertical device unit cells and is used for reducing the parasitic capacitance of the vertical device unit cells. In this embodiment, the voltage withstanding characteristic of the high-voltage power device is increased by connecting a plurality of vertical device unit cells in parallel, and the parasitic capacitance of the vertical device unit cells is reduced by providing an isolation region in the vertical device unit cells, so as to increase the switching speed of the high-voltage power device.
Drawings
Fig. 1 is a schematic structural diagram of a conventional high-voltage power device;
fig. 2 is a schematic structural diagram of a high-voltage power device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a high-voltage power device according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means one or more unless specifically limited otherwise.
The groove power device has the characteristics of high integration level, low on-resistance, high switching speed and small switching loss, and is widely applied to various power management and switching conversion. With the development of industry, the climate environment is worse and worse due to global warming, and energy saving, carbon reduction and sustainable development are more and more important in various countries, so that the requirements on the power consumption and the conversion efficiency of power MOS devices are higher and higher, the power consumption mainly comprises conduction loss and switching loss, and the power consumption of the existing devices still has room for improvement.
In the prior art, the voltage withstanding characteristic of the power devices is generally increased by connecting the power devices in parallel, but after the power devices are connected in parallel, although the high voltage withstanding characteristic of the power devices is improved, the parasitic capacitance of the power devices is increased, and the switching speed of the power devices is reduced.
Referring to fig. 1, in a field application where the voltage requirement is 600V, engineers achieve the need for high voltage endurance by connecting multiple power devices 01 in parallel, and reduce the area (by about 40%) and achieve the advantage of lower channel resistance, but with an increase in parasitic capacitance of about 25% -40%, resulting in a reduction in the switching speed of the power devices.
In order to solve the above technical problem, an embodiment of the present application provides a high voltage power device, which is shown with reference to fig. 2, wherein the high voltage power device includes: a semiconductor substrate 10, a plurality of vertical-type device unit cells 20, and an isolation region 20.
Specifically, a plurality of vertical type device unit cells 20 are disposed on the semiconductor substrate 10, and the plurality of vertical type device unit cells 20 are connected in parallel; the isolation region 20 is disposed on the semiconductor substrate 10 and located between adjacent vertical device unit cells 20, and the isolation region 20 is used to reduce the parasitic capacitance of the vertical device unit cell 20.
In the present embodiment, by disposing a plurality of vertical type device unit cells 20 in parallel, the voltage of the power device can be increased. For example, in some application scenarios, when the power device is required to withstand a high voltage, for example, a voltage of 600V, a plurality of vertical device cells 20 need to be arranged in parallel, so as to meet the requirement of high withstand voltage of the power device. However, when the plurality of vertical device cells 20 are connected in parallel, the parasitic capacitance of the vertical device cells also increases, which may reduce the switching speed of the power device, and further affect the performance and stability of the power device.
In the present embodiment, the isolation region 20 is located between adjacent vertical-type device unit cells 20, and the isolation region 20 serves to reduce the parasitic capacitance of the vertical-type device unit cell 20. Specifically, the isolation region 20 is disposed between the parallel vertical device cells 20, and is configured to isolate the adjacent vertical device cells 20, reduce the parasitic capacitance of the vertical device cells 20, further reduce the parasitic capacitance of the high-voltage power device, increase the switching speed of the high-voltage power device, and improve the performance of the high-voltage power device.
In the present embodiment, the parasitic capacitance of the vertical-type device cell 20 can be reduced by providing the isolation region 20 between the adjacent vertical-type device cells 20, thereby reducing the parasitic capacitance of the high-voltage power device. It is understood that when the high voltage power device is connected in parallel to the plurality of vertical type device unit cells 20, an isolation region 20 is disposed between each adjacent vertical type device unit cell 20. That is, it can be understood that, in a specific application scenario, when there are three vertical device unit cells 20 connected in parallel, two isolation regions 20 need to be disposed between adjacent vertical device unit cells 20, respectively, so as to reduce the parasitic capacitance of the vertical device unit cell 20, further reduce the parasitic capacitance of the high-voltage power device, and further improve the switching speed of the power device.
In one embodiment, specifically, the semiconductor substrate 10 is an N-type substrate, which can be used as a drain of a high-voltage power device, and the semiconductor substrate 10 is doped with an N-type element with a concentration of 1e19/cm3, which can greatly reduce the resistance of the semiconductor substrate 10.
In one embodiment, referring to fig. 3, the vertical device unit cell 20 includes: a gate metal layer 21, a gate oxide layer 22, a source region 23, a source oxide layer 24, and a drift layer 25.
Specifically, the gate oxide layer 22 is connected to the gate metal layer 21; the source region 23 is connected to the gate oxide layer 22; the source oxide layer 24 is connected to the source region 23 and the gate oxide layer 22, respectively; the drift layer 25 is provided on the semiconductor substrate 10, and the drift layer 25 is connected to the source oxide layer 24.
In the present embodiment, the drift layer 25 located above the semiconductor substrate 10 is doped with N-type elements to form an N-type drift layer 25, the doping concentration and thickness of the drift layer 25 are set according to the breakdown voltage of the high-voltage power device, and generally, the thicker the drift layer 25 of the high-voltage power device, the higher the breakdown voltage, the smaller the doping concentration, the greater the resistance of the formed drift region, and the higher the breakdown voltage. The drift layer 25 is covered with a gate metal layer 21, the gate metal layer 21 is connected to the source region 23 through a contact hole, specifically, the contact hole penetrates through the gate oxide layer 22 and the source oxide layer 24 to connect the adjacent source region 23 and the gate metal layer 21, the leakage of the high-voltage power device mainly comes from the barrier height of the gate metal layer 21 and the drift layer 25, and the smaller the barrier height, the larger the leakage of the high-voltage power device.
In one embodiment, when electrons approach the interface between the gate metal layer 21 and the drift layer 25, a kind of mirror charge is generated, which lowers the barrier height between the gate metal layer 21 and the drift layer 25, thereby increasing the leakage of the high voltage power device.
In one embodiment, forming the deep trench in the drift layer 25 by deep trench etching reduces the contact area of the gate oxide layer 22 and the drift layer 25, which may result in reduced leakage of the high voltage power device. Because the source regions 23 are located at two sides of the schottky region formed between the gate oxide layer 22 and the drift layer 25, and the source regions 23 are connected to the gate oxide layer 22, the source regions 23 can completely deplete the drift region formed by the drift layer 25 at a lower voltage to shield the interface between the gate oxide layer 22 and the drift layer 25, and at this time, when the drain voltage continues to increase, the electric field intensity in the high-voltage power device does not increase in proportion.
In an embodiment, referring to fig. 3, the source region 23 is located in the deep trench, the source region 23 is doped with N-type elements to form the N-type source region 23, and the source oxide layer 24 is doped with P-type elements.
In one embodiment, referring to fig. 2, the vertical device cell 20 is a symmetrical structure.
Specifically, the vertical device unit cells 20 are symmetrically arranged, so that the occupied area of the high-voltage power device can be reduced under the condition of meeting the requirement of high-voltage characteristics of the high-voltage power device, the high-voltage power device is more miniaturized, and the application scenes of the high-voltage power device are increased. The vertical device unit cell 20 has a symmetrical structure, and it is understood that the vertical device unit cell 20 may be symmetrical left and right, symmetrical up and down, and the like.
In one embodiment, referring to fig. 3, the depth of the isolation region 20 is less than the thickness of the drift layer 25 and greater than the thickness of the source oxide layer 24.
In the present embodiment, the depth of the isolation region 20 is set to be smaller than the thickness of the drift layer 25, it can be understood that the isolation region 20 is formed in the drift layer 25 and is completely surrounded by the drift layer 25, the drift layers 25 of the adjacent vertical device unit cells 20 are connected or the adjacent vertical device unit cells 20 share the same drift layer 25, the isolation region 20 is located between the adjacent vertical device unit cells 20, the parasitic capacitance of the vertical device unit cells 20 can be reduced, and further, the parasitic capacitance of the high-voltage power device can be reduced, and further, it can be understood that the isolation region 20 disposed in the drift layer 25 reduces the parasitic capacitance of the vertical device unit cells 20 by reducing the parasitic capacitance between the source regions 23 of the vertical device unit cells 20 and the semiconductor substrate 10, so as to further reduce the parasitic capacitance of the high-voltage power device, and improve the switching speed of the high-voltage power device.
In one embodiment, referring to fig. 3, the source region 23 has a thickness less than the thickness of the source oxide layer 24.
Specifically, the drift region can be more uniform by setting the thickness of the source region 23 to be smaller than the thickness of the source oxide layer 24, which is beneficial to completely depleting the drift region at a lower voltage by the source region 23, so that the interface between the gate metal layer 21 and the drift layer 25 is shielded by pinching off the drift region in advance, the electric field strength of the interface between the gate metal layer 21 and the drift layer 25 is reduced, and the problem of breakdown voltage reduction caused by overhigh electric field strength of the interface between the gate metal layer 21 and the drift layer 25 in the process of increasing the reverse voltage of the high-voltage power device is avoided.
In one embodiment, referring to fig. 2, a plurality of vertical device unit cells 20 are arranged in an array, and the isolation regions 20 are shaped like a "well".
Specifically, in the present embodiment, the plurality of vertical device unit cells 20 are arranged in an array, the isolation region 20 is located between the adjacent vertical device unit cells 20, and the adjacent isolation regions 20 are extended to be in contact, it can be understood that, in a high voltage power device, a plurality of small isolation regions 20 may be extended and in contact to form one isolation region 20, and the formed isolation region 20 is in a "well" shape. By respectively arranging the isolation regions 20 between the adjacent vertical device cells 20 and forming the vertical device cells into a shape like a Chinese character 'jing', the parasitic capacitance of the vertical device cells 20 can be effectively reduced, and further the parasitic capacitance of the high-voltage power device is reduced, so that the switching speed of the high-voltage power device is increased.
In one embodiment, the material of the semiconductor substrate 10 is silicon carbide or gallium nitride. In the present embodiment, silicon carbide and gallium nitride have the advantages of high forbidden bandwidth (corresponding to high breakdown electric field and high power density), high electrical conductivity, high thermal conductivity, and the like.
In one embodiment, the isolation region 20 is an etched channel.
Specifically, deep trench etching is performed on the drift layer 25, and etching is performed on the drift layer 25 to form an etching channel; in this embodiment, the etching process may be dry etching or wet etching, and the depth and the width of the etching channel are determined according to specific parameters of the high-voltage power device.
In one embodiment, the isolation regions 20 are shallow trench isolations.
In one embodiment, the isolation region 20 is a P-type doped region.
In the present embodiment, the P-type doping material may be boron or gallium, wherein the doping method may be a high temperature diffusion method or an ion implantation method.
In one embodiment, the doping method is an ion implantation method, the ion implantation can be performed at a lower temperature (e.g., 400 ℃), high-temperature processing is avoided, and the ion implantation can accurately control the concentration and the junction depth by controlling the electrical conditions (current and voltage) during implantation, so that the control of the impurity distribution shape is better realized. And the impurity concentration is not limited by the solid solubility of the material. The ion implantation can select one element to implant, and avoid mixing other impurities.
In one embodiment, the isolation region 20 is in contact with a gate oxide layer 22. In this embodiment, by disposing the isolation region 20 in contact with the gate oxide layer 22, the parasitic capacitance of the vertical device unit cell 20 can be effectively reduced, and further, the parasitic capacitance of the high voltage power device is reduced, so as to increase the switching speed of the high voltage power device.
In one embodiment, the vertical device cell 20 is any one of an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or a BJT (Bipolar Junction Transistor).
The embodiment of the present application provides a high voltage power device including: the semiconductor device includes a semiconductor substrate, a plurality of vertical type device unit cells, and an isolation region. The plurality of vertical device unit cells are arranged on the semiconductor substrate and connected in parallel; the isolation region is arranged on the semiconductor substrate, is positioned between the adjacent vertical device unit cells and is used for reducing the parasitic capacitance of the vertical device unit cells. In this embodiment, the voltage withstanding characteristic of the high-voltage power device is increased by connecting a plurality of vertical device unit cells in parallel, and the parasitic capacitance of the vertical device unit cells is reduced by providing an isolation region in the vertical device unit cells, so as to increase the switching speed of the high-voltage power device.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
The units described as separate parts may or may not be physically separate, and the parts displaying data as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A high voltage power device, comprising:
a semiconductor substrate;
a plurality of vertical device cells arranged on the semiconductor substrate, the plurality of vertical device cells being connected in parallel;
and the isolation region is arranged on the semiconductor substrate, is positioned between the adjacent vertical device unit cells and is used for reducing the parasitic capacitance of the vertical device unit cells.
2. The high voltage power device of claim 1, wherein the vertical device unit cell comprises:
a gate metal layer;
the grid oxide layer is connected with the grid metal layer;
a source region connected to the gate oxide layer;
the source electrode oxidation layer is respectively connected with the source electrode region and the grid electrode oxidation layer;
and the drift layer is arranged on the semiconductor substrate and is connected with the source electrode oxidation layer.
3. The high voltage power device of claim 1, wherein the vertical device unit cells are of a symmetric structure.
4. The high voltage power device of claim 2, wherein a depth of the isolation region is less than a thickness of the drift layer and greater than a thickness of the source oxide layer.
5. The high voltage power device of claim 2, wherein a thickness of the source region is less than a thickness of the source oxide layer.
6. The high voltage power device according to claim 1, wherein the plurality of vertical device cells are arranged in an array, and the isolation region is shaped like a "well".
7. The high voltage power device according to claim 1, wherein the material of the semiconductor substrate is silicon carbide or gallium nitride.
8. The high voltage power device of claim 1, wherein the isolation region is an etched channel.
9. The high voltage power device of claim 1, wherein the isolation region is a P-type doped region.
10. The high voltage power device of claim 2, wherein the isolation region is in contact with the gate oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221703868.4U CN217822819U (en) | 2022-06-30 | 2022-06-30 | High-voltage power device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221703868.4U CN217822819U (en) | 2022-06-30 | 2022-06-30 | High-voltage power device |
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| CN217822819U true CN217822819U (en) | 2022-11-15 |
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| CN202221703868.4U Active CN217822819U (en) | 2022-06-30 | 2022-06-30 | High-voltage power device |
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