CN112234095B - Power MOSFET device with enhanced cell design - Google Patents
Power MOSFET device with enhanced cell design Download PDFInfo
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- 238000013461 design Methods 0.000 title claims abstract description 73
- 238000002347 injection Methods 0.000 claims abstract description 63
- 239000007924 injection Substances 0.000 claims abstract description 63
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 23
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
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- 238000010586 diagram Methods 0.000 description 21
- 230000000903 blocking effect Effects 0.000 description 15
- 239000007943 implant Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 230000007774 longterm Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012938 design process Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract
The application discloses a power MOSFET device with enhanced cell design, which is used for solving the technical problem of reducing the electric field intensity in a gate oxide under the conditions of not changing the process flow and the cost of the device and not sacrificing more other performances. The power MOSFET device in the application comprises: an epitaxial layer having a first conductivity type; the first areas with the second conductivity type are uniformly distributed on the upper surface of the epitaxial layer, and each first area and the epitaxial layer form a first PN junction respectively; a plurality of central injection structures with a second conductivity type and uniformly distributed in the JFET region; the JFET region is formed by a gap between any two adjacent first regions; wherein, the central injection structures are round or regular polygon. According to the method and the device, the electric field shielding is realized through the central injection structure, so that the electric field intensity in the grid oxide is reduced, and the reliability of the device is improved.
Description
Technical Field
The present application relates to the field of semiconductor device technology, and more particularly to a power MOSFET device with enhanced cell design.
Background
Metal-Oxide-semiconductor field effect transistor (MOSFET) devices are commonly used for power and load control of circuits, and thus often need to withstand high voltage and high current operating environments. One potential problem in the high voltage blocking mode is the presence of a high electric Field at the gate oxide over the Junction Field-Effect Transistor (JFET) region of the power MOSFET device. Thus, in the long-term blocking mode, the reliability of the power MOSFET device may be greatly reduced.
In the prior art, in order to reduce the electric field intensity in the gate oxide, on one hand, the width of the JFET region is reduced, but the on-resistance of the power MOSFET device is increased in the mode, and the forward conduction performance is sacrificed; on the other hand, one or more separate second conductivity type region designs are added to the JFET region, but this approach is currently based solely on theoretical studies of the power MOSFET device and is not discussed in connection with actual power MOSFET devices.
Therefore, there is a need for a power MOSFET device that reduces the electric field strength in the gate oxide and improves the reliability of the power MOSFET device without changing the process flow and cost, and without sacrificing much other performance.
Disclosure of Invention
The embodiment of the application provides a power MOSFET device with an enhanced cell design, which aims to solve the technical problem of reducing the electric field intensity in a grid oxide under the conditions of not changing the process flow and the cost of the power MOSFET device and not sacrificing more other performances.
Embodiments of the present application provide a power MOSFET device including an enhanced cell design, comprising: an epitaxial layer having a first conductivity type; the first areas with the second conductivity type are uniformly distributed on the upper surface of the epitaxial layer, and each first area and the epitaxial layer form a first PN junction respectively; a plurality of central injection structures with a second conductivity type and uniformly distributed in the JFET region; the JFET region is formed by a gap between any two adjacent first regions; wherein, the central injection structures are round or regular polygon.
In the power MOSFET device with the enhanced cell design, the central injection structure is added in each JFET region formed by the interval between the first regions, so that the effect of shielding an electric field is helped, the electric field intensity in the grid oxide is further reduced, and the reliability of the power MOSFET device is enhanced. The technical effect of reducing the electric field intensity in the gate oxide is achieved under the conditions of not changing the process flow and the cost and not sacrificing more other performances.
In one implementation of the present application, communication between any two central injection structures; alternatively, any of the central injection structures communicates with its adjacent first region.
The power MOSFET device with the enhanced cell design has the advantages that the added central injection structure can be connected with each other to form a net-shaped central injection structure, and the connection with the source electrode can be realized in the transition area of the device, so that the smaller central injection structure size can be continuously maintained in the cell area of the device, and more device conduction performance can not be sacrificed. In addition, the size of the central injection structure can be further adjusted to enable the central injection structure to be communicated with the first area, so that the purpose of connecting with the source electrode is achieved, and more conduction performance of the device is guaranteed not to be sacrificed.
In one implementation of the present application, any two adjacent first region portions are connected so that the power MOSFET device has a plurality of JFET regions that are independent of each other.
The power MOSFET device with the enhanced cell design provided by the embodiment of the application, the first area between the adjacent JFET areas is similar to the central injection structure, and can play a role in shielding an electric field in a high-voltage blocking mode, so that the electric field intensity in the grid oxide is reduced. Meanwhile, the planar power MOSFET device with the continuous first area has low requirements on the process capability by the structural design, and further, the stability of the process flow and the cost is realized.
In one implementation of the present application, the power MOSFET device further includes: a plurality of second regions having the first conductivity type; wherein each second region is positioned inside each first region; the second region and the first region form a second PN junction; the depth of the second region is smaller than the depth of the first region; a plurality of third regions having a second conductivity type; wherein, each third area is positioned at the center of each first area and is connected with the first area; and ohmic contact metal is formed on the upper surface of the third region; the ohmic contact metal is in contact with the third region and the second region simultaneously to suppress parasitic bipolar diodes within the power MOSFET device.
In one implementation of the present application, the shape of the second region is the same as the shape of the first region. And the shape of the third region may be the same as the shape of the first region (second region).
In one implementation of the present application, the second region is a ring-shaped polygon.
In one implementation of the present application, the doping concentration of the third region is higher than the doping concentration of the first region.
The power MOSFET device with the optimized cell design, provided by the embodiment of the application, has the advantages that the first area is round or regular polygon, and compared with the traditional strip-shaped cell design, the area utilization rate can be increased under the same structural parameters, and further, more other performance parameters are not changed. The second area is annular polygonal, and the shape of the second area is consistent with that of the first area, so that the uniformity of the channel length of the power MOSFET device is ensured.
In one implementation of the present application, the power MOSFET device further includes: the insulating gate oxide layer is formed on the upper surface of the epitaxial layer and spans any two adjacent second areas; and the grid electrode conductive polycrystalline silicon is formed on the upper surface of the insulated grid electrode oxide layer and spans any two adjacent second areas.
In one implementation of the present application, the power MOSFET device further includes: a drain electrode located on the lower surface of the silicon carbide substrate; the silicon carbide substrate is positioned on the lower surface of the epitaxial layer and has a first conductivity type; the doping concentration of the silicon carbide substrate is higher than that of the epitaxial layer; the source electrode is positioned on the top of the power MOSFET device, and the source electrode and the grid conductive polysilicon are separated by an insulating dielectric layer.
In one implementation of the present application, several central injection structures are connected to the source electrode to reduce the impact on the device turn-on performance. The doping concentration of the central injection structure is equal to that of the first region or the third region.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a cross-sectional view of an active area cell of a conventional planar power MOSFET device;
fig. 2 is a schematic diagram of electric field distribution of a conventional planar power MOSFET device in blocking mode;
FIG. 3 is a schematic diagram of a conventional planar power MOSFET device with a striped cell design;
fig. 4 is a schematic diagram of a partial structure of a planar power MOSFET device with a stripe cell design including a central injection structure according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a partial structure of a planar power MOSFET device with a hexagonal cell design with a central injection structure according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a partial structure of a planar power MOSFET device with an octagonal cell design with a central injection structure according to an embodiment of the present application;
fig. 7 is a schematic diagram of a partial structure of a planar power MOSFET device with a hexagonal cell design with a mesh-like central implant structure according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a partial structure of a planar power MOSFET device with an octagonal cell design with a mesh-like central implant structure according to an embodiment of the present application;
fig. 9 is a schematic diagram of a local structure of a planar power MOSFET device with a hexagonal cell design in which a central injection structure is connected to a first region according to an embodiment of the present application;
fig. 10 is a schematic diagram of a partial structure of a planar power MOSFET device with an octagonal cell enhancement design according to an embodiment of the present application;
fig. 11 is a schematic diagram of a partial structure of a planar power MOSFET device with a circular cell enhancement design according to an embodiment of the present disclosure;
fig. 12 is a schematic diagram of a partial structure of a planar power MOSFET device with hexagonal cell enhancement design according to an embodiment of the present disclosure;
fig. 13 is a schematic diagram of a local structure of a planar power MOSFET device with a square cell enhancement design according to an embodiment of the present application.
Detailed Description
For the purposes, technical solutions and advantages of the present application, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The forbidden band width of the silicon carbide semiconductor material is about three times that of the silicon material, and the silicon carbide semiconductor material has higher critical breakdown electric field strength, higher heat conductivity coefficient, lower intrinsic carrier concentration and higher saturation drift speed, so that the silicon carbide is an ideal material for high-voltage, high-temperature and high-power devices.
The silicon carbide power device mainly comprises a power diode and a power switch tube. The silicon carbide power MOSFET device has the advantages of high switching speed, small on-resistance and the like, and can realize higher breakdown voltage through smaller thickness of an epitaxial layer (drift layer), so that the size and the energy consumption of a power switch module are reduced, and the silicon carbide power MOSFET device has obvious advantages in the application fields of a power switch, a converter and the like. For power MOSFET devices of silicon carbide semiconductor material, there are two technical routes for commercial devices, planar power MOSFET devices and trench power MOSFET devices. Among them, planar power MOS devices have a simpler process flow and are favored by commercial devices.
Power MOSFET devices are commonly used for power and load control of circuits and often need to withstand high voltage and high current operating environments. One potential problem in the high voltage blocking mode is the presence of a high electric Field at the gate oxide in the center of the Junction Field-Effect Transistor (JFET) region of the device. Therefore, in the long-term blocking mode, the reliability of the power MOSFET device is reduced. In the high voltage blocking mode, a high bias voltage (near the maximum operating voltage) is applied to the drain and the gate is held at an operating condition near ground. By gaussian law, the electric field strength in the gate oxide layer above the JFET region has the following relationship with the electric field strength in the semiconductor below:
E Oxide ＝(ε Semi /ε Oxide )E Semi
here ε Semi And epsilon Oxide Dielectric constants of silicon carbide and gate oxide layer, E Semi Is the electric field strength in the semiconductor below the gate oxide. In the case of silicon carbide,its critical field strength is about 3×10 6 V/cm when the semiconductor in the power MOSFET device reaches this value, the electric field strength in the gate oxide layer has already exceeded the safety threshold for long-term operation of the device by 4X 10 6 V/cm。
In the long-term blocking mode, the drain is placed under high forward bias and defects in the gate oxide may eventually cause the device to fail. Second, in conventional power MOSFET devices, the silicon carbide-gate oxide interface may also undergo hot carrier injection in the long-term blocking mode when the drain is placed at a high forward bias.
In order to reduce the electric field strength in the gate oxide, the following technical approaches are adopted:
1. by reducing the spacing between the well regions (the width of the JFET region), the electric field strength in the gate oxide is reduced. But this design increases the on-resistance of the power MOSFET device, sacrificing forward conduction performance.
2. The addition of one or more separate second conductivity type regions to the JFET region is based solely on theoretical considerations of the power MOSFET device and is not discussed in connection with actual power MOSFET device designs.
Therefore, the embodiment of the application provides a power MOSFET device with an optimized cell design to solve the technical problems in the prior art, and aims at a planar power MOSFET device, and combines with the actual power MOSFET device structural design, and the power MOSFET device reliability is improved by reducing the electric field intensity in the gate oxide without changing the process flow and the cost and without sacrificing more other performances through the optimized cell design. Meanwhile, various different layout designs are provided in the embodiment of the application, so that the device can be helped to achieve better balance between on-resistance, short circuit capacity and avalanche capacity.
The following describes in detail the technical solution proposed in the embodiments of the present application through the accompanying drawings.
Fig. 1 is a cell cross-sectional view of an active region of a conventional planar power MOSFET device. As shown in fig. 1, a power MOSFET device 10 includes a silicon carbide substrate 101 containing impurities and having a first conductivity type; a silicon carbide epitaxial layer 102 having a first conductivity type is formed on the substrate 101, and the doping concentration of the epitaxial layer 102 is lower than that of the silicon carbide substrate 101.
As shown in fig. 1, the upper surface of epitaxial layer 102 includes: a plurality of well regions 103 of a second conductivity type different from the first conductivity type; the well region 103 forms a first PN junction 113 with the epitaxial layer 102. A plurality of source regions 104, which contain highly doped first conductivity type, are formed in the well region 103 on the surface of the epitaxial layer 102, and form a second PN junction 114 with the well region 103. A plurality of regions 105 of the highly doped second conductivity type are formed in the well region 103 on the surface of the epitaxial layer 102, forming a connection with the well region 103 and forming an ohmic contact metal 109 thereon. An insulating gate oxide layer 106 is formed on top of the epitaxial layer 102 and spans two adjacent well regions 103 and source regions 104. A gate conductive polysilicon 107 is formed over the gate oxide 106 and spans two adjacent well regions 103 and source regions 104. A source electrode 110 is formed on top of the power MOSFET device 10. The gate conductive polysilicon 107 is separated from the source electrode 110 by an insulating dielectric layer 108. A drain electrode 111 formed on the back surface of the substrate 101.
As shown in fig. 1, a Junction Field-Effect Transistor (JFET) region 112 is formed between two adjacent well regions 103.
When the power MOSFET device is in the high voltage blocking mode for a long period of time, a high bias voltage (near the maximum operating voltage) is applied to the drain electrode 111 and the gate maintains operating conditions near ground potential, a high electric field is created in the gate oxide 106 directly above the JFET region. And the electric field distribution of the power MOSFET device is shown in fig. 2.
Fig. 2 is a schematic diagram of electric field distribution of a conventional planar power MOSFET device according to an embodiment of the present application in a blocking mode. As shown in fig. 2, in the long-term blocking mode, the drain is placed under a high forward bias and defects in the gate oxide may eventually cause the device to fail. Second, in conventional power MOSFET devices, the silicon carbide-gate oxide interface may also undergo hot carrier injection in the long-term blocking mode when the drain is placed at a high forward bias.
Most of the conventional power MOSFET devices include a stripe cell design, as shown in fig. 3. Fig. 3 is a schematic diagram of a conventional planar power MOSFET device with a stripe cell design.
For the design of a stripe cell, the structure 112 is the JFET region mentioned above, and in order to reduce the electric field strength in the gate oxide, one or more doped structures containing the second conductivity type, referred to as the center implant structure 115, are designed on the surface of the JFET region. As shown in fig. 4, the planar power MOSFET device with the stripe cell design having the central injection structure, the central injection structure 115, can act as a shield for the electric field, thereby reducing the electric field strength in the gate oxide.
However, in the power MOSFET device with the stripe cell design with the central injection structure shown in fig. 4, during actual use, a portion of the JFET region 112 for conducting current is sacrificed, so that the on-resistance of the device is increased, that is, a portion of the on-performance of the device is sacrificed.
In this regard, the round and regular polygon cell designs adopted in the embodiments of the present application have the advantage of higher area utilization (under the same structural parameter design, the area utilization of the round and regular polygon cells is higher). Therefore, the embodiments of the present application implement planar power MOS device designs with central injection structures based on round and regular polygon cells. The method can reduce the electric field intensity in the grid oxide and improve the reliability of the power MOSFET device through reasonable electric field shielding structure design under the conditions of not changing the process flow and the cost and not sacrificing more other performances.
Fig. 5 is a schematic diagram of a partial structure of a planar power MOSFET device with a hexagonal cell design with a central injection structure according to an embodiment of the present application. Similar to the stripe cell enhancement design, the power MOSFET device of fig. 5 employs a hexagonal cell design, and incorporates several central injection structures 115 into the JFET region 112 to act as a shield for the electric field in the high voltage blocking mode, helping to reduce the electric field strength in the gate oxide layer, and thus enhance the reliability of the device.
As shown in fig. 5, the power MOSFET device according to the embodiment of the present application mainly includes a first region (well region) 103, a second region 104, a third region 105, and a plurality of central injection structures 112. The first regions 103 are uniformly distributed on the upper surface of an epitaxial layer (not shown) having a first conductivity type and have a second conductivity type different from the epitaxial layer. The second region 104 is located inside the first region 103, the third region 105 is located at a center position of the first region 104, and the second region 104 has a first conductivity type, and the third region 105 has a second conductivity type. The central injection structure 115 has the second conductivity type and is distributed in the gaps between the first regions 103 to play a role of shielding the electric field, and the central injection structure 115 in fig. 5 adopts a triangle shape, and the first regions 103 adopt a hexagon shape.
In one embodiment of the present application, the second region 104 forms a second PN junction with the first region 103, and the depth of the second region 104 is smaller than the depth of the first region 103.
Further, the third region 105 is connected to the first region 103.
Further, an ohmic contact metal is formed on the upper surface of the third region 105, and the ohmic contact metal is simultaneously contacted with the third region and the second region to suppress parasitic bipolar transistors inside the MOSFET device.
In another embodiment of the present application, the second region is a ring polygon, and the shape of the second region is the same as that of the first region. For example, hexagonal as shown in fig. 5. The shapes of the first region and the third region may be the same or different, which is not limited in the embodiment of the present application.
Similarly, the embodiments of the present application also provide a power MOSFET device as shown in fig. 6. Fig. 6 is a schematic diagram of a partial structure of a planar power MOSFET device with an octagonal cell design with a central injection structure according to an embodiment of the present application. As shown in fig. 6, the cells of the power MOSFET device are in an octagonal design, and the first region 103, the second region 104, and the third region 105 are all in an octagonal design. And a number of central implant structures 115 are added in the JFET region 112 between the first regions 103. And the central implant structure 115 as shown in fig. 6 takes the form of a quadrilateral.
In one embodiment of the present application, several central injection structures as in fig. 5, 6 communicate with the source of the power MOSFET device to reduce the impact on the turn-on performance of the device.
Compared with the power MOSFET device with the stripe cell design shown in fig. 4, the power MOSFET device with the hexagonal and octagonal cell designs shown in fig. 5 and 6 has higher area utilization advantage, that is, under the same structural parameters, the area utilization ratio of the hexagonal and octagonal cells is higher than that of the stripe cells, so that the performance of the device is better.
It should be noted that the cell design and the central injection structure in the embodiments of the present application may be designed in a circular shape, a regular polygon shape, etc., and the hexagonal design in fig. 5 and the octagonal design in fig. 6 are only exemplary illustrations in the embodiments of the present application, and are not intended to limit the cell design shape in the present application. In the actual design process, other different hexagonal and octagonal regular polygon design cells can be adopted. The embodiments of the present application are not limited in this regard.
The embodiment of the application can achieve the technical problems of reducing the electric field intensity in the grid oxide and further improving the reliability of the device through the design of the power MOSFET device shown in the figures 4-6. However, in the actual device manufacturing process, the device designs shown in fig. 4, 5 and 6 have high requirements on the process capability (the central injection structure is limited by the minimum line width of the ohmic contact in the process conditions, so that the central injection structure with a smaller size cannot be realized, and the conduction performance of the device is finally sacrificed). Therefore, the embodiments of the present application also provide a power MOSFET device design with high feasibility, i.e. communication between any two adjacent central injection structures 115. The structure schematic diagram is shown in fig. 7 and 8.
Fig. 7 is a schematic diagram of a partial structure of a planar power MOSFET device with a hexagonal cell design with a mesh-like central implant structure according to an embodiment of the present disclosure; fig. 8 is a schematic diagram of a partial structure of a planar power MOSFET device with an octagonal cell design with a mesh-like central implant structure according to an embodiment of the present application.
As shown in fig. 7, the embodiment of the present application connects the plurality of central injection structures 115 of fig. 5 to each other in pairs to form a mesh-like central injection structure. And the first region 103, the second region 104 and the third region 105 in fig. 7 are of hexagonal cell design, and the central injection structure 115 is of triangular design. In contrast, the several central injection structures 115 in fig. 5 are independent of each other in pairs, while the central injection structures 115 in fig. 7 are in communication with each other in pairs.
As shown in fig. 8, the embodiment of the present application connects the plurality of central injection structures 115 of fig. 6 to each other in pairs to form a mesh-like central injection structure. I.e., the first region 103, the second region 104, and the third region 105 in fig. 8 all take the same octagonal design as the power mosfet device shown in fig. 6, and the several central injection structures 115 also take the same square design. In contrast, the central injection structures 115 of fig. 6 are designed to be independent of each other, while the central injection structures of fig. 8 are designed to be in communication with each other.
In one embodiment of the present application, a mesh-like center implant structure as shown in fig. 7 and 8 may be implemented in the transition region of the power MOSFET device to communicate with the source to reduce the impact on the turn-on performance of the power MOSFET device. And the doping concentration of the central implant structure 115 is equal to the doping concentration of the first region 103 or the third region 105.
Further, the doping concentration of the third region 105 is higher than the doping concentration of the first region 103.
That is, the mesh-shaped central injection structure in fig. 7 and 8 provided in the embodiments of the present application may connect several central injection structures isolated in fig. 5 and 6, and connect the source electrode in the transition region of the device. Furthermore, the dimension of the central injection structure can be kept small in the cell area of the device, and the conduction performance of the device is not excessively sacrificed. Therefore, the power MOSFET device in fig. 7 and 8 can be completely realized without changing the process and cost and without sacrificing more other performances, and the electric field intensity in the gate oxide layer is reduced, thereby improving the reliability of the device.
Further, in the power MOSFET device proposed in the embodiments of the present application, the size of the central injection structure 115 may also be adjusted so that any central injection structure 115 is turned on with the first region 103 adjacent thereto, thereby achieving the purpose of connection with the source. That is, any of the central injection structures of the power MOSFET device set forth in the embodiments of the present application may be turned on with its adjacent first region.
Fig. 9 is a schematic diagram of a local structure of a planar power MOSFET device with a hexagonal cell design in which a central injection structure is connected to a first region according to an embodiment of the present application. As shown in fig. 9, the dimension of the central implant structure 115 is enlarged to connect with the first region 103, so that the connection of the central implant structure 115 with the source can be realized, thereby ensuring that more device conduction performance is not sacrificed. As shown in fig. 9, the plurality of central injection structures 115 are connected to the first region 103, and the plurality of central injection structures 115 are in a triangular design, and the first region 103, the second region 104 and the third region 105 are in a hexagonal cell design.
In one embodiment of the present application, two adjacent first regions of the power MOSFET device are partially connected to form a plurality of mutually independent JFET regions in the power MOSFET device.
It will be apparent to those skilled in the art that the first region 103 in the power MOSFET device proposed in the embodiments of the present application may also function as an electric field shield. Accordingly, the embodiment of the present application further provides a power MOSFET device with a portion of the first region 103 connected, as shown in fig. 10.
Fig. 10 is a schematic diagram of a partial structure of a planar power MOSFET device with an octagonal cell enhancement design according to an embodiment of the present application. As shown in fig. 10, two adjacent first regions 103 are partially connected to form a plurality of JFET regions 112 that are independent of each other. Meanwhile, the portion of the first region 103 between the adjacent JFET regions 112 that is connected to each other, like the central injection structure 115 in the stripe cell enhancement design shown in fig. 4, can also function as a shield for the electric field in the high voltage blocking mode.
As shown in fig. 10, the first region 103, the second region 104 and the third region 105 are all in an octagonal design, and two adjacent first regions 103 are partially connected to form a plurality of JFET regions 112 that are independent of each other. The first regions 103 connected to each other can also realize an electric field shielding effect.
In another embodiment of the present application, the first region may be designed in a circular shape, a regular polygon, or the like. Thus, embodiments of the present application also provide a variety of power MOSFET devices that employ different shaped cell designs. Such as circular cells, as shown in fig. 11; hexagonal cells, as shown in fig. 12; square cells, as shown in fig. 13.
It will be apparent to those skilled in the art that the power MOSFET device set forth in the embodiments of the present application necessarily includes a source electrode, a gate electrode, and a drain electrode. Thus, the power MOSFET device further comprises: the insulating gate oxide layer is formed on the upper surface of the silicon carbide epitaxial layer and spans any two adjacent second areas; and the grid conductive polysilicon is formed on the upper surface of the insulated grid oxide layer and spans any two adjacent second areas.
Further, the power MOSFET device further includes: a drain electrode located on the lower surface of the silicon carbide substrate; the silicon carbide substrate is positioned on the lower surface of the epitaxial layer and has a first conductivity type; the doping concentration of the silicon carbide substrate is higher than that of the silicon carbide epitaxial layer; and the source electrode is positioned on the top of the power MOSFET device, and the source electrode and the grid conductive polysilicon are separated by an insulating dielectric layer.
The power MOSFET device with the enhanced cell design provided by the embodiment of the application aims at a planar power MOS device, combines with the actual power MOSFET device structural design, and achieves the technical effects of reducing the electric field intensity in the grid oxide and improving the reliability of the power MOSFET device under the conditions of not changing the process flow and the cost and not sacrificing more other performances through the optimized cell design. Meanwhile, the different layout designs shown in the embodiment of the application can help the device to realize better balance between on-resistance, short circuit capacity and avalanche capacity.
All embodiments in the application are described in a progressive manner, and identical and similar parts of all embodiments are mutually referred, so that each embodiment mainly describes differences from other embodiments.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.
Claims (7)
1. A power MOSFET device having an enhanced cell design, said power MOSFET device comprising:
an epitaxial layer having a first conductivity type;
the first areas with the second conductivity type are uniformly distributed on the upper surface of the epitaxial layer, and each first area and the epitaxial layer form a first PN junction respectively;
a plurality of central injection structures with a second conductivity type and uniformly distributed in the JFET region; the JFET region is formed by a gap between any two adjacent first regions;
wherein, the central injection structures are round or regular polygon;
any two adjacent first area parts are communicated, so that the power MOSFET device is provided with a plurality of mutually independent JFET areas;
the power MOSFET device further includes:
a plurality of second regions having the first conductivity type; wherein each of the second regions is located inside each of the first regions; the second region and the first region form a second PN junction; the depth of the second region is smaller than the depth of the first region;
a plurality of third regions having a second conductivity type; wherein, each third area is positioned at the center of each first area and is connected with the first area; and ohmic contact metal is formed on the upper surface of the third region;
the ohmic contact metal is contacted with the third region and the second region simultaneously;
the doping concentration of the third region is higher than the doping concentration of the first region.
2. The power MOSFET device of claim 1, wherein any two of said central injection structures are in communication;
alternatively, any one of the central injection structures communicates with the first region adjacent thereto.
3. The power MOSFET device of claim 1, wherein said second region has a shape that is the same as a shape of said first region.
4. The power MOSFET device of claim 1, wherein said second region is a ring-shaped polygon.
5. The power MOSFET device of claim 1, wherein said power MOSFET device further comprises:
the insulated gate oxide layer is formed on the upper surface of the epitaxial layer and spans any two adjacent second areas;
and the grid electrode conductive polysilicon is formed on the upper surface of the insulated grid electrode oxide layer and spans any two adjacent second areas.
6. The power MOSFET device of claim 1, wherein said power MOSFET device further comprises:
a drain electrode located on a lower surface of the silicon carbide substrate; the silicon carbide substrate is positioned on the lower surface of the epitaxial layer and has a first conductivity type; the doping concentration of the silicon carbide substrate is higher than that of the epitaxial layer;
and the source electrode is positioned on the top of the power MOSFET device, and the source electrode and the grid conductive polysilicon are separated by an insulating dielectric layer.
7. The power MOSFET device of claim 6, wherein said plurality of central injection structures are connected to said source electrode; wherein the doping concentration of the central injection structure is equal to the doping concentration of the first region or the third region.
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| CN113540251B (en) * | 2021-09-15 | 2021-12-03 | 浙江大学杭州国际科创中心 | Optimally-arranged trench gate power MOSFET device |
| CN115548101B (en) * | 2022-11-25 | 2023-03-10 | 浙江大学 | Silicon carbide MOSFET transistor device |
| CN116110937B (en) * | 2022-12-20 | 2023-10-20 | 瑶芯微电子科技(上海)有限公司 | Silicon carbide-based MOSFET device and manufacturing method |
| CN116190446B (en) * | 2022-12-20 | 2023-12-08 | 瑶芯微电子科技(上海)有限公司 | Silicon carbide-based MOSFET device with high reliability and manufacturing method thereof |
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