CN115548101B - Silicon carbide MOSFET transistor device - Google Patents
Silicon carbide MOSFET transistor device Download PDFInfo
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- CN115548101B CN115548101B CN202211488433.7A CN202211488433A CN115548101B CN 115548101 B CN115548101 B CN 115548101B CN 202211488433 A CN202211488433 A CN 202211488433A CN 115548101 B CN115548101 B CN 115548101B
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 100
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- 229910052710 silicon Inorganic materials 0.000 description 4
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model relates to a carborundum MOSFET transistor device, an interconnect structure has been designed between two adjacent cellular structures for two adjacent cellular structures are connected through interconnect structure, in the twinkling of an eye that surge impact or short circuit trouble take place, can make plasma spread to adjacent cellular structure from a cellular structure rapidly, thereby obtain the evenly distributed of carrier concentration and current density, avoid the inside local heat of taking place of device to concentrate and the serious phenomenon of temperature rise, improve the surge and the short circuit reliability of device.
Description
Technical Field
The application relates to the technical field of power electronic device design, in particular to a silicon carbide MOSFET transistor device.
Background
Silicon carbide MOSFET transistor devices will experience high current stresses, much greater than steady state peak or overload currents, under power transients, circuit faults, or lightning induced surges. Under surge impact, a large current multiplied by the voltage drop of the device forms instantaneous energy overshoot which flows into the device in a relatively short time, so that the junction temperature of the device is rapidly increased, the reliability of the device is possibly reduced, and even performance degradation and failure occur. Thus, the surge current resistance of silicon carbide MOSFET transistor devices is one of the key indicators in describing their robustness in extreme current surge situations. Silicon carbide MOSFET transistor devices with superior surge current resistance can effectively dissipate this energy without degradation or failure, thereby providing higher safety margins for, and improving the reliability and life of, the power equipment.
Commercial silicon carbide MOSFET transistor devices currently on the market generally have low surge current resistance and cannot meet the requirements of special applications, for example, in the application of Power Factor Correction (PFC) in a high-voltage power distribution system, surge large current surge may occur at the moment of circuit opening and/or at the time of circuit interruption. When surge shock occurs, the silicon carbide MOSFET transistor device dissipates a large amount of power and energy, and if the silicon carbide MOSFET transistor device is improperly designed, local overheating occurs, so that the surge current resistance of the silicon carbide MOSFET transistor device is reduced, and finally the silicon carbide MOSFET transistor device fails catastrophically due to overheating.
In order to obtain lower specific on-resistance and higher on-current density and further reduce the chip area and the production cost, the silicon carbide MOSFET transistor device is generally designed by adopting a short-channel and wider JFET structure, however, the JFET effect of the design is weakened, the current amplitude of the output characteristic saturation region of the device is larger, the device is in a saturation region working mode in short-circuit faults, the short-circuit current peak value is determined by the current amplitude of the saturation region, and therefore the weak JFET effect can cause the short-circuit current peak value to be higher (more than 10 times of the rated working current of the device). Compared with a silicon carbide MOSFET device, the silicon IGBT is a bipolar device and has a conductance modulation effect, and the silicon IGBT device with the same current level can be generally designed by adopting a long channel and a narrower JFET structure, so that a stronger JFET effect and lower saturation region working current are obtained, and the peak value of a short circuit of the device in short circuit fault is reduced (only about 4 times of the rated working current of the device).
The short-circuit current peak value that carborundum MOSFET transistor device flowed through the device is higher in short-circuit fault, in addition, carborundum MOSFET transistor generally has littleer chip area, the heating effect that short-circuit energy pulse arouses inside the device is more serious, and carborundum device PN junction is shallower, the position of generating heat is inside weak links such as being closer to chip surface grid oxide layer and aluminium electrode more in the device, above all aspects reason leads to carborundum MOSFET transistor device's short circuit bearing capacity than silicon IGBT device poor, it is short-circuit bearing time than silicon IGBT device specifically to show.
Silicon carbide MOSFET transistor devices have high switching speeds and weak short circuit tolerance, and have higher requirements for gate drive, which requires the ability to detect a short circuit within 1 microsecond and turn off the device quickly, avoiding damage to the device due to overheating. Thus, improving the shorting capability of silicon carbide MOSFET transistor devices can help increase the safety margin at the application end.
In summary, the conventional silicon carbide MOSFET transistor device has difficulty in achieving the contradictory relationship between the device turn-on performance and the reliability.
Disclosure of Invention
Based on this, it is necessary to provide a silicon carbide MOSFET transistor device in order to solve the problem that the area utilization and robustness of the conventional silicon carbide MOSFET transistor device are difficult to balance so that the area utilization and robustness of the device are compatible.
The present application provides a silicon carbide MOSFET transistor device comprising:
a substrate having a first conductivity type;
the epitaxial layer is arranged on the substrate and has a first conductive type;
the active region is formed on the top surface of the epitaxial layer;
the active region includes:
the cell structures are arranged on the top surface of the epitaxial layer in an array mode; the shape of the cellular structure is circular or polygonal;
each cell structure includes:
a well region having a second conductivity type;
a source region highly doped with a first conductivity type and located in the well region;
the doped region is arranged in the well region and is highly doped with the second conductive type; the source region is positioned at the periphery of the doped region;
the JFET area is arranged on the periphery of the well area; in a straight line direction, the JFET areas of two adjacent cellular structures are connected;
the doped region of each cellular structure and the doped regions of N cellular structures adjacent to the cellular structure are respectively connected with each other through an interconnection structure, N is a natural number, and at least one pair of cellular structures with the doped regions connected with each other exist.
The utility model relates to a carborundum MOSFET transistor device, an interconnect structure has been designed between two adjacent cellular structures for two adjacent cellular structures are connected through interconnect structure, in the twinkling of an eye that surge impact or short circuit trouble take place, can make plasma spread to adjacent cellular structure from a cellular structure rapidly, thereby obtain the evenly distributed of carrier concentration and current density, avoid the inside local heat of taking place of device to concentrate and the serious phenomenon of temperature rise, improve the surge and the short circuit reliability of device.
Drawings
Fig. 1 is a perspective view (with a transition region omitted) of a silicon carbide MOSFET transistor device provided in embodiment 12 of the present application.
Fig. 2 isbase:Sub>A perspective view ofbase:Sub>A silicon carbide MOSFET transistor device provided in embodiment 12 of the present application (with section linesbase:Sub>A-base:Sub>A 'and section lines B-B' omitted).
Fig. 3 isbase:Sub>A schematic diagram ofbase:Sub>A cross-section ofbase:Sub>A silicon carbide MOSFET transistor device in layoutbase:Sub>A, the cross-section being formed by cutting an active region alongbase:Sub>A section linebase:Sub>A-base:Sub>A' according to embodiment 12 of the present application.
Fig. 4 isbase:Sub>A schematic diagram ofbase:Sub>A cross-section ofbase:Sub>A silicon carbide MOSFET transistor device according to example 12 of the present application, the cross-section being formed by sectioning an active region alongbase:Sub>A section linebase:Sub>A-base:Sub>A' in layout modes b and c.
Fig. 5 is a schematic diagram of a cross-section of a silicon carbide MOSFET transistor device according to embodiment 12 of the present application, the cross-section being formed by sectioning an active region along a section line B-B' in layout mode a.
Fig. 6 is a schematic diagram of a cross-section of a silicon carbide MOSFET transistor device according to example 12 of the present application, the cross-section being taken along a section line B-B' of an active region in layout B.
Fig. 7 is a schematic diagram of a cross-section of a silicon carbide MOSFET transistor device according to example 12 of the present application, the cross-section being formed by sectioning an active region along a section line B-B'.
Fig. 8 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device provided in embodiment 1 of the present application.
Fig. 9 is a perspective view (with a transition region) of a silicon carbide MOSFET transistor device provided in embodiment 12 of the present application.
Fig. 10 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device provided in embodiment 2 of the present application.
Fig. 11 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device provided in example 3 of the present application.
Fig. 12 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device provided in embodiment 4 of the present application.
Fig. 13 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device provided in embodiment 5 of the present application.
Fig. 14 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device provided in example 6 of the present application.
Fig. 15 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device provided in embodiment 7 of the present application.
Fig. 16 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device provided in embodiment 8 of the present application.
Fig. 17 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device according to example 9 of the present application.
Fig. 18 is a top view of the active region and transition region of a silicon carbide MOSFET transistor device of example 10 of the present application.
Fig. 19 is a top view of the active and transition regions of a silicon carbide MOSFET transistor device of example 11 of the present application.
Fig. 20 is a top view of the active region and transition region of a silicon carbide MOSFET transistor device of example 12 of the present application.
Fig. 21 is a top view of the active region and transition region of a silicon carbide MOSFET transistor device of example 13 of the present application.
Fig. 22 is a top view of the active region and transition region of a silicon carbide MOSFET transistor device of example 14 of the present application.
Fig. 23 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device of example 15 of the present application.
Fig. 24 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device of example 16 of the present application.
Fig. 25 is a top view of an active region and a transition region of a silicon carbide MOSFET transistor device of example 17 of the present application.
Fig. 26 is a graph of short circuit test data for a silicon carbide MOSFET transistor device with a hexagonal cell structure and not having an interconnect structure, a silicon carbide MOSFET transistor device with a hexagonal cell structure and having an interconnect structure, and a silicon carbide MOSFET transistor device with a square cell structure and having an interconnect structure at different bus voltages.
Reference numerals:
10-a substrate; 20-an epitaxial layer; 30-an active region; 300-cell structure; 310-well region;
311-sides of well regions; 320-a source region; 330-doped region; 340-a JFET area;
350-an interconnect structure; 360-cell rows; 370-columns of cells; 40-transition zone.
Detailed Description
For the purpose of making the present application, technical solutions and advantages thereof more apparent, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The present application provides a silicon carbide MOSFET transistor device.
In one embodiment of the present application, as shown in fig. 1, the silicon carbide MOSFET transistor device includes a substrate 10, an epitaxial layer 20, and an active region 30. The substrate 10 has a first conductivity type. The epitaxial layer 20 is disposed on the substrate 10. The epitaxial layer 20 has a first conductivity type. An active region 30 is formed on the top surface of the epitaxial layer 20.
The active region 30 includes a plurality of cell structures 300. The plurality of cell structures 300 are arranged in an array on the top surface of the epitaxial layer 20. The shape of the cell structure 300 is circular or polygonal. Each cell structure 300 includes a well region 310, a source region 320, a doped region 330, and a JFET region 340. The well region 310 has a second conductivity type. The source region 320 has a highly doped first conductivity type, and the source region 320 is located in the well region 310. The doped region 330 is disposed in the well region 310, and the doped region 330 has a second conductive type with high doping. The source regions 320 are located around the doped regions 330. The JFET region 340 is disposed around the well region 310. In a straight line direction, the JFET regions 340 of two adjacent cell structures 300 meet.
The doped region 330 of each cell structure 300 and the doped regions 330 of the N cell structures 300 adjacent to the cell structure 300 are respectively connected to each other by an interconnection structure 350. N is a natural number. There is at least one pair of cell structures 300 with doped regions 330 interconnected.
Specifically, the substrate 10 is a silicon carbide substrate. The projection of the active region 30 on the top surface of the substrate 10 is an irregular polygon. For simplicity of illustration and ease of description, the projection of the active region 30 onto the top surface of the substrate 10 is shown as a rectangle throughout the drawings of this application.
Alternatively, the shape of the cell structure 300 provided herein may be circular and polygonal. With the same active area 30 and the same width of the 2.5 micron JFET region 340, the circular and polygonal shaped cell structures 300 provided herein can increase the total channel width of the silicon carbide MOSFET transistor device by 6% to 18% over the conventional stripe shaped cell structures.
For the same active area 30 and the same width of the 2.5 micron JFET region 340, the circular and polygonal cell structures 300 provided herein can increase the total area of the JFET region 340 of the silicon carbide MOSFET transistor device by 45% to 60% over the strip-shaped cell structures of the conventional scheme.
Therefore, the circular and polygonal cell structures 300 provided by the present application can effectively improve the area utilization of the silicon carbide MOSFET transistor device, so that the silicon carbide MOSFET transistor device has a lower specific on-resistance, thereby reducing the cost of the silicon carbide MOSFET transistor device.
The source region 320 has a highly doped first conductivity type, and specifically, may have a doping concentration greater than 1E19cm -3 N-type doping.
The doped region 330 is highly doped with the second conductive type, and specifically, the doping concentration may be greater than 1E19cm -3 P-type doping.
The total area of the JFET regions 340 of the circular and polygonal cell structures 300 is relatively large, which effectively increases the area utilization rate of the silicon carbide MOSFET transistor device and reduces the cost of the silicon carbide MOSFET transistor device, but increases the saturation current of the silicon carbide MOSFET transistor device, and increases the short-circuit peak current in the device during short-circuit failure, thereby reducing the short-circuit withstand capability of the silicon carbide MOSFET transistor device. In order to balance the area utilization and robustness of the silicon carbide MOSFET transistor device and to allow both the area utilization and robustness to be compatible, the present application provides an interconnect structure 350.
The interconnect structure 350 may be formed by ion implantation on the top surface of the epitaxial layer 20 of the sic MOSFET transistor device, connecting two adjacent cell structures 300, and crossing two adjacent JFET regions 340. The top surface of the epitaxial layer 20 is the surface of the epitaxial layer 20 away from the substrate 10.
One end of the interconnect structure 350 is connected to the doped region 330 of one cell structure 300, and the other end of the interconnect structure 350 is connected to the doped region 330 of another cell structure 300, so as to realize the interconnection between two adjacent cell structures 300.
It should be noted that all references to "doping depth" in this application refer to the length in the vertical direction perpendicular to the substrate 10. The greater the doping depth, the greater the length in the vertical direction perpendicular to the substrate 10.
The interconnect structure 350 is not limited to the doping depth, depending on the design requirements.
The doping depth of the interconnect structure 350 may be greater than the doping depth of the well region 310, the doping depth of the interconnect structure 350 may also be equal to the doping depth of the well region 310, and the doping depth of the interconnect structure 350 may also be less than the doping depth of the well region 310.
The doping depth of the doped region 330 may be greater than the doping depth of the well region 310, the doping depth of the doped region 330 may also be equal to the doping depth of the well region 310, and the doping depth of the doped region 330 may also be less than the doping depth of the well region 310.
The doping depth of the doped region 330 may be equal to the doping depth of the interconnect structure 350. The doping depth of the doped region 330 may not be equal to the doping depth of the interconnect structure 350, depending on the design requirements.
Fig. 3 isbase:Sub>A schematic diagram ofbase:Sub>A cross-section ofbase:Sub>A silicon carbide MOSFET transistor device provided in embodiment 12 of this application, the cross-section being formed by cutting an active region alongbase:Sub>A section linebase:Sub>A-base:Sub>A'. As shown in fig. 3, in the layout method a, the doping depth of the doped region 330 is equal to the doping depth of the interconnect structure 350. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both less than the doping depth of the well region 310. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both less than the doping depth of the JFET region 340. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than the doping depth of the source region 320. Thus, well region 310 and JFET region 340 can be seen in fig. 3.
Fig. 4 isbase:Sub>A schematic diagram ofbase:Sub>A cross-section ofbase:Sub>A silicon carbide MOSFET transistor device according to example 12 of the present application, the cross-section being formed by sectioning an active region alongbase:Sub>A section linebase:Sub>A-base:Sub>A' in layout modes b and c.
As shown in fig. 4, in layout styles b and c, the doping depth of the doped region 330 is equal to the doping depth of the interconnect structure 350. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than or equal to the doping depth of the well region 310. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than or equal to the doping depth of the JFET region 340. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than the doping depth of the source region 320. Thus, neither well region 310 nor JFET region 340 is visible in fig. 4.
The width of the JFET region 340 is denoted by K' in fig. 3.
Fig. 5 to 7 are more illustrative diagrams from another viewing angle. In fig. 5-7, the width of the JFET region 340 is represented using K ".
Fig. 5 is a schematic diagram of a cross-section of a silicon carbide MOSFET transistor device according to embodiment 12 of the present application, the cross-section being formed by sectioning an active region along a section line B-B' in layout mode a. As shown in fig. 5, in the layout method a, the doping depth of the doped region 330 is equal to the doping depth of the interconnect structure 350. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both less than the doping depth of the well region 310. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both less than the doping depth of the JFET region 340. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than the doping depth of the source region 320.
Fig. 6 is a schematic diagram of a cross-section of a silicon carbide MOSFET transistor device according to example 12 of the present application, the cross-section being taken along a section line B-B' of an active region in layout B. As shown in fig. 6, in the layout method b, the doping depth of the doped region 330 is equal to the doping depth of the interconnect structure 350. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both equal to the doping depth of the well region 310. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both equal to the doping depth of the JFET region 340. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than the doping depth of the source region 320.
Fig. 7 is a schematic diagram of a cross-section of a silicon carbide MOSFET transistor device according to example 12 of the present application, the cross-section being formed by sectioning an active region along a section line B-B'. As shown in fig. 7, in the layout method c, the doping depth of the doped region 330 is equal to the doping depth of the interconnect structure 350. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than the doping depth of the well region 310. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than the doping depth of the JFET region 340. The doping depth of the doped region 330 and the doping depth of the interconnect structure 350 are both greater than the doping depth of the source region 320.
The doping depth of the interconnect structure 350 may be in a range of 0.5 microns or more and 2 microns or less.
In this embodiment, an interconnection structure 350 is designed between two adjacent cell structures 300, so that the two adjacent cell structures 300 are connected through the interconnection structure 350, and at the moment of surge impact or short-circuit fault, plasma can be rapidly diffused from one cell structure 300 to the adjacent cell structure 300, so that the uniform distribution of carrier concentration and current density is obtained, the phenomena of local heat concentration and severe temperature rise inside the device are avoided, and the surge and short-circuit reliability of the device is improved.
In addition, the interconnect structure 350 of the present application also reduces the electric field strength in the gate oxide, improving the reliability of the silicon carbide MOSFET transistor device. The interconnect structure 350 of the present application also reduces the reverse recovery capacitance (Crss/Cgd) and gate charge (Qg) of the silicon carbide MOSFET transistor device, optimizing the dynamic loss of the silicon carbide MOSFET transistor device.
In an embodiment of the present application, the interconnection structure 350 and the doped region 330 are formed on the top surface of the epitaxial layer 20 simultaneously by ion implantation. The interconnect structure 350 and the doped region 330 have the same doping concentration. The interconnect structure 350 and the doped region 330 have the same doping depth.
Specifically, the top surface of the epitaxial layer 20 is the surface of the epitaxial layer 20 away from the substrate 10. In this embodiment, the interconnection structure 350 and the doped region 330 are simultaneously formed on the top surface of the epitaxial layer 20 by ion implantation, and the interconnection structure 350 and the doped region 330 have the same doping concentration and the same doping depth, so that the interconnection structure 350 and the doped region 330 are simultaneously formed on the top surface of the epitaxial layer 20 by the same ion implantation process without additional process or other additional technical equipment, thereby not only saving the technical cost and the material cost, but also improving the processing efficiency.
In an embodiment of the present application, the JFET region 340 is formed on the top surface of the epitaxial layer 20 by ion implantation. The JFET region 340 has a doping concentration greater than or equal to the first conductivity type doping concentration of the epitaxial layer 20.
Specifically, the JFET regions 340 of two adjacent cell structures 300 are connected, and the width of the JFET regions 340 in the extension direction of the sides of the well region 310 is denoted by K (the JFET regions 340 are denoted by K' in fig. 3, and the JFET regions 340 are denoted by K ″ in fig. 5 to 7, where K is used collectively for convenience of explanation), it can be understood that the distance between two adjacent well regions 310 in the extension direction of the sides of the well region 310 is 2K. K is set according to the value of the doping concentration of each structure in the silicon carbide MOSFET transistor device to ensure that the silicon carbide MOSFET transistor device has smaller on-resistance, and under the blocking mode, the adjacent well region 310 can play the role of effective electric field shielding effect to ensure the reliability of the silicon carbide MOSFET transistor device.
It should be noted that the width of the JFET region 340 in the extending direction of the sides of the well region 310 is expressed by "the width of the JFET region 340" for convenience of description, and the width of the JFET region 340 is expressed by the width of the JFET region 340 in the extending direction of the sides of the well region 310.
The JFET region 340 can have a doping concentration less than the doping concentration of the epitaxial layer 20, which increases the on-resistance, and therefore the JFET region 340 of the present application has a doping concentration greater than or equal to the first conductivity type doping concentration of the epitaxial layer 20. For example, when the doping concentration of the epitaxial layer 20 is 8E15cm -3 When the doping concentration of the JFET area 310 is less than 8E15cm -3 The on-resistance is increased.
The doping concentration of the epitaxial layer 20 is 3.5E15cm or more -3 And is less than or equal to 1E17cm -3 Doping concentration range of (a). The doping concentration of the JFET region 340 is greater than or equal to 3.5E15cm -3 And is less than or equal to 5E17cm -3 Doping concentration range of (a).
If the doping concentration of the JFET region 340 is not changed, the larger K is, the lower the on-resistance of the silicon carbide MOSFET transistor device is, but the higher the electric field strength in the gate oxide in the blocking state is, so that the value of K needs to be set according to the requirements of practical application scenarios.
In an embodiment of the present application, the doped region 330 is formed in the well region 310 by ion implantation.
Specifically, the doped region 330 is formed in the well region 310 by ion implantation, and is connected to the well region 310, and an ohmic contact metal (not shown) is formed above the doped region 330. To suppress parasitic bipolar transistors inside the silicon carbide MOSFET transistor device, an ohmic contact metal is simultaneously in contact with the source region 320.
The doping depth of the doped region 330 is not critical. The doping depth of the doped region 330 may be greater than, equal to, or less than the doping depth of the well region 310.
In an embodiment of the present application, the width of the JFET region 340 in a direction parallel to the side 311 of the well region 310 is in a range of values between 0.4 microns or more and 3 microns or less.
Optionally, in an embodiment, the JFET region 340 has a width K of 0.4 microns. In one embodiment, the JFET region 340 has a width K of 2.5 microns. In one embodiment, the JFET region 340 has a width of 1 micron.
In an embodiment of the present application, the well region 310 and the epitaxial layer 20 are a first PN junction, and the well region 310 and the source region 320 are a second PN junction.
Specifically, the well region 310 and the epitaxial layer 20 form a first PN junction. The well region 310 and the source region 320 form a second PN junction. The first PN junction and the second PN junction are homojunctions.
As shown in fig. 8, in an embodiment of the present application, the active area 30 includes a plurality of cell rows 360 and a plurality of cell columns 370. Each cell row 360 includes a plurality of cell structures 300 arranged as a row. Each cell column 370 includes a plurality of cell structures 300 arranged as a column. The plurality of cell rows 360 and the plurality of cell columns 370 are arranged in the active region 30 to form an array.
Specifically, for ease of understanding, the drawings of all embodiments of the present application only show a partial number of cell structures 300, the number of cell structures 300 in the active region 30 of an actual sic MOSFET transistor device is large, and the number of cell structures 300 in the active region 30 in the drawings does not limit the scope of the present application.
In one embodiment of the present application, two adjacent cell rows 370 are arranged in a staggered manner.
Specifically, it has been mentioned in the foregoing that the plurality of cell structures 300 are arranged in an array on the top surface of the epitaxial layer 20. The staggered arrangement is one of the array arrangements. In the embodiment shown in fig. 10, in the embodiment shown in fig. 11, in the embodiment shown in fig. 12, in the embodiment shown in fig. 16, in the embodiment shown in fig. 21, and in the embodiment shown in fig. 22, two adjacent cell columns 370 are arranged in a staggered arrangement.
In one embodiment of the present application, two adjacent cell rows 370 are aligned.
Specifically, the alignment arrangement is one of array arrangements. In the embodiment shown in fig. 8, in the embodiment shown in fig. 13, in the embodiment shown in fig. 14, in the embodiment shown in fig. 15, in the embodiment shown in fig. 17, in the embodiment shown in fig. 18, in the embodiment shown in fig. 19, in the embodiment shown in fig. 20, in the embodiment shown in fig. 23, in the embodiment shown in fig. 24, and in the embodiment shown in fig. 25, two adjacent cell columns 370 are aligned.
In an embodiment of the present application, as shown in fig. 9, the sic MOSFET transistor device further includes a transition region 40, and the transition region 40 is formed on the top surface of the epitaxial layer 20 by ion implantation. The transition region 40 is disposed at the periphery of the active region 30 and surrounds the active region 30.
Specifically, in one embodiment, the transition region 40, the doped region 330 and the interconnect structure 350 are formed on the top surface of the epitaxial layer 20 by a single ion implantation process, and they are formed on the top surface of the epitaxial layer 20 at the same time.
As shown in fig. 9, in an embodiment of the present application, the doped region 330 near the transition region 40 is connected to the transition region 40 through an interconnect structure 350.
In an embodiment of the present application, the interconnection structure 350 is a bar. The interconnect structure 350 extends along the length of the interconnect structure 350.
Specifically, the length direction of the interconnection structure 350 is the extension direction of the longest side of the interconnection structure 350.
In an embodiment of the present application, a projection shape of the well region 310 on the surface of the epitaxial layer 20 is a polygon. The length direction of the interconnect structure 350 is parallel to the extension direction of the side 311 of the well region 310, or the length direction of the interconnect structure 350 is perpendicular to the extension direction of the side 311 of the well region 310, or the length direction of the interconnect structure 350 is parallel to the diagonal direction of the well region 310.
In this embodiment, the projection shape of the well region 310 on the surface of the epitaxial layer 20 is a polygon. For example, fig. 8 shows embodiment 1 in which the projection shape of the well region 310 on the surface of the epitaxial layer 20 is square. Fig. 10 shows that the projection shape of the well region 310 of embodiment 2 on the surface of the epitaxial layer 20 is rectangular. Fig. 22 shows that the projection shape of the well region 310 of the embodiment 14 on the surface of the epitaxial layer 20 is a regular hexagon. Fig. 12 shows that the projection shape of the well region 310 of embodiment 4 on the surface of the epitaxial layer 20 is hexagonal.
In this embodiment, the length direction of the interconnection structure 350 is parallel to the extension direction of the side 311 of the well region 310, or the length direction of the interconnection structure 350 is perpendicular to the extension direction of the side 311 of the well region 310, or the length direction of the interconnection structure 350 is parallel to the diagonal direction of the well region 310, so there are 3 embodiments.
Example (a): the length direction of the interconnect structure 350 is parallel to the extension direction of the side 311 of the well region 310.
Specifically, embodiment 1 shown in fig. 8, embodiment 2 shown in fig. 10, embodiment 3 shown in fig. 11, embodiment 5 shown in fig. 13, embodiment 6 shown in fig. 14, embodiment 7 shown in fig. 15, embodiment 8 shown in fig. 16, embodiment 9 shown in fig. 17, and embodiment 10 shown in fig. 18 are all embodiments in which the length direction of the interconnect structure 350 is parallel to the extension direction of the side 311 of the well region 310.
Example (b): the length direction of the interconnect structure 350 is perpendicular to the extension direction of the side 311 of the well region 310.
Specifically, in embodiment 4 shown in fig. 12, embodiment 14 shown in fig. 22 is an embodiment in which the length direction of the interconnect structure 350 is perpendicular to the extension direction of the side 311 of the well region 310.
Example (iii): the length direction of the interconnect structure 350 is parallel to the diagonal direction of the well region 310.
Specifically, the embodiment 11 shown in fig. 19, the embodiment 12 shown in fig. 20, the embodiment 15 shown in fig. 23, the embodiment 16 shown in fig. 24, and the embodiment 17 shown in fig. 25 are all embodiments in which the length direction of the interconnect structure 350 is parallel to the diagonal direction of the well region 310.
In addition to the example (a), the example (b), and the example (c), there is also an example (d).
In an embodiment of the present application, that is, embodiment (four), a projection shape of the well region 310 on the surface of the epitaxial layer 20 is a circle. The length direction of the interconnection structure 350 is parallel to the diagonal direction of the external regular hexagon of the well region 310.
Specifically, in embodiment 13 shown in fig. 21, a projection shape of the well region 310 on the surface of the epitaxial layer 20 is a circle, and a length direction of the interconnect structure 350 is parallel to a diagonal direction of a regular hexagon circumscribing the well region 310.
In one embodiment of the present application, the number of the interconnect structures 350 starting from the doped region 330 of the cell structure 300 in each cell structure 300 is 2, 4 or 6. This includes example (five), example (six) and example (seven).
Example (five)
In one embodiment of the present application, the number of the interconnect structures 350 starting from the doped region 330 of the cell structure 300 in each cell structure 300 is 2.
Specifically, in the embodiment 1 shown in fig. 8, the embodiment 2 shown in fig. 10, the embodiment 3 shown in fig. 11, the embodiment 4 shown in fig. 12, and the embodiment 11 shown in fig. 19, the doped region 330 in each cell structure 300 of these 4 embodiments leads out 2 interconnect structures 350, that is, the number of the interconnect structures 350 starting from the doped region 330 is 2.
Example (VI)
In one embodiment of the present application, the number of the interconnection structures 350 starting from the doped region 330 of each cell structure 300 in each cell structure 300 is 4.
Specifically, in the embodiment 5 shown in fig. 13, the embodiment 6 shown in fig. 14, and the embodiment 12 shown in fig. 20, the doped region 330 in each cell structure 300 of the 3 embodiments leads to 4 interconnect structures 350, i.e., the number of the interconnect structures 350 starting from the doped region 330 is 4.
Example (seven)
In one embodiment of the present application, the number of the interconnect structures 350 starting from the doped region 330 of the cell structure 300 in each cell structure 300 is 6.
Specifically, in the embodiment 13 shown in fig. 21 and the embodiment 14 shown in fig. 22, the doped region 330 in each cell structure 300 leads to 6 interconnect structures 350, i.e., the number of the interconnect structures 350 starting from the doped region 330 is 6.
The greater the distribution density of the interconnect structures 350, the greater the number of interconnect structures 350 representing the same active area 30 area (which may be referred to as a unit area), the higher the robustness performance. However, interconnect structure 350, on the other hand, sacrifices the JEFT region 340 of the silicon carbide MOSFET transistor device. In other words, a greater distribution density of the interconnect structures 350 means a greater series resistance with a greater turn-on capability of the sacrificial silicon carbide MOSFET transistor device. Thus maintaining an even distribution density of the interconnect structure 350 and an overall robustness of the silicon carbide MOSFET transistor device. Example (five) this is true for example (six) and example (seven).
The present application also includes the following embodiments.
Example (eight)
In one embodiment of the present application, in every two adjacent cell structures 300 in each cell row 360, the number of the interconnect structures 350 starting from the doped region 330 of one cell structure 300 is 2, and the number of the interconnect structures 350 starting from the doped region 330 of another cell structure 300 is 0.
Specifically, please refer to fig. 15 for a schematic diagram of embodiment 7 on the basis that the length direction of the interconnect structure 350 is parallel to the extending direction of the side 311 of the well region 310, which is an implementation manner of this embodiment.
As shown in fig. 15, two adjacent cell structures 300 are selected in one cell row 360, and it can be seen that the number of the interconnect structures 350 starting from the doped region 330 of one cell structure 300 is 2, and the number of the interconnect structures 350 starting from the doped region 330 of another cell structure 300 is 0.
Example 8 shown in fig. 16 and example 15 shown in fig. 23 are two embodiments in this example.
Example (nine)
In one embodiment of the present application, in every two adjacent cell structures 300 in each cell column 370, the number of the interconnect structures 350 starting from the doped region 330 of one cell structure 300 is 4, and the number of the interconnect structures 350 starting from the doped region 330 of the other cell structure 300 is 2.
Specifically, please refer to fig. 17 for a schematic diagram of embodiment 9 on the basis that the length direction of the interconnect structure 350 is parallel to the extending direction of the side 311 of the well region 310, which is an implementation manner of this embodiment.
As shown in fig. 17, two adjacent cell structures 300 are selected in one cell column 370, and it can be seen that the number of the interconnect structures 350 starting from the doped region 330 of one cell structure 300 is 4, and the number of the interconnect structures 350 starting from the doped region 330 of another cell structure 300 is 2.
Example 16 shown in fig. 24 is also an embodiment under this example.
Example (ten)
In an embodiment of the present application, in two adjacent cell rows 360, in each two adjacent cell structures 300 in one cell row 360, the number of the interconnection structures 350 starting from the doped region 330 of one cell structure 300 is 4, and the number of the interconnection structures 350 starting from the doped region 330 of another cell structure 300 is 2. In every two adjacent cell structures 300 in another cell row 360, the number of the interconnect structures 350 starting from the doped region 330 of one cell structure 300 is 2, and the number of the interconnect structures 350 starting from the doped region 330 of another cell structure 300 is 0.
Specifically, on the basis that the length direction of the interconnect structure 350 is parallel to the extending direction of the side 311 of the well region 310, please refer to the schematic diagram of embodiment 10 shown in fig. 18, which is an implementation manner of this embodiment.
As shown in fig. 18, two adjacent cell rows 360, i.e., cell row X and cell row Y, are selected.
Two adjacent cell structures 300 are selected in the cell row X, and it can be seen that the number of the interconnect structures 350 starting from the doped region 330 of one cell structure 300 is 4, and the number of the interconnect structures 350 starting from the doped region 330 of another cell structure 300 is 2.
Two adjacent cell structures 300 are selected in the cell row Y, and it can be seen that the number of the interconnection structures 350 starting from the doped region 330 of one cell structure 300 is 2, and the number of the interconnection structures 350 starting from the doped region 330 of the other cell structure 300 is 0.
Example (eleven)
In one embodiment of the present application, in every two adjacent cell structures 300 in each cell row 360, the number of the interconnect structures 350 starting from the doped region 330 of one cell structure 300 is 4, and the number of the interconnect structures 350 starting from the doped region 330 of another cell structure 300 is 0.
Specifically, please refer to fig. 25 for a schematic diagram of embodiment 17 on the basis that the length direction of the interconnect structure 350 is parallel to the diagonal direction of the active region 30, which is an implementation manner of this embodiment.
As shown in fig. 25, two adjacent cell structures 300 are selected in one cell row 360, and it can be seen that the number of the interconnect structures 350 starting from the doped region 330 of one cell structure 300 is 4, and the number of the interconnect structures 350 starting from the doped region 330 of another cell structure 300 is 0.
In one embodiment of the present application, the cell structure 300 is square in shape. In the embodiments illustrated in fig. 8, 11, 13, 15, 16, 17, 18, 19, 20, 23, 24, and 25, the shape of the cell structure 300 is square.
In one embodiment of the present application, the shape of the cell structure 300 is circular. In the embodiment shown in fig. 21, the shape of the cell structure 300 is circular.
In one embodiment of the present application, the shape of the cell structure 300 is a regular hexagon. In the embodiment shown in fig. 22, the shape of the cell structure 300 is a regular hexagon.
In one embodiment of the present application, the shape of the cell structure 300 is a non-regular polygon. In the embodiment shown in fig. 10, 12, and 14, the shape of the cell structure 300 is a non-regular polygon.
FIG. 26 shows short circuit test data for silicon carbide MOSFET transistor devices having different cell structure designs at different bus voltages (400V/600V/800V).
As shown in fig. 26, device a is a regular hexagonal-cell silicon carbide MOSFET transistor device without the interconnect structure 350 of the present application, device B is a regular hexagonal-cell silicon carbide MOSFET transistor device with the interconnect structure 350 of the present application, and device C is a square-cell silicon carbide MOSFET transistor device with the interconnect structure 350 of the present application. In fig. 26, the horizontal axis represents the bus voltage in volts (V). The left vertical axis in fig. 26 represents the short circuit withstand time in microseconds (μ s). Short circuit withstand time, that is, the longest short circuit pulse width which ensures that the device does not fail under a certain short circuit experiment condition. The right vertical axis in fig. 26 represents short circuit withstand energy in joules (J). Short circuit withstand energy, namely, the maximum short circuit energy for ensuring that the device does not fail under certain short circuit experimental conditions.
From FIG. 26 we can conclude that the data is confirmed:
the interconnect structure 350 provided by the present application can effectively enhance the short circuit endurance of the device. At different bus voltages, the short-circuit withstand time of device B was raised by 60% (see 60% increase in fig. 26), 67% (see 67% increase in fig. 26), and 33% (see 33% increase in fig. 26), respectively, compared to device a.
The interconnection structure 350 provided by the application can help to reduce the short-circuit peak current of the device, increase the short-circuit robustness of the device, and further balance the area utilization rate and the robustness of the device, so that the two are considered.
In an embodiment of the invention, the first conductive type may be an N-type, and the second conductive type may be a P-type. In other embodiments, the first conductivity type may also be P-type, and the second conductivity type may also be N-type.
The technical features of the embodiments described above may be arbitrarily combined, the order of execution of the method steps is not limited, and for simplicity of description, all possible combinations of the technical features in the embodiments described above are not described, however, as long as there is no contradiction between the combinations of the technical features, the combinations should be considered as being within the scope of the present description.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (14)
1. A silicon carbide MOSFET transistor device, comprising:
a substrate (10), the substrate (10) having a first conductivity type;
an epitaxial layer (20), the epitaxial layer (20) being disposed over the substrate (10), and the epitaxial layer (20) having a first conductivity type;
an active region (30) formed on a top surface of the epitaxial layer (20);
the active region (30) comprises:
a plurality of cell structures (300), the plurality of cell structures (300) being arranged in an array on a top surface of the epitaxial layer (20); the shape of the cellular structure (300) is circular or polygonal;
each cell structure (300) comprises:
a well region (310), the well region (310) having a second conductivity type;
a source region (320) highly doped of a first conductivity type located within the well region (310);
a doped region (330) disposed within the well region (310), the doped region being highly doped with a second conductivity type; the source region (320) is located around the doped region (330);
a JFET region (340) disposed around the well region (310); in a straight line direction, the JFET areas (340) of two adjacent cellular structures (300) are connected;
the doping region (330) of each cell structure (300) and the doping regions (330) of N cell structures (300) adjacent to the cell structure (300) are respectively connected with each other through an interconnection structure (350), N is a natural number, and at least one pair of cell structures (300) with the doping regions (330) connected with each other exist;
the interconnection structure (350) and the doped region (330) are formed on the top surface of the epitaxial layer (20) simultaneously in an ion implantation mode, are connected with two adjacent cell structures (300) and cross two adjacent JFET regions (340), the conductivity type of the interconnection structure (350) is the same as that of the doped region (330), the doping concentration of the interconnection structure (350) and the doping region (330) is the same, and the doping depth is the same.
2. The silicon carbide MOSFET transistor device of claim 1, wherein the active region (30) comprises:
a plurality of cell rows (360), each cell row (360) comprising a plurality of cell structures (300) arranged as a row;
a plurality of cell columns (370), each cell column (370) comprising a plurality of cell structures (300) arranged in a column;
the plurality of cell rows (360) and the plurality of cell columns (370) are arranged in the active region (30) to form an array.
3. The silicon carbide MOSFET transistor device of claim 2, wherein adjacent two of the cell columns (370) are in a staggered arrangement.
4. The silicon carbide MOSFET transistor device of claim 2, wherein adjacent two of the cell columns (370) are aligned.
5. The silicon carbide MOSFET transistor device of claim 2, further comprising:
a transition region (40) formed on the top surface of the epitaxial layer (20) by ion implantation; the transition region (40) is disposed at a periphery of the active region (30) and surrounds the active region (30).
6. The silicon carbide MOSFET transistor device of claim 5, wherein the doped region (330) proximate the transition region (40) is connected to the transition region (40) by an interconnect structure (350).
7. The silicon carbide MOSFET transistor device of claim 1, wherein the interconnect structure (350) is strip-shaped and extends along a length of the interconnect structure (350).
8. The silicon carbide MOSFET transistor device of claim 1, wherein a projected shape of the well region (310) on the surface of the epitaxial layer (20) is a polygon, and a length direction of the interconnect structure (350) is parallel to an extension direction of a side (311) of the well region (310) or a length direction of the interconnect structure (350) is perpendicular to an extension direction of a side (311) of the well region (310) or a length direction of the interconnect structure (350) is parallel to a diagonal direction of the well region (310).
9. The silicon carbide MOSFET transistor device of claim 1, wherein the well region (310) has a circular projected shape on the surface of the epitaxial layer (20), and the length direction of the interconnect structure (350) is parallel to a diagonal direction of a circumscribed regular hexagon of the well region (310).
10. The silicon carbide MOSFET transistor device of claim 1, wherein within each cell structure (300), the number of interconnect structures (350) starting from the doped region (330) of the cell structure (300) is 2 or 4 or 6.
11. The silicon carbide MOSFET transistor device of claim 2, wherein in each two adjacent cell structures (300) in each cell row (360), the number of interconnect structures (350) starting from the doped region (330) of one cell structure (300) is 2, and the number of interconnect structures (350) starting from the doped region (330) of another cell structure (300) is 0.
12. The silicon carbide MOSFET transistor device of claim 2, wherein, in each of two adjacent cell structures (300) in each of the cell columns (370), the number of interconnect structures (350) starting from the doped region (330) of one cell structure (300) is 4, and the number of interconnect structures (350) starting from the doped region (330) of another cell structure (300) is 2.
13. The silicon carbide MOSFET transistor device of claim 2, wherein, in each of two adjacent cell structures (300) in one cell row (360), the number of interconnect structures (350) starting from the doped region (330) of one cell structure (300) is 4, the number of interconnect structures (350) starting from the doped region (330) of another cell structure (300) is 2, and the number of interconnect structures (350) starting from the doped region (330) of one cell structure (300) in each of two adjacent cell structures (300) in the other cell row (360) is 2, and the number of interconnect structures (350) starting from the doped region (330) of another cell structure (300) is 0.
14. The silicon carbide MOSFET transistor device of claim 2, wherein in each two adjacent cell structures (300) in each cell row (360), the number of interconnect structures (350) starting from the doped region (330) of one cell structure (300) is 4, and the number of interconnect structures (350) starting from the doped region (330) of another cell structure (300) is 0.
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