CN112599524B - Silicon carbide power MOSFET device with enhanced reliability - Google Patents
Silicon carbide power MOSFET device with enhanced reliability Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 177
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 177
- 210000000746 body region Anatomy 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000005669 field effect Effects 0.000 claims description 3
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- 238000001465 metallisation Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
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- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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- 238000002513 implantation Methods 0.000 description 1
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- 238000005468 ion implantation Methods 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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- 238000010248 power generation Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
The invention provides a silicon carbide power MOSFET device with enhanced reliability, which comprises a plurality of traditional silicon carbide MOSFET cells and a plurality of enhanced reliability cells, wherein the structure of the silicon carbide power MOSFET device comprises a substrate, a source electrode and a drain electrode, and further comprises a first N-type silicon carbide region positioned above the substrate; a first source region including a first P-type body region, a second P-type body region and a second N-type silicon carbide region, located above the first N-type silicon carbide region; a first isolated gate region over the first source region. The first surface of the unit cell is designed to be polygonal or circular, and the first P-type body regions in the unit cell with enhanced reliability are connected into a whole. The structure reduces the area of a JFET region and improves the reliability of the gate oxide of the device; the area of the first P type body region is increased, and the avalanche tolerance of the device is improved; through the design of the first P type body regions which are connected into a whole, the potentials of the first P type body regions of all the unit cells are equal, and the short-circuit capacity of the device is effectively improved.
Description
Technical Field
The present invention relates to semiconductor devices, and more particularly to a silicon carbide power MOSFET device with enhanced reliability.
Background
The performance of traditional silicon-based semiconductor devices has gradually approached the physical limit of materials, and devices made of third-generation semiconductor materials represented by silicon carbide have excellent working capabilities of high frequency, high voltage, high temperature resistance, radiation resistance and the like, and can realize higher power density and higher efficiency.
Silicon carbide power MOSFET is taken as a representative of SiC switch devices, has the advantages of low switching loss, high working frequency, easiness in driving, suitability for parallel connection and the like, and is gradually popularized and used in application scenes of electric vehicles, charging piles, new energy power generation, industrial control, flexible direct-current power transmission and the like. Fig. 1-1 is a cross-sectional view 000 of a conventional silicon carbide power MOSFET cell. The conventional silicon carbide power MOSFET cell comprises a drain electrode 1, a source electrode 11, a first isolation gate region 13, a substrate 2, a first N-type silicon carbide region 3, a first source electrode region 12 and a JFET region 7. The first N-type silicon carbide region 3 has a first N-type doping concentration, is positioned above the substrate 2 and has a first surface 14; the substrate 2 has a second surface 15. The JFET region 7 is adjacent to the first N-type silicon carbide region 3 or within the first N-type silicon carbide region 3; the first source region 12 is located above the first N-type silicon carbide region 3 and on two sides of the JFET region 7, the first source region 12 includes a second N-type silicon carbide region 5, a first P-type body region 4, and a second P-type body region 6, the second N-type silicon carbide region 5 has a second N-type doping concentration, the second N-type doping concentration may be greater than the first N-type doping concentration, the first P-type body region 4 has a first P-type doping concentration, the second P-type body region 6 has a second P-type doping concentration, and the second P-type doping concentration may be greater than the first P-type doping concentration; the first isolation gate region 13 is positioned above the JFET region 7 and the first source region 12, and the first isolation gate region 13 comprises a gate oxide layer 8, a gate electrode layer 9 and a passivation layer 10; the source 11 comprises a first metallization layer extending over the first surface 14 and forming an ohmic contact at an interface location 001 in direct contact with the first source region 12. The drain 1 comprises a second metallization layer extending below the second surface 15 and forming an ohmic contact with the substrate 2 at an interface location 002.
Fig. 1-2 is a top view of a silicon carbide power MOSFET device 000-1 in a striped arrangement on first surface 14. Comprises a plurality of conventional silicon carbide power MOSFET cells 000 arranged periodically in a first direction alpha and a fourth direction delta in a stripe arrangement.
Fig. 1-3 are top views of silicon carbide power MOSFET devices 000-2 in a hexagonal arrangement at first surface 14. Comprises a plurality of conventional silicon carbide power MOSFET cells 000 which are arranged periodically in a first direction alpha, a second direction beta and a third direction gamma and are in a hexagonal arrangement. The hexagonal cell design of fig. 1-3 allows for higher device integration than the stripe design of fig. 1-2, but the JFET area footprint of the device is higher with a corresponding decrease in reliability.
Compared with the traditional Si IGBT module, the SiC MOSFET can improve the system efficiency due to lower conduction loss and faster switching frequency. However, in the development of power electronic equipment technology, the stability and reliability of the system are another important consideration while pursuing the work efficiency and power density. The reliability of silicon carbide power MOSFET devices is a critical factor affecting their practical application in power electronic systems. The short circuit capability, surge capability and avalanche tolerance of the device are improved in the design of the silicon carbide power MOSFET device, and the design of the silicon carbide power MOSFET device has become a key problem as the more optimized device performance is pursued.
Disclosure of Invention
To address one or more of the above-identified problems of the prior art, the present invention is directed to a silicon carbide power MOSFET device with enhanced reliability.
According to an embodiment of the present invention, there is provided a silicon carbide power MOSFET device with enhanced reliability, including a substrate, a silicon carbide region above the substrate, and a source region within the silicon carbide region, a body region within the source region, the silicon carbide power MOSFET device comprising: the silicon carbide power MOSFET device comprises a plurality of enhanced reliability cells and a plurality of traditional silicon carbide MOSFET cells, wherein the enhanced reliability cells and the traditional silicon carbide MOSFET cells are arranged in the silicon carbide power MOSFET device in a polygonal or circular shape, an independent JFET (junction field effect transistor) area is arranged between adjacent body areas of the traditional silicon carbide MOSFET cells, the source areas of the traditional silicon carbide MOSFET cells are located on two sides of the JFET area, and the body areas in each enhanced reliability cell are connected into a whole.
According to yet another embodiment of the present invention, there is provided a silicon carbide power MOSFET device with enhanced reliability, including a substrate, a silicon carbide region located over the substrate, a source region located within the silicon carbide region, and a body region located within the source region, the silicon carbide power MOSFET device comprising: a plurality of enhanced reliability cells and a plurality of conventional silicon carbide MOSFET cells arranged in an octagonal or quadrilateral arrangement within the silicon carbide power MOSFET device at a surface of the silicon carbide region, wherein adjacent body regions of the conventional silicon carbide MOSFET cells include a separate JFET region therebetween, the source regions of the conventional silicon carbide MOSFET cells are located on both sides of the JFET region, and the body regions within each enhanced reliability cell are integrally connected.
The silicon carbide power MOSFET device with the enhanced reliability and the manufacturing method thereof can obviously reduce the area of a JFET (junction field effect transistor) region, reduce the electric field intensity of a gate oxide layer and improve the reliability of gate oxide of the device. Meanwhile, the avalanche tolerance of the device can be obviously improved by increasing the area of the first P type body region. In addition, the potentials of the first P type body regions of all the unit cells are equal through interconnection, and the short-circuit capacity of the device can be effectively improved. The silicon carbide power MOSFET device with the enhanced reliability and the manufacturing method thereof can improve the reliability of the device, and have high feasibility and good application prospect under the conditions of laboratories and industrial production.
Drawings
Fig. 1-1 is a cross-sectional view of a conventional silicon carbide power MOSFET cell 000;
fig. 1-2 is a top view of a conventional silicon carbide power MOSFET device 000-1, wherein the MOSFET device 000-1 includes a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, the conventional silicon carbide power MOSFET cells being arranged in a stripe arrangement periodically in a plurality of directions within the silicon carbide power MOSFET device 000-1;
1-3 are top views of a conventional silicon carbide power MOSFET device 000-2, the MOSFET device 000-2 comprising a plurality of conventional silicon carbide power MOSFET cells 000 as shown in FIG. 1-1, the conventional silicon carbide power MOSFET cells being arranged in a hexagonal arrangement periodically in a plurality of directions within the silicon carbide power MOSFET device 000-2;
FIG. 2 is a cross-sectional view of an enhanced reliability cell 100 according to an embodiment of the invention;
fig. 3-1 is a top view of a silicon carbide power MOSFET device 200 according to an embodiment of the invention, the MOSFET device 200 including a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the conventional silicon carbide power MOSFET cells and enhanced reliability cells being in a hexagonal arrangement and being periodically arranged in the silicon carbide power MOSFET device 200 in a plurality of directions;
fig. 3-2 is a top view of a silicon carbide power MOSFET device 200-1 according to an embodiment of the invention, the MOSFET device 200-1 including a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the conventional silicon carbide power MOSFET cells and enhanced reliability cells being arranged in a hexagonal arrangement periodically in a plurality of directions within the silicon carbide power MOSFET device 200-1;
fig. 4 is a top view of a silicon carbide power MOSFET device 300 according to an embodiment of the present invention, the MOSFET device 300 comprising a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the conventional silicon carbide power MOSFET cells and enhanced reliability cells being arranged in a quadrilateral arrangement and periodically arranged in the silicon carbide power MOSFET device 300 in a plurality of directions;
fig. 5 is a top view of a silicon carbide power MOSFET device 400 according to an embodiment of the invention, the MOSFET device 400 including a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the conventional silicon carbide power MOSFET cells and enhanced reliability cells being in a circular arrangement and being periodically arranged in the silicon carbide power MOSFET device 400 in a plurality of directions;
fig. 6 is a top view of a silicon carbide power MOSFET device 500 in accordance with an embodiment of the present invention, the MOSFET device 500 including a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the conventional silicon carbide power MOSFET cells and enhanced reliability cells being in an octagonal arrangement and being periodically arranged in the silicon carbide power MOSFET device 500 in a plurality of directions;
fig. 7 is a flow chart 600 of an enhanced reliability silicon carbide power MOSFET device fabricated in accordance with an embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those of ordinary skill in the art that these specific details are not required in order to practice the present invention. Furthermore, in some embodiments, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present invention.
Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the figures provided herein are for illustrative purposes, and wherein like reference numerals refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The power MOSFET device of the invention includes but is not limited to planar MOSFET, trench MOSFET, and split gate MOSFET, and the material includes but is not limited to silicon carbide, gallium nitride, and silicon.
Fig. 2 is a cross-sectional view 100 of an enhanced reliability cell. The enhanced reliability cell includes a drain 16, a source 25, a first isolation gate region 27, a substrate 17, a first N-type silicon carbide region 18, a first source region 26. The substrate 17 has a second surface 29. The first N-type silicon carbide region 18 is located above the substrate 17, has a first surface 28 and has a first N-type doping concentration; the first source region 26 is located above the first N-type silicon carbide region 18, the first source region 26 includes a second N-type silicon carbide region 20, a first P-type body region 19 and a second P-type body region 21, the second N-type silicon carbide region 20 has a second N-type doping concentration, the first P-type body region 19 has a first P-type doping concentration, and the second P-type body region 21 has a second P-type doping concentration; the first isolation gate region 27 is located above the first source region 26, the first isolation gate region 27 includes a gate oxide layer 22, a gate electrode layer 23, and a passivation layer 24; the source 25 comprises a first metallization layer extending over the first surface 28 and in direct contact with the first source region 26 forming an ohmic contact at an interface location 003. The drain 16 comprises a second metallization layer extending below the second surface 29 and forming an ohmic contact with the substrate 17 at an interface location 004.
In one embodiment, the enhanced reliability cell 100 of fig. 2 differs from the conventional silicon carbide power MOSFET cell 000 of fig. 1 in that the first source regions 26 of the enhanced reliability cell 100 of fig. 2 have adjacent first P-type body regions 19 that are connected together, i.e., the adjacent first P-type body regions 19 may be in direct contact to form the same closed continuous region, and there may be no JFET region between adjacent first P-type body regions 19 as shown in fig. 1.
Fig. 3-1 is a top view of a silicon carbide power MOSFET device 200 according to an embodiment of the invention, the MOSFET device 200 comprising a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the plurality of conventional silicon carbide power MOSFET cells 000 and the plurality of enhanced reliability cells 100 being in a hexagonal arrangement and being periodically arranged within the silicon carbide power MOSFET device 200 in a first direction α, a second direction β, and a third direction γ.
The silicon carbide power MOSFET device 200 with enhanced reliability shown in fig. 3-1 differs from the conventional silicon carbide power MOSFET device 000-2 shown in fig. 1-3 in that adjacent first P-type body regions 19 in each enhanced reliability cell 100 can be joined together by the introduction of the enhanced reliability cell 100, reducing the total area of the JFET region 7 in the device, such a structure that the area of the JFET region is significantly reduced, the electric field strength of the gate oxide layer is reduced, and the reliability of the gate oxide of the device is improved. Meanwhile, the avalanche tolerance of the device can be obviously improved by increasing the area of the first P type body region. In addition, the first P type body regions of the cells are designed to be connected into a whole, so that the potential of the first P type body regions of the cells is equal, and the short-circuit capacity of the device can be effectively improved. This applies to all polygonal structural designs incorporating the enhanced reliability cell 100.
In one embodiment as shown in fig. 3-1, the first P-type body region 19 connection location of each enhancement mode cell can be located at a corner of the hexagon (e.g., corner θ), and the JFET region 7 can be located between the nearest two sides of adjacent hexagonal cells (e.g., between sides μ and φ).
Fig. 3-1 is a top view of a silicon carbide power MOSFET device 200-1 according to an embodiment of the invention, the MOSFET device 200-1 including a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the plurality of conventional silicon carbide power MOSFET cells 000 and the plurality of enhanced reliability cells 100 being in a hexagonal arrangement and being periodically arranged within the silicon carbide power MOSFET device 200-1 in a first direction α, a second direction β, and a third direction γ.
The silicon carbide power MOSFET device 200-1 with enhanced reliability shown in fig. 3-2 differs from the silicon carbide power MOSFET device 200 with enhanced reliability shown in fig. 3-1 in that not all of the cells at the hexagonal corner locations are enhanced reliability cells 100. That is, in one embodiment of the present invention, the body tie location of the enhanced reliability cell may be located at each corner of the polygon or at a certain corner of the polygon.
In one embodiment shown in fig. 3-2, some of the cells at the corner locations of the hexagon are reliability-enhancing cells 100 and the remaining cells at the corner locations of the hexagon are conventional silicon carbide power MOSFET cells 000.
In one embodiment shown in fig. 3-2, the ratio of the number of enhanced reliability cells 100 at the hexagonal corner locations to the number of conventional silicon carbide power MOSFET cells 000 is 1: 1. In one embodiment, the ratio of the number of two cells at the corner positions of the hexagon can be any value. Fig. 4 is a top view of a silicon carbide power MOSFET device 300 according to an embodiment of the present invention, the MOSFET device 300 comprising a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the conventional silicon carbide power MOSFET cells 000 and the enhanced reliability cells 100 being in a quadrilateral arrangement, periodically arranged in the silicon carbide power MOSFET device 300 in a first direction a and a fourth direction δ; the device integration level (higher than that of a strip design) equal to that of a hexagonal structure design can be obtained by adopting a quadrilateral structure design, and meanwhile, the reliability of the device is improved by introducing the reliability-enhancing unit cell 100.
In one embodiment as shown in fig. 4, the first P-type body region 19 connection location of each enhancement mode cell may be located at a top corner of the quadrilateral (e.g., top corner θ) and the JFET region 7 location may be located between the nearest two sides of adjacent quadrilateral cells (e.g., between sides μ and φ).
Fig. 5 is a top view of a silicon carbide power MOSFET device 400 according to an embodiment of the invention, the MOSFET device 400 including a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1 and a plurality of enhanced reliability cells 100 as shown in fig. 2, the conventional silicon carbide power MOSFET cells 000 and the enhanced reliability cells 100 being in a circular arrangement periodically arranged in the silicon carbide power MOSFET device 400 in a first direction α, a second direction β, and a third direction γ; the circular structure can weaken the electric field concentration phenomenon when the device blocks high voltage, enable the device to bear higher withstand voltage, and meanwhile, the reliability of the device is improved by introducing the reliability-enhanced unit cell 100.
In one embodiment, as shown in fig. 5, the JFET region 7 may be located between the nearest two arcs of adjacent circular cells (e.g., between arc epsilon and arc eta).
Fig. 6 is a top view of a silicon carbide power MOSFET device 500 in accordance with an embodiment of the present invention, the MOSFET device 500 including a plurality of conventional silicon carbide power MOSFET cells 000 as shown in fig. 1-1, and a plurality of enhanced reliability cells 100 as shown in fig. 2, the conventional silicon carbide power MOSFET cells and the enhanced reliability cells being in an octagonal or quadrilateral arrangement and being periodically arranged within the silicon carbide power MOSFET device 500 in a first direction a and a fourth direction δ; in one embodiment, the quadrilateral first source regions 26 (including the first P-type body regions 19, the second P-type body regions 21 and the second N-type silicon carbide regions 20) may not be filled in part of the octagonal densely-arranged gaps. Compared with the traditional strip-shaped cellular design, the octagonal structural design can increase the integration level of the device, and in addition, the electric field concentration phenomenon when the octagonal structure blocks high voltage is superior to that of a hexagonal structure and a square structure, so that the device can bear higher withstand voltage.
In one embodiment, as shown in FIG. 6, the first P-type body region 19 attachment locations for each enhanced cell may be located at the corners of an octagon and a quadrilateral (e.g., corner θ) 1 And apex angle θ 2 ) The JFET region 7 may be located between the nearest two sides of adjacent octagonal cells (e.g., side μ 1 And the side phi 1 Between) or between two sides of adjacent octagonal cells that are closest to the quadrilateral cells (e.g., side μ 2 And the side phi 2 In between).
In the embodiment shown in fig. 3-6, regions of the conventional silicon carbide power MOSFET cell 000 and the enhanced reliability cell 100 of the same name but different numbers can be implemented in the same process step and can be considered to be the same region, except for the first P-type body region 19 and the first P-type body region 4. In the embodiments shown in fig. 3-6, the number of conventional silicon carbide power MOSFET cells 000 and the number of enhanced reliability cells 100 and their ratios in a device can be determined according to actual requirements. The plurality of reliability-enhancing cells and the conventional silicon carbide MOSFET cells are periodically arranged in a plurality of directions, wherein the plurality of reliability-enhancing cells and the conventional silicon carbide MOSFET cells may be arranged in the same shape or in different shapes.
Fig. 7 is a flow chart 600 of fabricating a silicon carbide power MOSFET for an enhancement body diode according to an embodiment of the invention. The manufacturing method comprises steps S1-S5.
Step S1, growing a first N-type silicon carbide region on the substrate, wherein the first N-type silicon carbide region has a first N-type doping concentration;
step S2, a first source region is formed by multiple implantation on the first N-type silicon carbide region, the first source region includes a second N-type silicon carbide region, a first P-type body region and a second P-type body region, the second N-type silicon carbide region has a second N-type doping concentration, the first P-type body region has a first P-type doping concentration, and the second P-type body region has a second P-type doping concentration. In a conventional power MOSFET cell, a JFET region is between the first source regions, and in one embodiment, the JFET region is formed by ion implantation using a mask on the first N-type silicon carbide region and has a third N-type doping concentration;
step S3, forming an isolation gate region on the first N-type silicon carbide region, the oxide layer being grown by thermal oxygen, in one embodiment, the method further comprises forming thermal oxygen by chemical vapor deposition;
step S4, growing a first metallization layer on the first N-type silicon carbide region and on the first isolation gate region; in one embodiment, the first metallization layer is grown by using a Cu metal material to replace a traditional Al metal so as to improve the melting temperature of an electrode material, thereby improving the surge current resistance of the device;
step S5, a second metallization layer is grown under the substrate.
For clarity of explanation of the embodiments, a P-type body region, a P-type silicon carbide region, an N-type silicon carbide region, and the like are used for illustration, but it should be noted that in other embodiments, the regions are not limited to the doping type illustrated in the embodiments, the P-type body region may be an N-type body region, and the P-type silicon carbide region may be an N-type silicon carbide region.
For clarity of explanation of the embodiments, a P-type body region, a P-type silicon carbide region, an N-type silicon carbide region, and the like are used for illustration, but it should be noted that in other embodiments, the doping type is not limited to that illustrated in the embodiments, the P-type body region may be an N-type body region, and the P-type silicon carbide region may be an N-type silicon carbide region.
While the present invention has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalence of such metes and bounds are therefore intended to be embraced by the appended claims.
Claims (10)
1. A silicon carbide power MOSFET device of enhanced reliability, the silicon carbide power MOSFET device being a vertical device comprising a substrate, a silicon carbide region above the substrate and a source region within the silicon carbide region, a body region within the source region, the silicon carbide power MOSFET device comprising: the silicon carbide power MOSFET device comprises a plurality of enhanced reliability cells and a plurality of traditional silicon carbide MOSFET cells, wherein the enhanced reliability cells and the traditional silicon carbide MOSFET cells are arranged in the silicon carbide power MOSFET device in a polygonal or circular mode, independent JFET (junction field effect transistor) areas are arranged between adjacent body areas of the traditional silicon carbide MOSFET cells, source areas of the traditional silicon carbide MOSFET cells are located on two sides of the JFET areas, and the adjacent body areas in the source areas are connected into a whole.
2. The silicon carbide power MOSFET device of claim 1, wherein when the plurality of enhanced reliability cells and the plurality of conventional silicon carbide MOSFET cells are arranged in a polygon within the silicon carbide power MOSFET device, the body contact locations of the enhanced reliability cells are located at the top corners of the polygon.
3. The silicon carbide power MOSFET device of claim 1, wherein the JFET region is located between the nearest two sides of adjacent polygons when the plurality of enhanced reliability cells and plurality of conventional silicon carbide MOSFET cells are arranged within the silicon carbide power MOSFET device in polygons.
4. The silicon carbide power MOSFET device of claim 1, wherein when the plurality of enhanced reliability cells and the plurality of conventional silicon carbide MOSFET cells are arranged in a polygon within the silicon carbide power MOSFET device, some of the cells at the corners of the polygon are enhanced reliability cells and the remaining cells at the corners of the polygon are conventional silicon carbide power MOSFET cells.
5. The silicon carbide power MOSFET device of claim 1, wherein the JFET region is located between the two nearest-most arcs when the plurality of enhanced reliability cells and the plurality of conventional silicon carbide MOSFET cells are arranged in a circle within the silicon carbide power MOSFET device at a surface of the silicon carbide region.
6. The silicon carbide power MOSFET device of claim 1, wherein the plurality of enhanced reliability cells and conventional silicon carbide MOSFET cells are arranged periodically in a plurality of directions.
7. The silicon carbide power MOSFET device of claim 6, wherein the plurality of enhanced reliability cells and the conventional silicon carbide MOSFET cells are arranged in the same shape or in different shapes.
8. A silicon carbide power MOSFET device of enhanced reliability, the silicon carbide power MOSFET device being a vertical device comprising a substrate, a silicon carbide region located above the substrate, a source region located within the silicon carbide region, and a body region located within the source region, the silicon carbide power MOSFET device comprising: a plurality of enhanced reliability cells and a plurality of conventional silicon carbide MOSFET cells arranged in the silicon carbide power MOSFET device in an octagonal or quadrilateral shape at the surface of the silicon carbide region, wherein the adjacent body regions of the conventional silicon carbide MOSFET cells comprise independent JFET regions, the source regions of the conventional silicon carbide MOSFET cells are located on both sides of the JFET regions, and the adjacent body regions in the source regions are connected into a whole.
9. The silicon carbide power MOSFET device of claim 8, wherein the source regions are quadrilateral in shape with gaps between octagons.
10. The silicon carbide power MOSFET device of claim 8, wherein the body connection locations of the enhanced reliability cells are located at corners of an octagon or a quadrilateral, and the JFET region is located between the nearest two sides of adjacent octagons or between the nearest two sides of adjacent octagons and quadrigons.
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| JP2006165013A (en) * | 2004-12-02 | 2006-06-22 | Nissan Motor Co Ltd | Semiconductor device and its manufacturing method |
| WO2017205346A1 (en) * | 2016-05-23 | 2017-11-30 | General Electric Company | Electric field shielding in silicon carbide metal-oxide-semiconductor (mos) device cells using body region extensions |
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| US9209262B2 (en) * | 2012-12-27 | 2015-12-08 | Panasonic Intellectual Property Management Co., Ltd. | Silicon carbide semiconductor device and method for manufacturing same |
| US10453923B2 (en) * | 2016-03-16 | 2019-10-22 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device |
| JP6593294B2 (en) * | 2016-09-28 | 2019-10-23 | トヨタ自動車株式会社 | Semiconductor device |
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Effective date of registration: 20231023 Address after: S103-3, Building 6, Phase 5, Information Port, No. 733 Jianshe Third Road, Ningwei Street, Xiaoshan District, Hangzhou City, Zhejiang Province, 311200 Patentee after: Hangzhou Xinzhu Semiconductor Co.,Ltd. Address before: No. 733, Jianshe 3rd road, Xiaoshan District, Hangzhou, Zhejiang 311200 Patentee before: Hangzhou International Science and technology innovation center of Zhejiang University |