CN114400258A - Planar power MOSFET device integrated with junction barrier Schottky diode - Google Patents
Planar power MOSFET device integrated with junction barrier Schottky diode Download PDFInfo
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- CN114400258A CN114400258A CN202210048047.XA CN202210048047A CN114400258A CN 114400258 A CN114400258 A CN 114400258A CN 202210048047 A CN202210048047 A CN 202210048047A CN 114400258 A CN114400258 A CN 114400258A
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- 230000004888 barrier function Effects 0.000 title claims abstract description 66
- 230000005669 field effect Effects 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 31
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 21
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 18
- 150000002500 ions Chemical class 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 230000000694 effects Effects 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
Abstract
The application discloses a planar power MOSFET device integrated with a junction barrier Schottky diode, which is used for solving the technical problem that the existing junction barrier Schottky cells and the existing MOSFET cells conflict when occupying the active region part of the device together. The device comprises: the epitaxial layer and a plurality of unit cells which are distributed on the first side surface of the epitaxial layer and have the same shape and structure; each unit cell at least comprises a well region, a source electrode region, a high-doped P-type region and a junction barrier Schottky region comprising a preset number of high-doped P-type regions; a Junction Field Effect Transistor (JFET) area is formed between the well areas; a first PN junction is formed between the well region and the epitaxial layer, and a second PN junction is formed between the well region and the source electrode region; forming a third PN junction by the preset number of highly doped P-type regions in the junction barrier Schottky region and the epitaxial layer; the value ranges of the distances between the JFET region and the highly doped P-type region are all in the same preset interval. The device solves the problem that the junction barrier Schottky cell and the MOSFET cell conflict when occupying the active region part of the device together.
Description
Technical Field
The application relates to the technical field of power semiconductor manufacturing, in particular to a planar power MOSFET device integrated with a junction barrier Schottky diode.
Background
Basal Plane Dislocations (BPD) exist in the silicon carbide crystal, and can be converted into Stacking Faults (SF) under certain conditions. When the body diode in a silicon carbide power MOSFET device is turned on, under bipolar operation, Stacking Faults (SF) continue to expand due to electron-hole recombination, resulting in bipolar degradation. This phenomenon increases the on-state voltage resistance of the silicon carbide power MOSFET, increases the leakage current in the blocking mode, increases the on-state voltage drop of the body diode, and thus decreases the reliability of the device.
In practical circuit applications, designers typically use external anti-parallel schottky diodes to suppress the body diode in power MOSFET devices in order to avoid bipolar degradation. However, for cost reasons, junction barrier schottky diodes can be embedded in each cell unit of a power MOSFET device, while the entire device shares the same termination structure, thus reducing the overall chip size.
However, for a silicon carbide planar power MOSFET device with a junction barrier schottky diode integrated inside the cells, there is a conflict relationship between the junction barrier schottky cells and the MOSFET cells occupying the active area portion of the device together. Therefore, how to solve the problem that the existing junction barrier schottky cell and the MOSFET cell conflict when occupying the active region part of the device together is urgent to be solved.
Disclosure of Invention
The embodiment of the application provides a planar power MOSFET device integrated with a junction barrier Schottky diode, which is used for solving the technical problem that the existing junction barrier Schottky cell and the existing MOSFET cell conflict when occupying the active region part of the device together.
The embodiment of the application provides an integrated junction barrier schottky diode's planar power MOSFET device, its characterized in that, the device includes: the epitaxial layer and a plurality of unit cells which are distributed on the first side surface of the epitaxial layer and have the same shape and structure; wherein the epitaxial layer is an N-type region; each unit cell at least comprises a well region, a source electrode region, a high-doped P-type region and a junction barrier Schottky region comprising a preset number of high-doped P-type regions; wherein: the well region is a P-type region, and the source region is an N-type region; the well region is contacted with the outermost layer of the high-doped P-type region; a Junction Field Effect Transistor (JFET) area is formed between the adjacent well areas; forming a first PN junction between the well region and the epitaxial layer; a second PN junction is formed between the well region and the source electrode region; forming a third PN junction by the preset number of highly doped P-type regions in the junction barrier Schottky region and the epitaxial layer; the value range of the width of the JFET area and the value range of the distance between the highly doped P-type areas are in the same preset interval.
The planar power MOSFET device of the integrated junction barrier Schottky diode provided by the embodiment of the application not only solves the problem that the existing junction barrier Schottky cell and the existing MOSFET cell conflict when occupying the active area part of the device together, but also ensures that the junction barrier Schottky diode has higher current conduction capability on the premise of smaller conduction loss of the MOSFET device through the special design of the fusion of the junction barrier Schottky cell and the MOSFET cell.
In one implementation of the present application, the device further comprises: an ohmic contact metal; the ohmic contact metal covers the surface of the outermost layer of the high-doped P-type region and part of the source electrode region; a first ohmic contact is formed between the ohmic contact metal and the outermost layer of the highly doped P-type region; forming a second ohmic contact between the ohmic contact metal and the source region; the first ohmic contact and the second ohmic contact are interconnected to suppress a parasitic bipolar transistor effect within the MOSFET device.
In one implementation of the present application, the device further comprises: a Schottky contact metal; the Schottky contact metal covers the surfaces of the junction barrier Schottky regions with the preset number; a Schottky contact is formed between the Schottky contact metal and the Schottky region.
In one implementation of the present application, the device further comprises: insulating the grid oxide layer and the grid conductive polysilicon; the insulated gate oxide layer covers the JFET area and the well area, and the boundary of the insulated gate oxide layer is positioned on the source electrode area; the grid conductive polysilicon covers the insulated grid oxide layer, and the width of the grid conductive polysilicon is less than or equal to that of the insulated grid oxide layer.
In one implementation of the present application, the device further comprises: an insulating dielectric layer; the insulating medium layer covers the insulating grid oxide layer and the grid conductive polysilicon.
In one implementation of the present application, the device further comprises: a source electrode; the source electrode is contacted with the ohmic contact metal and the Schottky contact metal; an insulating dielectric layer separates the gate conductive polysilicon from the source metal.
In one implementation of the present application, the device further comprises: a silicon carbide substrate, a drain electrode; the first side surface of the silicon carbide substrate is in contact with the second side surface of the epitaxial layer; wherein the silicon carbide substrate is an N-type region; the drain electrode covers the second side surface of the silicon carbide substrate.
In one implementation of the present application, the silicon carbide substrate has an ion doping concentration greater than the ion doping concentration of the epitaxial layer; the ion doping concentration in the distance between the JFET area and the high-doping P-type area is larger than or equal to that of the epitaxial layer.
In an implementation manner of the application, the preset interval is 0.8 um-5 um, and the range of the preset number is 1-10.
In one implementation of the present application, the shape of the unit cell is a circle or a regular polygon.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a cross-sectional view of an active region of a planar power MOSFET device integrated with a junction barrier schottky diode according to an embodiment of the present application;
fig. 2 is a schematic diagram of a regular hexagonal cell structure according to an embodiment of the present disclosure;
fig. 3 is a schematic three-dimensional perspective view of a regular hexagonal cell structure according to an embodiment of the present disclosure;
fig. 4 is another cross-sectional view of an active region of a planar power MOSFET device with an integrated junction barrier schottky according to an embodiment of the present application;
fig. 5 is a schematic diagram of a circular cell structure according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a regular quadrilateral cell structure according to an embodiment of the present application;
fig. 7 is a schematic diagram of another regular quadrilateral cell structure according to an embodiment of the present application.
Description of reference numerals:
a planar power MOSFET device active region 10 integrated with a junction barrier Schottky diode; a silicon carbide substrate 101; an epitaxial layer 102; a well region 103; a source region 104; a highly doped P-type region 105; an insulated gate oxide layer 106; a gate conductive polysilicon 107; an insulating dielectric layer 108; an ohmic contact metal 109; a schottky contact metal 110; a source electrode 111; a drain electrode 112; a JFET region 113; a junction barrier schottky region 114; a first PN junction 115; a second PN junction 116; a third PN junction 118; a second highly doped P-type region 117.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a planar power MOSFET device integrated with a junction barrier Schottky diode, which is used for solving the technical problem that the existing junction barrier Schottky cells and MOSFET cells conflict when occupying the active region part of the device together
The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a cross-sectional view of an active region of a planar power MOSFET device integrated with a junction barrier schottky diode according to an embodiment of the present application. As shown in fig. 1, a planar power MOSFET device 10 incorporating a junction barrier schottky diode includes an epitaxial layer 102; wherein, the epitaxial layer is an N-type region. In addition, as shown in fig. 1, a plurality of unit cells having the same shape and structure are distributed on the first side surface of the epitaxial layer.
It should be noted that the resistance of the planar power MOSFET device is composed of the following components: source resistance, channel resistance, JFET resistance, drift layer resistance, substrate resistance, contact resistance, etc. The ratio of the channel resistance to the JFET resistance is high, and the channel resistance and the JFET resistance are influenced by the structural parameters of the MOSFET unit cells. The main parameters affecting the MOSFET specific on-resistance are the total channel width and the total area of the JFET region, which correspondingly affect the channel resistance and the JFET resistance, respectively. Due to the MOSFET device designed by the round and regular polygonal unit cells, higher channel width and total area of a Junction Field Effect Transistor (JFET) area can be realized, and further, the specific on-resistance is lower. Therefore, the cell shape in the embodiment of the present application is designed in a regular polygon or a circle.
Fig. 2 is a schematic structural diagram of a regular hexagonal cell provided in an embodiment of the present application, as shown in fig. 2, each cell includes: well 103, source region 104, two highly doped P-type regions 105 and two junction barrier schottky regions 114.
As shown in fig. 2, one of the highly doped P-type regions 105 is included in the junction barrier schottky region 114, and the well 103, the source 104, the highly doped P-type region 105 and the junction barrier schottky region 114 are shaped as concentric regular hexagons. Fig. 3 is a three-dimensional schematic view of a regular hexagonal cell structure according to an embodiment of the present disclosure, and it can be understood that the three-dimensional schematic view of the regular hexagonal cell structure shown in fig. 3 is a corresponding schematic view of the regular hexagonal cell structure shown in fig. 2.
In one embodiment of the present application, a predetermined number of highly doped P-type regions may be included in the junction barrier schottky region 114, the predetermined number being in a range of 1 to 10.
Further, a Junction Field Effect Transistor (JFET) region 113 is formed between adjacent cells.
It should be noted that the cross-sectional view corresponding to the dashed line AA' in fig. 2 is a cross-sectional view of the active region of the planar power MOSFET device of the integrated junction barrier schottky diode shown in fig. 1; the cross-sectional view corresponding to the dashed line BB' in fig. 2 is another cross-sectional view of the active region of the planar power MOSFET device with the integrated junction barrier schottky diode shown in fig. 4. It will be appreciated that for the two highly doped P-type regions 105 of fig. 2, which are separately named for distinction in fig. 1, in contact with the well region 103 is the highly doped P-type region 105 and within the junction barrier schottky region 114 is the second highly doped P-type region 117.
Further, as shown in fig. 1, the lower half portion of the highly doped P-type region 105 is in contact with the well region 103, the source region 104 surrounds the highly doped P-type region 105, a first PN junction 115 is formed between the well region 103 and the epitaxial layer 102, and a second PN junction 116 is formed between the well region 103 and the source region 104; a third PN junction 118 is formed between the second highly doped P-type region 117 in the junction barrier schottky region 114 and the epitaxial layer 102. In addition, it is understood that the source region 104 is surrounded by the well 103 and the highly doped P-type region 105. .
The well 103, the highly doped P-type region 105, and the second highly doped P-type region 117 are all P-type regions, and the source region 104 is an N-type region.
In one embodiment of the present application, the ion doping concentration range of the well region 103 is: 5E15cm-3～5E18cm-3(ii) a The ion doping concentration range of the source region 104 is: 1E18cm-3～1E22cm-3(ii) a The ion doping concentration range of the highly doped P-type region 105 is: 1E18cm-3～1E22cm-3。
It should be noted that, due to the design of the width n and the ion implantation concentration of the JFET region 113, it is required to ensure that the MOSFET has a smaller on-state voltage drop, and in the blocking mode, an effective electric field shielding effect can be achieved between adjacent well regions, so as to ensure the reliability of the device. Similarly, the distance s between the highly doped P-type regions 105 and the ion implantation concentration in the distance s need to ensure that the schottky diode has sufficient current conduction capability, and in the blocking mode, an effective electric field shielding effect can be achieved between adjacent well regions, thereby ensuring the reliability of the device. Therefore, in the embodiment of the present application, the value range of the width n of the JFET region and the value range of the distance s between the highly doped P-type region 105 and the second highly doped P-type region 117 are both within the preset interval; the ion doping concentration of the JFET region 113 and the ion doping concentration within the gap between the highly doped P-type region 105 and the second highly doped P-type region 117 are all greater than or equal to the ion doping concentration of the epitaxial layer 102. The design can make the MOSFET device have smaller conduction voltage drop, and under the blocking mode, the effective electric field shielding effect can be achieved between the adjacent well regions. It can be understood that, in the case that the preset number of the second highly doped P-type regions 117 is greater than 1, the range of the distance s between adjacent second highly doped P-type regions 117 is also within the preset interval, and the ion doping concentration within the distance s between adjacent second highly doped P-type regions 117 is also greater than or equal to the ion doping concentration of the epitaxial layer 102.
In one embodiment of the present application, the preset interval is 0.8um to 5 um; the ion doping concentration range within the gap between the JFET region 113 and the highly doped P-type region is: 1E15cm-3～5E17cm-3。
In one embodiment of the present application, the planar power MOSFET device 10 of integrated junction barrier schottky diode further comprises: a silicon carbide substrate 101 and a drain electrode 112.
As shown in fig. 1, a first side surface of a silicon carbide substrate 101 is in contact with a second side surface of an epitaxial layer 102; wherein, the silicon carbide substrate 101 is an N-type region; the drain electrode 112 covers the second side surface of the silicon carbide substrate 101; the silicon carbide substrate 101 has an ion doping concentration greater than that of the epitaxial layer 102.
In one embodiment of the present application, the ion doping concentration range of the silicon carbide substrate 101 is: 1E18cm-3～1E20cm-3The ion doping concentration range of the epitaxial layer 102 is: 1E14cm-3～5E16cm-3。
In one embodiment of the present application, the planar power MOSFET device 10 of integrated junction barrier schottky diode further comprises: the ohmic contact metal 109 and the schottky contact metal 110.
As shown in fig. 1, the ohmic contact metal 109 covers the highly doped P-type region 105 and a portion of the surface of the source region 104, and a first ohmic contact is formed between the ohmic contact metal 109 and the highly doped P-type region 105; in addition, in order to suppress the parasitic bipolar transistor effect inside the MOSFET device 10, the ohmic contact metal 109 also forms a second ohmic contact with the source region 104; wherein the first ohmic contact and the second ohmic contact are formed to be connected to each other. The schottky contact metal 110 covers the surface of the junction barrier schottky region 114 to form schottky contact with the schottky region; as shown in fig. 1, it is understood that in the junction barrier schottky region 114, other portions except for a predetermined number of highly doped P-type regions are schottky regions.
In one embodiment of the present application, the planar power MOSFET device 10 of integrated junction barrier schottky diode further comprises: insulating the gate oxide layer 106 from the gate conductive polysilicon 107.
As shown in fig. 1, the insulated gate oxide layer 106 covers the JFET region 113 and the well region 104, and the boundary of the insulated gate oxide layer 106 is located on the source region 104; the gate conductive polysilicon 107 covers the insulated gate oxide layer 106, and the width of the gate conductive polysilicon 107 is less than or equal to the width of the insulated gate oxide layer 106.
In one embodiment of the present application, the planar power MOSFET device 10 of integrated junction barrier schottky diode further comprises: an insulating dielectric layer 108.
As shown in fig. 1, an insulating dielectric layer 108 covers the insulated gate oxide layer 106 and the gate conductive polysilicon 107.
In one embodiment of the present application, the planar power MOSFET device 10 of integrated junction barrier schottky diode further comprises: and a source electrode 111.
As shown in fig. 1, the source electrode 111 is in contact with the ohmic contact metal 109 and the schottky contact metal 110; in addition, an insulating dielectric layer 108 separates the gate conductive polysilicon 107 from the source metal 111.
Fig. 5 is a schematic diagram of a circular unit cell structure according to an embodiment of the present disclosure. As shown in fig. 5, the predetermined number is two, and the well 103, the source region 104, the two highly doped P-type regions 105 and the two junction barrier schottky regions 114 are shaped as concentric rings. The cross-sectional view corresponding to the dashed line AA' in fig. 5 is a cross-sectional view of the active region of the planar power MOSFET device of the integrated junction barrier schottky diode shown in fig. 1; the cross-sectional view corresponding to the dashed line BB' in fig. 5 is another cross-sectional view of the active region of the planar power MOSFET device with the integrated junction barrier schottky diode shown in fig. 4.
Fig. 6 is a schematic diagram of a regular quadrilateral cell structure according to an embodiment of the present application. As shown in fig. 6, the predetermined number is two, and the well 103, the source region 104, the two highly doped P-type regions 105 and the two junction barrier schottky regions 114 are in a concentric regular quadrilateral structure. In addition, the regular quadrilateral cell arrangement shown in fig. 6 is a staggered arrangement of regular quadrilateral cells in two adjacent rows or two adjacent columns. The cross-sectional view corresponding to the dashed line AA' in fig. 6 is a cross-sectional view of the active region of the planar power MOSFET device of the integrated junction barrier schottky diode shown in fig. 1; the cross-sectional view corresponding to the dashed line BB' in fig. 6 is another cross-sectional view of the active region of the planar power MOSFET device with the integrated junction barrier schottky diode shown in fig. 4.
In an embodiment of the present application, the regular quadrilateral cells may have a plurality of different arrangement modes, and fig. 7 is a schematic view of another regular quadrilateral cell structure provided in the embodiment of the present application, as shown in fig. 7, the predetermined number is two, and the well region 103, the source region 104, the two highly doped P-type regions 105, and the two junction barrier schottky regions 114 are shaped as concentric regular quadrilateral structures. In addition, the regular square cell arrangement shown in fig. 7 is such that the regular square cells in each row and each column are aligned. The cross-sectional view corresponding to the dashed line AA' in fig. 7 is a cross-sectional view of the active region of the planar power MOSFET device of the integrated junction barrier schottky diode shown in fig. 1; the cross-sectional view corresponding to the dashed line BB' in fig. 7 is another cross-sectional view of the active region of the planar power MOSFET device with the integrated junction barrier schottky shown in fig. 4.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A planar power MOSFET device incorporating a junction barrier schottky diode, the device comprising:
the epitaxial layer and a plurality of unit cells which are distributed on the first side surface of the epitaxial layer and have the same shape and structure; wherein the epitaxial layer is an N-type region;
each unit cell at least comprises a well region, a source electrode region, a high-doped P-type region and a junction barrier Schottky region comprising a preset number of high-doped P-type regions; wherein: the well region is a P-type region, and the source region is an N-type region; the well region is in contact with the outermost layer of the high-doped P-type region;
a Junction Field Effect Transistor (JFET) area is formed between the adjacent well areas;
forming a first PN junction between the well region and the epitaxial layer;
a second PN junction is formed between the well region and the source region;
a preset number of highly doped P-type regions in the junction barrier Schottky region and the epitaxial layer form a third PN junction;
the value range of the width of the JFET region and the value range of the distance between the highly doped P-type regions are in the same preset interval.
2. The planar power MOSFET device of integrated junction barrier schottky diode of claim 1, further comprising: an ohmic contact metal;
the ohmic contact metal covers the surface of the outermost layer of the highly doped P-type region and part of the source electrode region;
a first ohmic contact is formed between the ohmic contact metal and the outermost layer of the highly doped P-type region;
forming a second ohmic contact between the ohmic contact metal and the source region;
the first ohmic contact and the second ohmic contact are interconnected to suppress a parasitic bipolar transistor effect inside the MOSFET device.
3. The planar power MOSFET device of integrated junction barrier schottky diode of claim 2, further comprising: a Schottky contact metal;
the Schottky contact metal covers the surface of the junction barrier Schottky region;
and a Schottky contact is formed between the Schottky contact metal and the Schottky region.
4. The planar power MOSFET device of integrated junction barrier schottky diode of claim 1, further comprising: insulating the grid oxide layer and the grid conductive polysilicon;
the insulated gate oxide layer covers the JFET area and the well area, and the boundary of the insulated gate oxide layer is positioned on the source electrode area;
the grid conductive polysilicon covers the insulated grid oxide layer, and the width of the grid conductive polysilicon is smaller than or equal to that of the insulated grid oxide layer.
5. The planar power MOSFET device of integrated junction barrier schottky diode of claim 4, further comprising: an insulating dielectric layer;
the insulating medium layer covers the insulating grid oxide layer and the grid conductive polysilicon.
6. The planar power MOSFET device of integrated junction barrier schottky diode of claim 5, further comprising: a source electrode;
the source electrode is contacted with the ohmic contact metal and the Schottky contact metal;
the insulating dielectric layer separates the gate conductive polysilicon from the source metal.
7. The planar power MOSFET device of integrated junction barrier schottky diode of claim 1, further comprising: a silicon carbide substrate, a drain electrode;
the first side surface of the silicon carbide substrate is in contact with the second side surface of the epitaxial layer; wherein the silicon carbide substrate is an N-type region;
the drain electrode covers the second side surface of the silicon carbide substrate.
8. The planar power MOSFET device of integrated junction barrier Schottky diode of claim 7,
the ion doping concentration of the silicon carbide substrate is greater than that of the epitaxial layer;
and the ion doping concentration in the distance between the JFET region and the high-doping P-type region is greater than or equal to that of the epitaxial layer.
9. The planar power MOSFET device of claim 1, wherein the predetermined interval is 0.8um to 5um, and the predetermined number is 1 to 10.
10. The planar power MOSFET device of integrated junction barrier schottky diode of claim 1, wherein the shape of the unit cell is a circle or a regular polygon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210048047.XA CN114400258A (en) | 2022-01-17 | 2022-01-17 | Planar power MOSFET device integrated with junction barrier Schottky diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210048047.XA CN114400258A (en) | 2022-01-17 | 2022-01-17 | Planar power MOSFET device integrated with junction barrier Schottky diode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116682735A (en) * | 2023-08-04 | 2023-09-01 | 深圳基本半导体有限公司 | Preparation method of MOS structure self-alignment process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116682735A (en) * | 2023-08-04 | 2023-09-01 | 深圳基本半导体有限公司 | Preparation method of MOS structure self-alignment process |
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