CN111640783B - Composite Pin Schottky diode with various cell designs - Google Patents
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- 238000013461 design Methods 0.000 title claims abstract description 22
- 239000002131 composite material Substances 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 2
- 238000013021 overheating Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
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- 230000015556 catabolic process Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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- 238000012937 correction Methods 0.000 description 1
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- 239000012535 impurity Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Abstract
The invention relates to a composite Pin Schottky diode designed by various unit cells, which comprises: a plurality of unit cells are arranged in the second conductive region; the first unit cell in the plurality of unit cells comprises a first area and a second area, the first area is arranged around the second area, the second unit cell in the plurality of unit cells comprises a third area, the third unit cell in the plurality of unit cells comprises a fourth area, a first PN junction is formed between the first area and/or the third area and the epitaxial layer, a second PN junction is formed between the second area and the epitaxial layer, and a third PN junction is formed between the fourth area and the epitaxial layer; the width of the third PN junction is larger than the widths of the first PN junction and the second PN junction, and the third PN junction is started before the first PN junction and the second PN junction under the condition of surge large current. Through the design of PN junctions with different sizes, the area of an active region of a device can be more efficiently utilized under the condition that the performance of a normal current conduction mode of the Schottky diode is kept or not influenced as much as possible, so that large surge current is uniformly dispersed on the surface of the device, the damage to the device caused by local overheating is effectively reduced, and the stability of the device is improved.
Description
Technical Field
The invention relates to the technical field of power diodes, in particular to a composite Pin Schottky diode with various cell designs.
Background
The power device comprises a power diode and a power switch tube, and the power diode has two working modes in circuit application: an on mode and a blocking mode. For the conduction working mode, except the normal current working condition, the abnormal working condition of accidental surge large current also exists. Under the abnormal working condition of surge current, the phenomenon of instantaneous energy overshoot and chip temperature rise can happen to the diode, and the device is caused to fail.
Generally, power electronics will be subjected to high current stresses under surges caused by circuit faults or lightning. In the event of surge, the large current multiplied by the voltage drop of the device will form a transient overshoot of energy, which flows into the device in a relatively short time, resulting in a rapid rise in the junction temperature of the device, possibly causing a reduction in the reliability of the device, and even performance degradation and failure.
The current commercial silicon carbide diode devices generally have low surge current resistance and cannot meet the requirements of special applications, for example, in the application of a Power Factor Correction (PFC) in a high-voltage distribution system, a surge large current surge may occur at the moment of circuit opening and/or at the moment of circuit interruption. When surge surges occur, the diodes dissipate a large amount of power and energy, and if the device structure is improperly designed, the device has poor surge current resistance, and the device may fail catastrophically due to overheating.
Disclosure of Invention
The invention provides a composite Pin Schottky diode with various cell designs, and aims to solve the following technical problems to a certain extent: the electronic devices such as the diode and the like cannot bear the surge large current impact, and the reliability is low.
In one aspect, an embodiment of the present application provides a composite PiN schottky diode with multiple cell designs, where the diode includes: the PN junction comprises a PN junction, a first conductive area and a second conductive area, wherein the first conductive area and the second conductive area form the PN junction, the second conductive area is positioned on the surface of the first conductive area, the first conductive area comprises an epitaxial layer, and a plurality of cells are distributed in the second conductive area; wherein the content of the first and second substances,
a first cell of the plurality of cells comprises a first area and a second area, the first area is arranged around the second area, the first area is in a ring-shaped octagon shape, the second area is in a regular polygon shape or a circular shape, and the center of the first area is the same as that of the second area; a second cell of the plurality of cells includes a third region having an annular quadrilateral shape; a third cell of the plurality of cells comprises a fourth region, the fourth region being octagonal;
a first PN junction is formed between the first region and/or the third region and the epitaxial layer, a second PN junction is formed between the second region and the epitaxial layer, and a third PN junction is formed between the fourth region and the epitaxial layer;
the width of the third PN junction is larger than the widths of the first PN junction and the second PN junction, so that the third PN junction is opened before the first PN junction and the second PN junction under the condition of surge current.
In one example, the width of the second PN junction is greater than the width of the first PN junction such that the second PN junction turns on before the first PN junction under inrush current conditions.
In one example, the first cell and the second cell are disposed around the third cell.
In one example, a plurality of the first unit cells and/or the second unit cells are disposed between two adjacent third unit cells.
In one example, n first cells are disposed between two third cells, and where n may be 1-1000000.
In one example, adjacent ones of the first, third and fourth regions are connected to each other.
In one example, the first unit cell, the second unit cell and the third unit cell have the same depth, and the depth is the depth of the second conductive region formed on the surface of the epitaxial layer.
In one example, further comprising: a substrate, wherein,
the substrate is positioned on the surface of one side, away from the second conductive area, of the epitaxial layer;
the doping concentration of the substrate is higher than that of the epitaxial layer.
In one example, further comprising: a schottky contact metal, wherein,
the Schottky contact metal covers the surface of the epitaxial layer, and Schottky contact is formed between the Schottky contact metal and the epitaxial layer.
In one example, further comprising: the ohmic contact metal and the cathode electrode form a first ohmic contact with the second conductive region;
the cathode electrode is arranged on one side of the substrate, which is far away from the epitaxial layer, and a second ohmic contact is formed between the substrate and the cathode electrode.
According to the diode device provided by the embodiment of the application, when surge large current passes through, PN junctions in multiple unit cells are turned on step by step under the condition that the current exceeds different threshold values. Through the design, the area of the active region can be more efficiently utilized, and the current is uniformly dispersed on the surface of the device, so that the damage of the device caused by local overheating is effectively reduced, and the stability of the device is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic cross-sectional view of a diode according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a cell arrangement of a second conductive region according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view taken along line AA' of FIG. 2;
FIG. 4 is a schematic diagram A illustrating a cell arrangement of a second conductive region according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view taken along line EE' of FIG. 4;
FIG. 6 is a schematic diagram B illustrating a cell layout of a second conductive region according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a cell layout design of a second conductive region according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a cell layout design D of a second conductive region according to an embodiment of the invention;
FIG. 9 is a schematic diagram E illustrating a cell layout of a second conductive region according to an embodiment of the present invention;
fig. 10 is a schematic sectional view taken along line FF' in fig. 9.
Detailed Description
In order to more clearly explain the overall concept of the present application, the following detailed description is given by way of example in conjunction with the accompanying drawings.
The material of the semiconductor plays a decisive role in the performance of the semiconductor, and the silicon carbide semiconductor material has the forbidden bandwidth about three times that of the silicon material, higher critical breakdown electric field intensity, higher thermal conductivity, lower intrinsic carrier concentration and higher saturation drift velocity, which make the silicon carbide an ideal material for high-voltage, high-temperature and high-power devices. Two technical routes exist for commercial devices based on silicon carbide semiconductor material power diodes, namely junction barrier schottky diode structures and composite PiN schottky diode structures.
The junction barrier schottky diode has lower reverse leakage current and stronger blocking characteristics than a pure schottky diode by alternately arranging narrow P + regions in an N-drift layer. The composite Pin Schottky diode structure is an improved structure based on a junction barrier Schottky diode, the design of a narrow P + region is reserved, a wider P + region is added in an active region, PN junctions formed by the wide P + regions can be opened under the condition that a device is impacted by surge current, and carriers are injected into a drift layer, so that the device has lower resistivity and higher current conduction capability under the condition of large surge current impact. Therefore, the composite PiN schottky diode has higher surge current resistance than the junction barrier schottky diode.
The surge current resistance of the device is a key indicator describing its robustness in extreme current surge situations. Devices with superior inrush current resistance can effectively dissipate this energy without degradation or failure, thereby providing higher safety margins for the electrical equipment, improving the reliability and life of the electrical equipment.
The structural design of the device is described in detail below.
Fig. 1 is a schematic cross-sectional view of a diode of the present invention, and as shown in fig. 1, a composite PiN schottky diode 10 mainly includes: a silicon carbide substrate 12 containing impurities and having a first conductivity type; an epitaxial layer 13 of the first conductivity type formed on the silicon carbide substrate, the doping concentration of the epitaxial layer being lower than the doping concentration of the substrate; a plurality of second conductive regions 14 having a different conductivity type from the first conductive regions, formed on the surface of the epitaxial layer; forming a first ohmic contact 18 over the second conductive type region 14; a schottky contact metal 19 is located on top of the entire epitaxial layer 13, forming a schottky junction 16; a second ohmic contact 17 is formed between the back surface of substrate 12 and cathode electrode 11.
In the embodiment of the invention, the first conductive region in the composite Pin Schottky diode structure is an N-type region, the second conductive region is a P + region, and a PN junction 15 formed by the P + region and the N-type region can be opened under the condition of large current to form a working mode that the PN junction 15 is connected with the Schottky junction 16 in parallel, so that higher surge current resistance is provided for the device. Therefore, the shape, size and arrangement of P + greatly affect the electrical characteristics of the composite PiN schottky diode under surge current operation.
It is understood that, in other embodiments of the present invention, the first conductive region in the composite PiN schottky diode structure may also be a P region, and the second conductive region may also be an N region, which is not particularly limited in this application.
Structural parameters such as the area width, the interval and the like of the second conductive area are reasonably designed, the starting voltage of the PN junction can be reduced, the starting voltage in the embodiment of the application refers to the voltage drop between the anode and the cathode of the diode corresponding to the PN junction when the PN junction is started, the power loss and the increase of the junction temperature of the device under the condition of surge current are reduced, and therefore the surge current resistance of the device is improved. The structural design of the second conductive region not only affects the surge current resistance of the device, but also affects the conduction voltage drop of the device under the normal current working condition, so that the conduction performance of the device is changed. This is because, under normal current (current less than the maximum steady state operating current specified in the manufacturer's data sheet), only the schottky junction is turned on because the schottky barrier height is much lower than the PN junction built-in potential. If the area of the second conductive region is larger, the area of the active region is excessively occupied, and the corresponding Schottky junction area is reduced, so that the conduction voltage drop of the device in a normal current conduction mode is increased, and the conduction performance of the device is reduced. On the other hand, when the device is impacted by abnormal surge current, the PN junction is more easily opened due to the wider structure design of the second conductive region, once the PN junction starts to conduct current, current carriers are injected into the drift layer, the resistance and the conduction voltage drop of the device are reduced, and therefore the surge current resistance of the device is enhanced. It can be seen that the composite PiN schottky diode has a trade-off relationship between normal current conduction performance and surge current resistance.
Fig. 2 is a layout diagram of a second conductive region, according to an embodiment of the present invention, as shown in fig. 2, the area occupied by the conductive current in the active region of the circular unit cell is smaller under a normal operating current.
In order to increase the ratio of the active area, a new cell design is provided in the embodiment of the present invention, and fig. 3 is a schematic diagram a of the arrangement of the cells in the second conductive region in the embodiment of the present invention.
As shown in fig. 4, the embodiment of the present invention provides two structures of unit cells, namely, a first unit cell in an octagonal shape and a second unit cell in a quadrilateral shape, wherein the first unit cell includes a first region and a second region, the first region is disposed around the second region, adjacent second regions are connected together by edges, the first region is in an octagonal shape, and the second region is in an arbitrary shape, and may be a circular shape or a regular polygon, such as a quadrilateral shape or an octagonal shape; the second cell comprises a third area which is an annular quadrangle, and the adjacent first area and the third area are mutually connected.
Through calculation, when the cell designs of fig. 2 and fig. 4 are densely paved with active area areas of the same size, the active area occupation ratio of the schottky diode is 50.49% and 52.98%, respectively. By the cell design, the effective area of the Schottky diode in forward conduction can be increased.
Further, fig. 3 is a schematic cross-sectional view taken along line AA' in fig. 2 according to an embodiment of the present invention, where 14 in fig. 3 denotes a second conductive region, P 1 And P 2 Respectively, indicate their width, 14A indicates a value of P 1 Second conductive region of width, 14B denotes having P 2 Second conductive region of width, 20 for schottky channel region, 15A for P 1 PN junction of width, 15B denotes with P 2 A wide PN junction. When the diode conducts current in forward direction, the current flows fromThe anode electrode of the diode flows into the drift region through the schottky junction, through the substrate, and out the cathode electrode. And first through the channel region formed between the second conductive regions before current enters the drift region. The current will, when passing through the channel region, create a potential difference across the PN junction formed between the drift region of the first conductive region and the second conductive region, which will be turned on when the potential difference exceeds the built-in potential of the PN junction.
Changing the width of the second conductive region will affect the conduction current threshold for triggering the PN junction to turn on, and the voltage drop between the anode and the cathode of the diode corresponding to the PN junction to turn on is called the turn-on voltage of the PN junction. The wider the width of the second conductive region, the lower the turn-on voltage of the PN junction. As shown in FIG. 3, the dotted lines BB ', CC' show the widths P 1 And P 2 Current path near the P + region. When the potential difference between BB 'and CC' reaches the built-in potential of the PN junction formed by the P + region and the drift layer, the PN junction is turned on. The potential difference of BB ', CC ' is equal to the current of the channel region multiplied by the resistance of the BB ', CC segments. As is apparent from fig. 3, when the P + interval distance is constant, i.e., the channel region width is constant, the magnitude of the resistance is mainly affected by the P + region width, and when the P + region width is larger, i.e., P 2 Greater than P 1 The greater its resistance, i.e. R CC' Greater than R BB' 。
FIG. 5 is a cross-sectional view taken along line EE' of FIG. 4 according to an embodiment of the present invention, as shown in FIG. 5, through a new cell structure design provided according to an embodiment of the present invention, still having P in the second conductive region 1 And P 2 Of the width of (a). Meanwhile, through the design of the embodiment of the invention, the effective area of the Schottky diode in forward conduction can be increased.
Thus, in either FIG. 3 or FIG. 5, when the current increases to the current threshold I that triggers the PN junction 15B to turn on 2 Then CC' will reach the built-in potential of the second PN junction with the width of P 2 The PN junction of (a) is first turned on. As the current continues to increase, the current threshold I for the first PN junction to open is exceeded 1 Then BB' also reaches the built-in potential of the first PN junction 15A, and is thus wideDegree P 1 The PN junction is also turned on.
Based on the above situation, the structure shown in fig. 4 is designed to continue to increase the third unit cells having the second conductive type regions with wider widths while keeping the second conductive region pitch unchanged. So that the third PN junction with wider width has I 2 Smaller threshold value of the switching current I 3 Therefore, the device is turned on under a lower voltage, and the surge current resistance of the device is enhanced.
Fig. 6 is a schematic diagram B illustrating a cell arrangement of a second conductive region according to an embodiment of the present invention, where as shown in fig. 6, 30 denotes a first cell and 40 denotes a second cell, a third cell 50 is further disposed in the second conductive region, the third cell includes a fourth region, the fourth region is octagonal, and adjacent first, third, and fourth regions are connected to each other. As shown in fig. 6, the fourth region is the entire region of the third cell 50. Designing the fourth region to form a PN junction with a width of P3 such that P 3 The PN junction of the width has a relatively I 2 Smaller threshold value of the switching current I 3 And the device is turned on under a lower voltage, so that the surge current resistance of the device is enhanced.
FIG. 7 is a schematic diagram of a cell design of a second conductive region according to an embodiment of the present invention; FIG. 8 is a schematic diagram of a cell design D of a second conductive region according to an embodiment of the present invention; FIG. 9 is a schematic diagram of a cell design E of a second conductive region according to an embodiment of the present invention; fig. 7-9 show different arrangement manners of the first unit cells and the second unit cells, respectively, and fig. 7 is based on fig. 6, and the arrangement number and density of the third unit cells are reduced, and two first unit cells are arranged between two adjacent third unit cells. In fig. 8, the number and density of the arrangement of the third unit cells are further reduced, and three first unit cells are disposed between two adjacent third unit cells. In fig. 9, the arrangement number density of the third unit cells is again reduced, and four first unit cells are disposed between two adjacent third unit cells. By analogy, n first cells may be arranged every two third cells, where n may be 1 to 1000000.
It can be understood that the schematic arrangement diagrams of the first cell, the second cell, and the third cell shown in fig. 6 to 9 are merely exemplary preferred technical solutions, and should not be a limitation to the embodiments of the present invention, and the embodiments of the present invention adopt a regular arrangement manner to realize the arrangement of the first cell, the second cell, and the third cell, and may also adopt other arrangement manners without regularity or complete disorder, which is not described herein again.
FIG. 10 is a schematic cross-sectional view taken along line DD' of FIG. 9, where P is shown in FIG. 9 3 Denotes the width of the P + region, 14C denotes a P + region 3 P + region of width, 15C denotes a region having P 3 A wide PN junction. As can be seen from the figure, P 3 Width greater than P 2 Width greater than P 1 Width, by adding a cell having a wider width P based on the arrangement of the cells shown in FIG. 4 3 So as to have P 3 The PN junction of the width has a relatively I 2 Smaller threshold value of the on-current I 3 Therefore, the device is turned on under lower voltage, and the surge current resistance of the device is enhanced.
The embodiments of the present invention are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment is described with emphasis on differences from other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement or the like made within the spirit and principle of the present application shall be included in the application.
Claims (10)
1. A composite Pin Schottky diode of multiple cell designs, comprising: the PN junction comprises a first conductive region and a second conductive region, wherein the first conductive region and the second conductive region of the PN junction are formed, the second conductive region is positioned on the surface of the first conductive region, the first conductive region comprises an epitaxial layer, and a plurality of cells are distributed in the second conductive region; wherein the content of the first and second substances,
a first cell of the plurality of cells comprises a first area and a second area, the first area is arranged around the second area, the first area is in a ring-shaped octagon shape, the second area is in a regular polygon shape or a circular shape, and the center of the first area is the same as that of the second area; a second cell of the plurality of cells includes a third region, the third region being an annular quadrilateral; a third cell of the plurality of cells comprises a fourth region, the fourth region being octagonal;
a part of the third region of the second unit cell is surrounded by four of the first regions connected to each other, and another part of the third region of the second unit cell is surrounded by three of the first regions and one of the fourth regions connected to each other, each of the fourth regions being surrounded by four of the first regions and four of the third regions alternately arranged and connected to each other;
a first PN junction is formed between the first region and/or the third region and the epitaxial layer, a second PN junction is formed between the second region and the epitaxial layer, and a third PN junction is formed between the fourth region and the epitaxial layer;
the width of the third PN junction is larger than the width of the first PN junction and the second PN junction, so that the third PN junction is opened before the first PN junction and the second PN junction under the condition of surge current.
2. The diode of claim 1, wherein the width of the second PN junction is greater than the width of the first PN junction such that the second PN junction turns on before the first PN junction in the event of an inrush current.
3. The diode of claim 1, wherein the first cell and the second cell are circumferentially disposed around the third cell.
4. The diode of claim 1, wherein a plurality of the first cells and/or the second cells are disposed between two adjacent third cells.
5. The diode of claim 1, wherein n of said first cells are disposed between two of said third cells, and wherein n is 1-1000000.
6. The diode of claim 1, wherein adjacent ones of the first, third and fourth regions are interconnected together.
7. The diode of claim 1, wherein the first, second and third cells have the same depth, and wherein the depth is the depth at which the second conductive region is formed on the surface of the epitaxial layer.
8. The diode of claim 1, further comprising: the substrate is positioned on the surface of one side, away from the second conductive region, of the epitaxial layer; the doping concentration of the substrate is higher than that of the epitaxial layer.
9. The diode of claim 1, further comprising: and the Schottky contact metal covers the surface of the epitaxial layer, and Schottky contact is formed between the Schottky contact metal and the epitaxial layer.
10. The diode of claim 8, further comprising: the ohmic contact metal and the cathode electrode form a first ohmic contact with the second conductive region; the cathode electrode is arranged on one side of the substrate, which is far away from the epitaxial layer, and a second ohmic contact is formed between the substrate and the cathode electrode.
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| CN107579121A (en) * | 2016-07-05 | 2018-01-12 | 现代自动车株式会社 | Schottky-barrier diode and its manufacture method |
| CN107845683A (en) * | 2016-09-21 | 2018-03-27 | 株式会社东芝 | Semiconductor device |
| CN110571281A (en) * | 2019-08-01 | 2019-12-13 | 山东天岳电子科技有限公司 | Hybrid Pin junction Schottky diode and manufacturing method thereof |
| WO2020026401A1 (en) * | 2018-08-02 | 2020-02-06 | 三菱電機株式会社 | Wide band gap semiconductor device and power conversion device |
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| TWI521718B (en) * | 2012-12-20 | 2016-02-11 | 財團法人工業技術研究院 | Integrated device including junction barrier schottky diode embedded in mosfet cell array |
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| CN107579121A (en) * | 2016-07-05 | 2018-01-12 | 现代自动车株式会社 | Schottky-barrier diode and its manufacture method |
| CN107845683A (en) * | 2016-09-21 | 2018-03-27 | 株式会社东芝 | Semiconductor device |
| WO2020026401A1 (en) * | 2018-08-02 | 2020-02-06 | 三菱電機株式会社 | Wide band gap semiconductor device and power conversion device |
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