JPH0677472A - Surge protective element - Google Patents
Surge protective elementInfo
- Publication number
- JPH0677472A JPH0677472A JP3335859A JP33585991A JPH0677472A JP H0677472 A JPH0677472 A JP H0677472A JP 3335859 A JP3335859 A JP 3335859A JP 33585991 A JP33585991 A JP 33585991A JP H0677472 A JPH0677472 A JP H0677472A
- Authority
- JP
- Japan
- Prior art keywords
- exposed
- base region
- region
- base
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001681 protective effect Effects 0.000 title abstract description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 9
- 239000002131 composite material Substances 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000007480 spreading Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- JCALBVZBIRXHMQ-UHFFFAOYSA-N [[hydroxy-(phosphonoamino)phosphoryl]amino]phosphonic acid Chemical compound OP(O)(=O)NP(O)(=O)NP(O)(O)=O JCALBVZBIRXHMQ-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は遮断性能とサージ動作性
能にすぐれた製造容易なサイリスタ型のサージ防護素子
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thyristor type surge protection element which has excellent breaking performance and surge operation performance and is easy to manufacture.
【０００２】[0002]
【従来の技術】図６（ａ）に示すＰＮＰＮＰ層からなる
基本構造をもち、図６（ｂ）に示す電流電圧特性（一方
向のみを示す）をもつ両方向のサイリスタ型サージ防護
素子は、小型安価であるなどから通信回路などの弱電回
路のサージ防護用としてよく使用されている。この防護
素子は基本動作回路を示す図７のように、被保護回路Ｈ
の両端間に接続して使用され、例えば図６（ｂ）に示す
サージ防護素子ＺのＶBOを越える電圧値をもつサージＳ
が線路に侵入したとき、直ちにオンして被保護回路Ｈの
保護を行うものである。この場合サージ防護素子Ｚはサ
ージ電流の通過後、電源電圧Ｅ0 により流される電流を
直ちに遮断して、サージ侵入前の状態に戻ることが求め
られる。そのためには公知のように防護素子Ｚの保持電
流ＩH が ＩH ＞Ｅ0 ／Ｒ ただし Ｒ：回路インピーダンス Ｅ0 ：電源電圧 の関係を満足することを要し、良好な遮断性能を得るた
めには保持電流ＩH が大であることが求められる。とこ
ろで保持電流ＩH は従来から知られているように、例え
ば図６（ａ）により説明したサイリスタ型サージ防護素
子Ｚの各領域の構造、即ち各領域の不純物濃度や厚みな
どの選定により大にすることが可能である。しかし一方
この方法による保持電流ＩH の増大は、同時にサージ電
流容量を小にする結果をもたらし、両者はトレードオフ
の関係となる。従って両者を同時に満足させることは必
ずしも容易ではなく、しかも不純物濃度の精密な制御な
どを必要とするため製造も難しい。そこでその対策とし
て図８（ａ）（ｂ）に示す電極を除いた上面図と、その
Ａ−Ａ’矢視断面図の構成をもつ素子が提案された。こ
の素子は例えばＰ半導体共通基板の一面に設けたＮ1 ベ
ース領域が、複数箇所においてＰ1 エミッタ領域を突き
抜けて表面に露呈し、Ｎ2 ベース領域が複数箇所におい
てＰ2 エミッタ領域を突き抜けて表面に露呈すると同時
に、前記露呈Ｎ1 ベース領域Ｓ1 とＰ1 エミッタ領域が
金属電極Ｔ1 により短絡され、前記露呈Ｎ2 ベース領域
Ｓ2 がＰ2 エミッタ領域と金属電極Ｔ2 により短絡され
た構造をもつサージ防護素子である。2. Description of the Related Art A bidirectional thyristor type surge protection device having a basic structure composed of a PNPNP layer shown in FIG. 6A and having a current-voltage characteristic (showing only one direction) shown in FIG. Because of its low cost, it is often used for surge protection of weak electric circuits such as communication circuits. This protection element is a protected circuit H as shown in FIG.
Is used by connecting between both ends of the surge protection device Z, for example, a surge S having a voltage value exceeding V BO of the surge protection element Z shown in FIG.
When it enters the line, it is turned on immediately to protect the protected circuit H. In this case, the surge protection element Z is required to immediately cut off the current passed by the power supply voltage E 0 after passing the surge current and return to the state before the surge intrusion. For that purpose, as is well known, the holding current I H of the protective element Z needs to satisfy the relation of I H > E 0 / R, where R: circuit impedance E 0 : power supply voltage, and in order to obtain a good breaking performance. Is required to have a large holding current I H. By the way, as is known in the art, the holding current I H is largely set by, for example, selecting the structure of each region of the thyristor type surge protection device Z described with reference to FIG. 6A, that is, the impurity concentration and thickness of each region. It is possible to On the other hand, however, the increase of the holding current I H by this method also brings about a result of reducing the surge current capacity at the same time, and the two are in a trade-off relationship. Therefore, it is not always easy to satisfy both of them, and moreover, manufacturing is difficult because precise control of impurity concentration is required. Therefore, as a countermeasure against this, an element having a top view excluding the electrodes shown in FIGS. 8A and 8B and a cross-sectional view taken along the line AA ′ of the element has been proposed. In this device, for example, the N 1 base region provided on one surface of the P semiconductor common substrate penetrates the P 1 emitter region at a plurality of positions and is exposed on the surface, and the N 2 base region penetrates a P 2 emitter region at a plurality of positions to the surface. At the same time, the exposed N 1 base region S 1 and the P 1 emitter region are short-circuited by the metal electrode T 1 , and the exposed N 2 base region S 2 is short-circuited by the P 2 emitter region and the metal electrode T 2. It is a surge protection device with.
【０００３】[0003]
【発明が解決しようとする課題】この提案されたサージ
防護素子の構造によれば、以下に記載する動作説明から
明らかなように、露呈Ｎ1 ，Ｎ2 ベース領域Ｓ1 ，Ｓ2
を設けることのない従来のサージ防護素子に比べて、露
呈Ｎ1 ，Ｎ2 ベース領域Ｓ1 ，Ｓ2 の数、配置等によっ
て保持電流ＩH を増大させることができるので製造も容
易である。しかしその反面保持電流ＩH を増大させるた
め、例えば露呈Ｎ1 ベース領域の数や面積を増大させる
と、これに比例して図６（ｂ）に示すスイッチング電流
ＩS を増大させる。従って遮断性能を向上できても、サ
ージに対する動作性能を低下させる欠点がある。即ちこ
の提案されたサージ防護素子の電極Ｔ1 からＴ2 方向
（図８（ｂ）中矢印参照）のタンオン時、印加電圧が接
合Ｊ2 の耐圧ＶBOを越えると、図８（ｂ）のように電流
Ｉ0 ，Ｉ1 ，Ｉ2 等の成分からなる電流Ｉが流れる。こ
のうちＩ1成分とＮ2 ベース領域の実効横方向抵抗ＲN
による電圧降下が接合Ｊ1 を順バイアスし、このバイア
ス電圧が接合Ｊ1 の立上り電圧を越えると、始めて接合
Ｊ1から正孔の注入が起こって、電極Ｔ1 ，Ｔ2 間をタ
ンオフするに至る。このため露呈Ｎ1 ベース領域Ｓ1 の
ない構造のものに比べて、スイッチング電流ＩS を増大
させる。次にオン状態では露呈Ｎ1 ベース領域Ｓ1 の直
下においては導通せず、Ｐ1 エミッタ領域の直下の部分
においてのみ導通して、接合Ｊ1 からの正孔の注入と接
合Ｊ3 からの電子の注入によりオン状態が保持される。
またオン状態が低下してタンオフする過程では、接合Ｊ
1 より注入された正孔は露呈Ｎ1 ベース領域Ｓ1におい
て再結合する。このため実効注入効率を下げ、露呈Ｎ1
ベース領域Ｓ1 のない構造のものに比べて保持ＩH を増
大させる。According to the structure of the proposed surge protection element, as is apparent from the operation description given below, the exposed N 1 , N 2 base regions S 1 , S 2 are exposed.
Since the holding current I H can be increased depending on the number and arrangement of the exposed N 1 and N 2 base regions S 1 and S 2 as compared with a conventional surge protection element that does not include the above, it is easy to manufacture. However, in order to increase the holding current I H , for example, if the number or area of the exposed N 1 base regions is increased, the switching current I S shown in FIG. 6B is increased in proportion to this. Therefore, even if the breaking performance can be improved, there is a drawback that the operating performance against a surge is lowered. That is, when the applied voltage exceeds the withstand voltage V BO of the junction J 2 at the time of tan-on in the direction from the electrode T 1 to the electrode T 2 of the proposed surge protection element (see the arrow in FIG. Thus, the current I composed of the components such as the currents I 0 , I 1 , and I 2 flows. Of these, the effective lateral resistance R N of the I 1 component and the N 2 base region
Voltage drop due to the forward biasing the junction J 1, when the bias voltage exceeds the threshold voltage of the junction J 1, the first time by the injection of holes going from the junction J 1, between the electrode T 1, T 2 to Tan'ofu Reach Therefore, the switching current I S is increased as compared with the structure having no exposed N 1 base region S 1 . Next, in the ON state, conduction does not occur immediately under the exposed N 1 base region S 1 , but conduction occurs only under the P 1 emitter region, and injection of holes from the junction J 1 and electrons from the junction J 3 occur. The ON state is maintained by the injection of.
Also, in the process of turning off due to the decrease of the on-state, the junction J
The holes injected from 1 are recombined in the exposed N 1 base region S 1 . Therefore, the effective injection efficiency is reduced, and the exposure N 1
The retention I H is increased as compared to the structure having no base region S 1 .
【０００４】以上の動作機構によるスイッチング電流Ｉ
S の増大と、保持電流ＩH の増大効果は、図８（ｂ）の
電流Ｉ1 の流路に沿ったＮ2 ベース領域の実効横方向抵
抗ＲN が小さい程大となる。従って同一チップ面積では
露呈Ｎ1 ベース領域Ｓ1 間の距離が小となるから、露呈
Ｎ1 ベース領域Ｓ1 の数が多い程大となることは明らか
である。しかしながら図８（ｂ）に示したＮ1 ベース領
域からＮ2 ベース領域に直接流れる電流成分Ｉ0 は、タ
ンオン動作に寄与しない無効電流として流れ、付加電流
としてスイッチング電流ＩS のみを増加させることにな
る。なお図８（ｂ）の電流成分Ｉ2 も無効電流である
が、これは図６（ａ）に示した従来のものと同じである
ので説明を省略する。即ち以上から図８に示した露呈Ｎ
1 ベース領域Ｓ1 を設けた構造では、Ｓの数を多くする
程保持電流ＩH の増大効果は大であるが、その反面露呈
Ｎ1 ベース領域Ｓ1 の数と面積に比例して不必要な電流
Ｉ0 が流れて、スイッチング電流ＩSの増大を招く結果
となるため、サージ動作性能を低下させることになる。
更にサイリスタ型素子のタンオンにおいては、最もタン
オンの容易な一点において先ずタンオンし、そののちタ
ンオンした領域が全面積、例えば図８のＰ1 領域に拡が
る過程をとるのが通常である。従ってオン面積の増大速
度がサージ電流の増加速度より遅いと、タンオン過程で
電流密度が過大となり、これが限度をこすと素子を破壊
することになる。このため電流の立上りの速いサージに
対しては防護が不充分となる。これを防ぐためには電流
の立上りの速いサージの場合にも、少なくともその電流
の増大に対応して円滑にオン面積が増大することが必要
である。しかし保持電流ＩH の増大を図るため、図８の
露呈Ｎ1 ベース領域Ｓ1 の数と増大させるとその相互距
離も小さくなるので、一点から始まったオンが全面に拡
がるのを妨害する。このためこれによってもサージ電流
容量を低下させて、サージ動作性能を低下させる。The switching current I by the above operating mechanism
The effect of increasing S and increasing the holding current I H is greater as the effective lateral resistance R N of the N 2 base region along the flow path of the current I 1 in FIG. 8B is smaller. Therefore, in the same chip area, the distance between the exposed N 1 base regions S 1 becomes small, and it is obvious that the larger the number of exposed N 1 base regions S 1 , the larger. However, the current component I 0 directly flowing from the N 1 base region to the N 2 base region shown in FIG. 8B flows as a reactive current that does not contribute to the tan-on operation, and only the switching current I S is increased as an additional current. Become. The current component I 2 in FIG. 8 (b) is also a reactive current, but this is the same as the conventional one shown in FIG. 6 (a), and therefore its explanation is omitted. That is, from the above, the exposure N shown in FIG.
In the structure in which the 1 base region S 1 is provided, the effect of increasing the holding current I H is greater as the number of S is increased, but on the other hand, the exposure is unnecessary in proportion to the number and area of the N 1 base region S 1. Current I 0 flows, resulting in an increase in the switching current I S , which results in deterioration of the surge operation performance.
Further, in the tan-on of the thyristor type element, it is usual to first tan-on at a point where the tan-on is the easiest, and then the tan-on region spreads over the entire area, for example, the P 1 region in FIG. Therefore, if the increasing rate of the on-area is slower than the increasing rate of the surge current, the current density becomes excessive in the tan-on process, and if this exceeds the limit, the element will be destroyed. For this reason, protection is insufficient for surges with a rapid rise of current. In order to prevent this, even in the case of a surge with a rapid rise of current, it is necessary to smoothly increase the on-area in response to the increase in current. However, if the number of exposed N 1 base regions S 1 in FIG. 8 is increased in order to increase the holding current I H , the mutual distance also becomes smaller, so that the ON starting from one point is prevented from spreading to the entire surface. Therefore, this also reduces the surge current capacity and the surge operation performance.
【０００５】[0005]
【発明の目的】本発明は前記した従来構造の問題点を一
挙に解決しうるサージ防護素子、即ちサージ動作性能を
犠牲にすることなく遮断性能を向上させうる製造容易な
サージ防護素子の提示にある。It is an object of the present invention to provide a surge protection element which can solve the above-mentioned problems of the conventional structure all at once, that is, a surge protection element which can improve the interruption performance without sacrificing the surge operation performance. is there.
【０００６】[0006]
【課題を解決するための本発明の手段】本発明の目的は
次の手段により達成される。即ち図１に示す本発明の基
本構造を示す実施例図のように、Ｐ半導体共通基板の両
面にそれぞれＮ1 ベース領域とＰ1 エミッタ領域、Ｎ2
ベース領域とＰ2 エミッタ領域とを設けると共に、前記
Ｎ1 ベース領域およびＮ2 ベース領域の一部が互いに重
ならない交互配置のもとに複数箇所において、それぞれ
前記Ｐ1 およびＰ2 エミッタ領域を突き抜けて表面に露
呈する、露呈Ｎ1 およびＮ2 ベース領域Ｓ1 およびＳ2
を形成させ、この露呈Ｎ1 ベース領域Ｓ1 とＰ1 エミッ
タ領域、および露呈Ｎ2 ベース領域Ｓ1 とＰ2 エミッタ
領域とを、それぞれ各面において短絡してそれぞれ一つ
の電極Ｔ1，Ｔ2 をなすように構成する。また図１中に
示す両面の露呈Ｎ1 ベース領域Ｓ1と露呈Ｎ2 ベース領
域Ｓ2 間の最短距離Ｄと、前記Ｐ半導体共通基板の中央
部の厚さＷP との間 ＷP ／２≦Ｄ≦２ＷP をもたせ、また更に露呈Ｎ1 およびＮ2 ベース領域
Ｓ1 ，Ｓ2 の最大幅φとＰ半導体共通基板の厚さＷP と
の間に ＷP ≦φ≦４ＷP の関係をもたせることにより達成される。The objects of the present invention are achieved by the following means. That is, as shown in the embodiment of the present invention shown in FIG. 1, the N 1 base region, the P 1 emitter region and the N 2 base region are formed on both sides of the P semiconductor common substrate.
A base region and a P 2 emitter region are provided, and the N 1 base region and the N 2 base region penetrate through the P 1 and P 2 emitter regions, respectively, at a plurality of locations under an alternating arrangement in which a part of the N 1 base region and the N 2 base region do not overlap each other. Exposed N 1 and N 2 base regions S 1 and S 2
And the exposed N 1 base region S 1 and P 1 emitter region and the exposed N 2 base region S 1 and P 2 emitter region are short-circuited on each surface to form one electrode T 1 , T 2 respectively. It is configured to Further, between the shortest distance D between the exposed N 1 base region S 1 and the exposed N 2 base region S 2 shown in FIG. 1 and the thickness W P of the central portion of the P semiconductor common substrate, W P / 2 ≤D≤2W P , and further, the relationship of W P ≤φ≤4 W P between the maximum width φ of the exposed N 1 and N 2 base regions S 1 and S 2 and the thickness W P of the P semiconductor common substrate. It is achieved by having.
【０００７】[0007]
【作用】以上からわかるように本発明は、両面の露呈Ｎ
1 およびＮ2 ベース領域Ｓ1 ，Ｓ2 を有効面積とする逆
向きの単位サイリスタが中央のＰ半導体共通基板、即ち
Ｐベース領域を共通として交互に配置された構造であっ
て、次のように動作する。電極Ｔ1 →Ｔ2 方向における
オン状態では、露呈Ｎ2 ベース領域Ｓ2 の部分が導通し
ている。電流が減少してタンオフに至る動作における露
呈Ｎ1 ベース領域Ｓ1 の作用は、図８（ａ）（ｂ）を用
いて前記した従来素子の露呈Ｎ1 ベース領域Ｓ1 のそれ
と同じである。従って本発明によれば同一チップ面積の
場合、露呈Ｎ1 およびＮ2 ベース領域Ｓ1 およびＳ2 の
数を増し、Ｓ1 とＳ2 間の距離Ｄを小さくすることによ
り、保持電流ＩH を増大させて遮断性能を向上させるこ
とができる。次にタンオン過程では、図１に示すように
露呈Ｎ1 ベース領域Ｓ1 に対向する部分には、Ｐ2 エミ
ッタ領域が位置している。従って本発明の構造では、図
８によって前記した従来の構造のものと異なり、無効電
流成分Ｉ0 が流れるのが阻止される。このためＩ0 に起
因するスイッチング電流ＩS の増大によるサージ動作性
能の低下を生ずることがないもので、これは電極Ｔ2 →
Ｔ1 方向の動作時において同じである。また本発明では
露呈Ｎ2 ベース領域Ｓ2 に対応する部分が、各々一つの
単位サイリスタを形成している。従ってＳ2 の面積を小
（同一チップ面積で数を大）にすれば、この中でのオン
の拡がり速度の問題を解決することができる。このため
前記タンオン時の電流密度の増大による電流密度の低下
の問題も解決でき、更に本発明では従来の構造と異な
り、単位サイリスタがチップ全面に分散された形となる
ため、オン時の発熱が分散される。従ってこれによって
も電流容量の増大を図りうるもので、以上については電
極Ｔ2 →Ｔ1 方向の動作においても同様である。従って
本発明によれば従来の構造のものに比べて、サージ動作
性能と遮断性能の共にすぐれた製造容易なサージ防護素
子を実現できる。As can be seen from the above, the present invention is applicable to both sides of the exposure N
1 and N 2 base regions S 1 and S 2 are effective areas, and unitary thyristors in opposite directions are arranged alternately with the central P semiconductor common substrate, that is, the P base regions in common, as follows. Operate. In the ON state in the direction of the electrode T 1 → T 2 , the exposed N 2 base region S 2 is conductive. Action of exposed N 1 base region S 1 in operation current reaches the Tan'ofu decreases is the same as that of exposed N 1 base region S 1 of the prior art device described above with reference to FIG. 8 (a) (b). Therefore, according to the present invention, for the same chip area, the holding current I H can be reduced by increasing the number of exposed N 1 and N 2 base regions S 1 and S 2 and reducing the distance D between S 1 and S 2. It can be increased to improve the blocking performance. Next, in the tan-on process, as shown in FIG. 1, the P 2 emitter region is located in the portion facing the exposed N 1 base region S 1 . Therefore, in the structure of the present invention, unlike the conventional structure described above with reference to FIG. 8, the reactive current component I 0 is prevented from flowing. Therefore, the surge operation performance is not deteriorated due to the increase of the switching current I S due to I 0, which is caused by the electrode T 2 →
The same is true during operation in the T 1 direction. Further, in the present invention, the portions corresponding to the exposed N 2 base region S 2 each form one unit thyristor. Therefore, if the area of S 2 is made small (the number is large with the same chip area), the problem of the ON spread speed in this can be solved. Therefore, the problem of a decrease in current density due to an increase in current density at the time of tan-on can be solved. Furthermore, unlike the conventional structure, the unit thyristor is distributed over the entire surface of the chip, and therefore heat generation at the time of on-state is generated. Distributed. Therefore, this can also increase the current capacity, and the same applies to the above in the operation in the direction of the electrode T 2 → T 1 . Therefore, according to the present invention, it is possible to realize a surge protection element which is superior in both surge operation performance and interruption performance and easy to manufacture as compared with the conventional structure.
【０００８】以上に加えて本発明においては、露呈Ｎ1
ベース領域Ｓ1 と露呈Ｎ2 ベース領域は、それぞれＤの
間隔をもつように設けられ、しかも前記したように露呈
Ｎ1ベース領域Ｓ1 はＰ2 エミッタ領域と対面し、露呈
Ｎ2 ベース領域Ｓ2 はＰ1 エミッタ領域と対面した構造
をもつ、従って以下に説明するように距離Ｄを、製造技
術上の加工精度などと関連のもとに適切に選定すること
により、サージ動作性能を更に向上させることができ、
また露呈ベース領域Ｓ1 とＳ2 の大きさφを製造技術上
の加工精度などと関連させて適切に選定することによ
り、タンオン過程におけるオン面積の拡がり速度を更に
向上させて電流容量を向上できる。In addition to the above, in the present invention, the exposure N 1
The base region S 1 and the exposed N 2 base region are provided so as to have an interval of D, respectively, and as described above, the exposed N 1 base region S 1 faces the P 2 emitter region and is exposed to the exposed N 2 base region S. 2 has a structure facing the P 1 emitter region. Therefore, as described below, by properly selecting the distance D in relation to the processing accuracy in manufacturing technology, surge operation performance is further improved. Can be
Further, by appropriately selecting the size φ of the exposed base regions S 1 and S 2 in relation to the processing accuracy in manufacturing technology, etc., it is possible to further improve the on-area spreading speed in the tan-on process and improve the current capacity. .
【０００９】即ちオン時本発明の構造においては、電流
Ｉ2 が露呈ベース領域Ｓ1 からＳ2へと、Ｐ半導体共通
基板を斜めに横切って流れるが、これは接合Ｊ1 の順バ
イアスには無効な電流であり、スイッチング電流ＩS を
増大させる一因となっている。従って電流Ｉ2 を小とす
ることによりサージ動作性能を向上しうる。この電流Ｉ
2 は図１（ｃ）中における、電流の流路を考えることに
より理解されるように、間隔ＤとＷP に関係し、ＷP を
例えば一定とした場合Ｄが小になるに伴い急激に大にな
り、Ｄが負となると図８で示した従来構造における無効
電流成分Ｉ0 と同じになる。一方図１において露呈ベー
ス領域Ｓ1 ，Ｓ2 の面積を一定としたとき距離Ｄを大に
すると、Ｓ1 ，Ｓ2 が数が減って露呈ベース領域の総面
積、従って電流容量の減少を招くことになる。このため
Ｄをあまり大にすることは好ましくない。従って以上か
ら距離Ｄには厚さＷP に対して最適な範囲があり、Ｄを
露呈ベース領域の形状や配置、各層の構造、例えば不純
物濃度や厚さとの関連、製造技術上の加工精度などを考
慮して最適に選定することにより、サージ動作性能を更
に向上できる。実験によれば最適範囲として ＷP ／２≦Ｄ≦２ＷP ………（１） とするのが適当であるとする結果が得られた。That is, in the structure of the present invention when turned on, the current I 2 flows from the exposed base region S 1 to S 2 diagonally across the P semiconductor common substrate, which is not the forward bias of the junction J 1. This is an invalid current, which is one of the causes of increasing the switching current I S. Therefore, the surge operation performance can be improved by reducing the current I 2 . This current I
2 is related to the distance D and W P as can be understood by considering the flow path of the current in FIG. 1 (c), and when W P is constant, for example, as D becomes smaller, When it becomes large and D becomes negative, it becomes the same as the reactive current component I 0 in the conventional structure shown in FIG. On the other hand, in FIG. 1, when the distance D is increased when the area of the exposed base regions S 1 and S 2 is constant, the number of S 1 and S 2 is reduced and the total area of the exposed base regions, and thus the current capacity, is reduced. It will be. Therefore, it is not preferable to make D too large. Therefore, from the above, the distance D has an optimum range for the thickness W P , and D is exposed. The shape and arrangement of the base region, the structure of each layer, for example, the relation with the impurity concentration and the thickness, the processing accuracy in manufacturing technology, etc. The surge operation performance can be further improved by optimally selecting in consideration of the above. According to the experiment, the optimum range is set as W P / 2 ≦ D ≦ 2W P (1).
【００１０】次にタンオン過程におけるオン面積の拡が
りに関係して、露呈ベース領域Ｓ1，Ｓ2 の大きさφに
ついて説明する。図２は本発明において電流Ｉ1 が増加
して接合Ｊ1 を順バイアスし、タンオンが始まる過程を
示す部分拡大図である。電極Ｔ1 →Ｔ2 方向の動作にお
いては順バイアス露呈Ｎ2 ベース領域Ｓ2 の真上の中央
部において最大となる。従ってこの部分で先ず正孔の注
入ｉh が起こり、接合Ｊ3 からの電子注入ｉe と相まっ
て、この部分からタンオンが始まって露呈Ｎ2 ベース領
域全面に拡がることになる。この拡がり現象は主として
注入キャリア（電子と正孔）の縦および横方向の拡散に
よって定まる。このため露呈Ｎ2 ベース領域Ｓ2 の大き
さφは、Ｐ半導体共通基板の厚さＷP に依存し、φ／２
がＷP 程度であれば動作時間は縦方向のキャリア移動時
間のみによってほぼ定まり、これを越えるとオンが全面
に拡がるまでに要する時間は大となる。従って電流密度
が過大となるのを招かないためには、電流の立上り速度
が速い用途（商用商波交流のような遅いものでは殆ど問
題はない）に対しては、露呈Ｎ2 ベース領域Ｓ2 の大き
さについて上限を設けることが有効であり、これは電極
Ｔ2 →Ｔ1 方向の動作についても全く同様に云える。一
方露呈ベース領域Ｓ1 ，Ｓ2 間の距離Ｄが前記（１）式
により制限された条件のもとで、露呈ベース領域Ｓ1 と
Ｓ2 の大きさが小さいと、同一チップ面積では電流容量
を定めるＳ1 ，Ｓ2 の総面積が小さくなる。従ってさこ
の面から露呈ベース領域Ｓ1 とＳ2 の面積の下限に制限
を受けざるを得ない。従ってφについても電流の立上り
の速い用途に対してはＰ半導体共通基板の厚さＷP に関
して最適範囲があり、これを満足させることにより更に
電流容量を増大させることができる。実験によれば最適
範囲は、露呈ベース領域Ｓ1 ，Ｓ2 の形状や配置、各層
の構造例えば不純物濃度や厚さ、製造上の加工精度など
の条件、露呈ベース領域の距離Ｄなどを加味して ＷP ≦φ≦４ＷP ……………（２） とするのが適当であるとする結果が得られた。Next, the size φ of the exposed base regions S 1 and S 2 will be described with reference to the spread of the on-area in the tan-on process. FIG. 2 is a partially enlarged view showing a process in which the current I 1 increases and the junction J 1 is forward biased to start tanning in the present invention. In the operation in the direction of the electrode T 1 → T 2 , the forward bias exposure N 2 becomes maximum in the central portion just above the base region S 2 . Accordingly occur injection i h of first holes in this section, together with an electron injection i e from the junction J 3, so that the single note from this portion spreads exposed N 2 base entire region starting. This spreading phenomenon is mainly determined by vertical and horizontal diffusion of injected carriers (electrons and holes). Therefore, the size φ of the exposed N 2 base region S 2 depends on the thickness W P of the P semiconductor common substrate, and φ / 2
Is approximately W P , the operation time is almost determined only by the carrier movement time in the vertical direction, and if it exceeds this, the time required for the ON to spread to the entire surface becomes long. Therefore, in order to prevent the current density from becoming excessively high, the exposure N 2 base region S 2 is used for applications in which the current rising speed is fast (a slow one such as commercial commercial wave AC causes almost no problem). It is effective to set an upper limit with respect to the magnitude of the above, which can be said to be exactly the same for the operation in the direction of the electrode T 2 → T 1 . On the other hand, if the size of the exposed base regions S 1 and S 2 is small under the condition that the distance D between the exposed base regions S 1 and S 2 is limited by the equation (1), the current capacity is the same in the same chip area. The total area of S 1 and S 2 that determines Therefore, from this point of view, there is no choice but to be limited by the lower limit of the area of the exposed base regions S 1 and S 2 . Therefore, as for φ, there is an optimum range for the thickness W P of the P semiconductor common substrate for applications in which the current rises quickly, and by satisfying this range, the current capacity can be further increased. According to the experiment, the optimum range takes into consideration the shape and arrangement of the exposed base regions S 1 and S 2 , the structure of each layer such as the concentration and thickness of impurities, the conditions such as processing accuracy in manufacturing, and the distance D of the exposed base region. As a result, it was found that it is appropriate to set W P ≦ φ ≦ 4 W P (2).
【００１１】[0011]
【実施例】以上本発明について説明したが、例えば一方
向極性の侵入サージが殆どである回路の保護のため、例
えば図３，図４の変形構成をとることができる。また２
つの線路と接地間にサージが同時に侵入したときの保護
をも確実に行えるようにするため、図５のように本発明
の２箇の素子を複合した３端子構成とすることもでき
る。次にこれらについて説明する。図３（（ａ）図は電
極を除いた上面図、（ｂ）図はそのＡ−Ａ’部矢視断面
図）の例は、上下面の露呈Ｎ1 ，Ｎ2 ベース領域Ｓ1 ，
Ｓ2 の面積をＳ2 ＞Ｓとなるように異ならせる。そして
電極Ｔ2 →Ｔ1 方向の電流容量に比べてＴ1 →Ｔ2方向
の電流容量が大となるようにして、同一チップ面積のも
とに一方向の電流容量を犠牲にして他方向の電流容量を
増大させたもので、Ｓ1 ，Ｓ2 の面積が異なるほかはＷ
P ／２≦Ｄ≦２ＷP の条件を含めて、図１に示したもの
と本質的に同じである。次に図４（（ａ）図は電極を除
いた上面図、（ｂ）図はそのＡ−Ａ’部矢視断面図）の
例は図３の例と同様に一方向の電流容量を他方向の電流
容量に比べ大としたもので、この例では露呈Ｎ2 ベース
領域Ｓ2 を連続した一つの領域としている点が異なるの
みであり、実質的な動作，作用，効果については変わる
ものはない。また更に図５（（ａ）図は電極を除いた上
面図、（ｂ）図はそのＡ−Ａ’部矢視断面図、（ｃ）図
は基本保護回路図）の例は、本発明を３端子複合素子に
適用したもので、サージ電圧が図（ｃ）のように、線路
Ｌ1 と接地Ｇ間に印加された場合には、電極Ｔ1 −Ｔ3
間が動作し、線路Ｌ2 と接地Ｇ間に印加された場合に
は、電極Ｔ2 −Ｔ3 間が動作するようにする（サージの
極性が逆の場合も同様である）。またＰベース領域とＮ
2 ベース領域を共通として、電極Ｔ1 −Ｔ3 間が動作し
たときこれに縦続して電極Ｔ2 −Ｔ3 間が動作し、電極
Ｔ2 −Ｔ3 間が動作したとき電極Ｔ1 −Ｔ3 間が縦続動
作するようにして、接地Ｇに対して線路Ｌ1 とＬ2 に同
時に正逆サージが侵入したときにも、時間差なくＴ1 −
Ｔ3 間およびＴ2 −Ｔ3 が同時に動作して、線路Ｌ1 ，
Ｌ2 間に横サージを生じないようにし、これによる被防
護回路Ｈの損傷などを招かないようにしたものである。
なお以上における説明では、露呈ベース領域Ｓ1 ，Ｓ2
の形状を円形としているが、これは本発明の本質ではな
く、本発明の範囲内において種々の形状から考えられ
る。またＳ1 ，Ｓ2 との配置についても同様である。こ
の場合露呈ベース領域の露呈形状が円形以外の場合に
は、距離Ｄについては最短距離、露呈ベース領域Ｓ1 ，
Ｓ2 の大きさφについては最大径を考えればよい。また
以上においては伝導型がＰ1 Ｎ1 ＰＮ2 Ｐ2 型である場
合について説明したが、逆の伝導型であるＮ1 Ｐ1 ＮＰ
2 Ｎ2 としても、本発明が同様に成立することは云うま
でもない。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention has been described above. For example, in order to protect a circuit in which a unidirectional polarity intrusion surge is mostly present, for example, modified configurations shown in FIGS. 3 and 4 can be adopted. Again 2
In order to ensure protection when surges simultaneously enter between one line and the ground, a three-terminal configuration in which two elements of the present invention are combined as shown in FIG. 5 can be used. Next, these will be described. 3 ((a) is a top view without electrodes, (b) is a sectional view taken along the line AA 'in FIG. 3), the upper and lower surfaces are exposed N 1 , N 2 base regions S 1 ,
The area of S 2 made different so as to be S 2> S. Then, the current capacity in the T 1 → T 2 direction is set to be larger than that in the electrode T 2 → T 1 direction, and the current capacity in one direction is sacrificed in the same chip area while the current capacity in the other direction is sacrificed. The current capacity is increased, and W is different except that the areas of S 1 and S 2 are different.
It is essentially the same as that shown in FIG. 1 including the condition of P / 2 ≦ D ≦ 2W P. Next, the example of FIG. 4 (FIG. 4A is a top view without electrodes, FIG. 4B is a cross-sectional view taken along the line AA ′ in FIG. 4B) shows the same unidirectional current capacity as the example of FIG. The current N is larger than the current capacity in the direction, and in this example, the exposed N 2 base region S 2 is a single continuous region. The only difference is the actual operation, action, and effect. Absent. Further, the example of FIG. 5 (FIG. 5A is a top view without electrodes, FIG. 5B is a sectional view taken along the line AA ′ in FIG. 5C, and FIG. 5C is a basic protection circuit diagram) show the present invention. 3 which was applied to a terminal composite element, such as the surge voltage is FIG (c), when applied with the line L 1 and the ground G, the electrode T 1 -T 3
When the voltage is applied between the line L 2 and the ground G, the electrodes T 2 and T 3 are operated (the same applies when the polarity of the surge is opposite). In addition, P base area and N
As a common two base regions, the electrode T 2 -T 3 between operates by cascade thereto when between electrodes T 1 -T 3 is operated, the electrode T 1 -T when between electrodes T 2 -T 3 is operated Even if the forward and reverse surges simultaneously enter the lines L 1 and L 2 with respect to the ground G by cascading between the three, T 1 −
Between T 3 and T 2 −T 3 operate simultaneously, and the lines L 1 ,
A lateral surge is not generated between L 2 and the protected circuit H is not damaged by this.
In the above description, the exposed base regions S 1 , S 2
Although the shape is circular, this is not the essence of the present invention, and various shapes can be considered within the scope of the present invention. The same applies to the arrangement of S 1 and S 2 . In this case, when the exposed shape of the exposed base region is other than circular, the distance D is the shortest distance, the exposed base region S 1 ,
Regarding the size φ of S 2, the maximum diameter may be considered. Further, although the case where the conductivity type is the P 1 N 1 PN 2 P 2 type has been described above, the opposite conductivity type is N 1 P 1 NP.
It goes without saying that the present invention is similarly applicable to 2 N 2 .
【００１２】[0012]
【発明の効果】以上から明らかなように本発明によれ
ば、サージ動作性能と遮断性能にすぐれ、しかも雷サー
ジなどの立上りの速いサージに対しても十分な保護を行
いうるすぐれたサージ防護素子を提供しうるもので、通
信回路などの雷サージ防護などこの種サージ防護にすぐ
れた効果を奏する。As is apparent from the above, according to the present invention, an excellent surge protection element having excellent surge operation performance and cutoff performance, and being capable of sufficiently protecting against surges such as lightning surges having a fast rising edge. It provides excellent effects for this type of surge protection such as protection against lightning surges in communication circuits and the like.
【図１】本発明の基本構造を示す実施例の説明図であ
る。FIG. 1 is an explanatory view of an embodiment showing the basic structure of the present invention.
【図２】本発明におけるタンオンが始まる過程の説明図
である。FIG. 2 is an explanatory diagram of a process of starting tan-on in the present invention.
【図３】本発明の他の実施例の説明図である。FIG. 3 is an explanatory diagram of another embodiment of the present invention.
【図４】本発明の他の実施例の説明図である。FIG. 4 is an explanatory diagram of another embodiment of the present invention.
【図５】本発明を３端子複合素子に適用した例の説明図
である。FIG. 5 is an explanatory diagram of an example in which the present invention is applied to a three-terminal composite element.
【図６】従来のサージ防護素子の説明図である。FIG. 6 is an explanatory diagram of a conventional surge protection element.
【図７】従来のサージ防護素子の基本動作回路である。FIG. 7 is a basic operation circuit of a conventional surge protection element.
【図８】特性の改善されたサージ防護素子の説明図であ
る。FIG. 8 is an explanatory diagram of a surge protection element having improved characteristics.
Ｅ0 電源電圧 Ｒ 回路インピーダンス Ｚ サージ防護素子 Ｈ 被保護回路 Ｓ サージ Ｄ 露呈Ｎ1 ベース領域Ｓ1 と露呈Ｎ2 ベース領域Ｓ2
間の距離 ＷP Ｐ共通半導体基板の厚み φ 露呈Ｎ1 ベース領域Ｓ1 と露呈Ｎ2 ベース領域Ｓ2
の大きさE 0 Power supply voltage R Circuit impedance Z Surge protection element H Protected circuit S Surge D Exposure N 1 Base area S 1 and Exposure N 2 Base area S 2
Distance between W P P Common semiconductor substrate thickness φ Exposed N 1 base region S 1 and exposed N 2 base region S 2
Size of
Claims (5)
れＮ1 （Ｐ1 ）ベース領域とＰ1 （Ｎ1 ）エミッタ領
域、Ｎ2 （Ｐ2 ）ベース領域とＰ2 （Ｎ2 ）エミッタ領
域を設け、前記Ｎ1 （Ｐ1 ）ベース領域およびＮ2 （Ｐ
2 ）ベース領域の一部が複数箇所においてそれぞれ前記
Ｐ1 （Ｎ1 ）およびＰ2 （Ｎ2 ）エミッタ領域を突き抜
けて表面に露呈し、かつ両面の露呈Ｎ1 とＮ2 ベース領
域が互いに重なる部分がないようにはなれて交互に配置
されて、各面においてそれぞれ前記Ｐ1 （Ｎ1 ）エミッ
タ領域と露呈Ｎ1 （Ｐ1 ）ベース領域およびＰ
2 （Ｎ2 ）エミッタ領域と露呈Ｎ2 （Ｐ2 ）ベース領域
とが短絡されて一つの電極をなすように構成されると共
に、前記両面の露呈Ｎ1 とＮ2 のベース領域間の最短距
離Ｄと、中央のＰ（Ｎ）半導体共通基板の厚さＷP との
関係をＷP ／２≦Ｄ≦２ＷPとしたことを特徴とするサ
ージ防護素子。1. A N 1 (P 1 ) base region and a P 1 (N 1 ) emitter region, and an N 2 (P 2 ) base region and a P 2 (N 2 ) emitter, respectively, on both surfaces of a P (N) semiconductor common substrate. A region is provided, and the N 1 (P 1 ) base region and N 2 (P 1 ) are provided.
2 ) Part of the base region penetrates the P 1 (N 1 ) and P 2 (N 2 ) emitter regions and is exposed to the surface at a plurality of locations, and the exposed N 1 and N 2 base regions on both sides overlap each other. They are arranged so as not to have any parts and are alternately arranged, and the P 1 (N 1 ) emitter region, the exposed N 1 (P 1 ) base region and the P 1
The 2 (N 2 ) emitter region and the exposed N 2 (P 2 ) base region are short-circuited to form one electrode, and the shortest distance between the exposed N 1 and N 2 base regions on both surfaces. A surge protection element characterized in that the relationship between D and the thickness W P of the central P (N) semiconductor common substrate is W P / 2 ≦ D ≦ 2W P.
ス領域の最大径φと中央のＰ（Ｎ）半導体共通基板の厚
さＷP との関係をＷP ≦φ≦４ＷP としたことを特徴と
するサージ防護素子。2. The method of claim 1, the relationship between the exposed N 1 and N 2 of the maximum diameter phi a central base region P (N) of the semiconductor common substrate thickness W P was W P ≦ φ ≦ 4W P Surge protection element characterized by
ベース領域の面積を異ならせたことを特徴とするサージ
防護素子。3. The double sided exposure N 1 and N 2 according to claim 1.
A surge protection element characterized by having different areas of the base region.
域が互いに連続した一つの領域をなすことを特徴とする
サージ防護素子。4. The surge protection element according to claim 1, wherein the exposed base regions on one surface form one continuous region.
る複合型のサージ防護素子。5. A composite type surge protection device having the structure according to any one of claims 1 to 4 as a basic constituent element.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03335859A JP3142617B2 (en) | 1991-11-27 | 1991-11-27 | Surge protection element |
| US07/946,092 US5352905A (en) | 1991-11-27 | 1992-09-17 | Semiconductor surge suppressor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03335859A JP3142617B2 (en) | 1991-11-27 | 1991-11-27 | Surge protection element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0677472A true JPH0677472A (en) | 1994-03-18 |
| JP3142617B2 JP3142617B2 (en) | 2001-03-07 |
Family
ID=18293186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03335859A Expired - Fee Related JP3142617B2 (en) | 1991-11-27 | 1991-11-27 | Surge protection element |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5352905A (en) |
| JP (1) | JP3142617B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2699015B1 (en) * | 1992-12-04 | 1995-02-24 | Sgs Thomson Microelectronics | Surge protection device. |
| US5483086A (en) * | 1993-04-20 | 1996-01-09 | Shindengen Electric Manufacturing Co., Ltd. | Four layer semiconductor surge protector having plural short-circuited junctions |
| FR2709872B1 (en) * | 1993-09-07 | 1995-11-24 | Sgs Thomson Microelectronics | Bidirectional shockley diode. |
| US5500377A (en) * | 1994-09-06 | 1996-03-19 | Motorola, Inc. | Method of making surge suppressor switching device |
| US5815359A (en) * | 1995-09-08 | 1998-09-29 | Texas Instruments Incorporated | Semiconductor device providing overvoltage protection against electrical surges of positive and negative polarities, such as caused by lightning |
| JP2002184952A (en) * | 2000-12-15 | 2002-06-28 | Shindengen Electric Mfg Co Ltd | Semiconductor device and its manufacturing method |
| JP3742636B2 (en) * | 2003-08-27 | 2006-02-08 | ファナック株式会社 | Surge voltage suppressor |
| CN103956387A (en) * | 2014-05-15 | 2014-07-30 | 安徽芯旭半导体有限公司 | Surge protection device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3391310A (en) * | 1964-01-13 | 1968-07-02 | Gen Electric | Semiconductor switch |
| US3907615A (en) * | 1968-06-28 | 1975-09-23 | Philips Corp | Production of a three-layer diac with five-layer edge regions having middle region thinner at center than edge |
| NL162658C (en) * | 1969-04-08 | 1980-06-16 | Organon Nv | METHOD FOR CONVERTING A 17BETA HYDROXY STERID INTO THE COMPATIBLE 17 ALFA HYDROXY COMPOUND |
| SE414357B (en) * | 1978-08-17 | 1980-07-21 | Asea Ab | OVERVOLTAGE PROTECTION FOR PROTECTION OF SEMICONDUCTOR COMPONENTS OF LOW EFFECT TYPE |
| US4644437A (en) * | 1985-11-01 | 1987-02-17 | At&T Bell Laboratories | Telephone subscriber loop overvoltage protection integrated circuit |
| US4905119A (en) * | 1988-06-27 | 1990-02-27 | Teccor Electronics, Inc. | Solid state overvoltage protection circuit |
| US4967256A (en) * | 1988-07-08 | 1990-10-30 | Texas Instruments Incorporated | Overvoltage protector |
| JPH0614546B2 (en) * | 1990-02-09 | 1994-02-23 | 新電元工業株式会社 | Compound thyristor |
-
1991
- 1991-11-27 JP JP03335859A patent/JP3142617B2/en not_active Expired - Fee Related
-
1992
- 1992-09-17 US US07/946,092 patent/US5352905A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP3142617B2 (en) | 2001-03-07 |
| US5352905A (en) | 1994-10-04 |
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