CN117832279A

CN117832279A - Shielding type buried U-groove SIC MOSFET structure for increasing source contact of JFET region

Info

Publication number: CN117832279A
Application number: CN202410013226.9A
Authority: CN
Inventors: 许一力
Original assignee: Beijing Qingxin Micro Energy Storage Technology Co ltd
Current assignee: Beijing Qingxin Micro Energy Storage Technology Co ltd
Priority date: 2024-01-04
Filing date: 2024-01-04
Publication date: 2024-04-05

Abstract

The invention discloses a shielding type buried channel U-groove SIC MOSFET structure for increasing source contact of a JFET region, which comprises a plurality of MOS (metal oxide semiconductor) cells connected in parallel, wherein shielding structures and source contacts are respectively added at the bottom and the top of the JFET region of the MOS cells, buried channel U-grooves are added in the source region of a device, the buried channel U-groove structure is added, the source size of the device can be reduced, the whole cell size is reduced, the width of the JFET region is greatly shortened at the bottom of the JFET region, the current path width of the device is reduced by depletion effect at the bottom of the JFET region, the short-circuit saturated current of the device is greatly reduced, the short-circuit capacity of the SiC MOSFET is improved, the combined action of a reverse bias Schottky junction and the shielding structures is reduced or even eliminated, the extremely strong electric field formed under the JFET region when drain-source voltage occurs is further improved, the source contact can reduce the voltage drop of a body diode, the original body diode is changed into a surge injection structure of a schottky diode, and the surge resistance of the body diode is increased; the opposite area of the gate electrode and the drain electrode is reduced, and the switching loss of the device can be reduced.

Description

Shielding type buried U-groove SIC MOSFET structure for increasing source contact of JFET region

Technical Field

The invention relates to the technical field of on-chip structure improvement of avalanche breakdown resistance and short circuit resistance of SiC MOSFETs, in particular to a shielding buried U-groove SIC MOSFET structure for increasing source contact of a JFET region.

Background

The SiC MOSFET device has the remarkable advantages of high frequency and low loss, and has very wide application in the fields of electric automobiles, photovoltaic inverters, charging piles and the like. However, on one hand, the extremely fast switching speed of the SiC MOSFET causes the problem that the device is extremely easy to generate the overshoot of drain-source voltage in the turn-off process, and particularly, the problem that the SiC MOSFET device is easy to generate short-time avalanche breakdown in the application of an 800V electric drive system and the like, extremely large electrothermal stress is formed near the gate oxide of the SiC MOSFET, and the device performance is easy to be degraded or even damaged in the long-term use process is easy to generate; on the other hand, when the load short circuit occurs in the electric drive system, the short circuit fault occurs in the SiC MOSFET, and the instantaneous high-voltage high current is extremely easy to cause the short circuit failure of the device. At present, few methods for simultaneously optimizing avalanche capability and short circuit capability of a SiC MOSFET device are adopted, and most of the methods are still optimized and improved based on single robustness. For example, in the prior art, methods of optimizing P-well doping morphology, optimizing terminal electric field distribution and the like are generally adopted to adjust cell structure parameters, or methods of optimizing driving to prevent device from generating drain-source voltage overshoot and the like in the device turn-off process are adopted to improve SiC MOSFET avalanche capability or inhibit device from generating drain-source voltage overshoot, and methods of shortening JFET region or integrating short-circuit protection function in driving circuit and the like are adopted to improve short-circuit fault ride-through capability of SiC MOSFET in an actual power supply system. These methods generally improve only one robustness of the device and can introduce negative effects on other performance of the device. For example, shortening the JFET width may cause the SiC MOSFET device to increase in specific on-resistance, resulting in increased device on-loss. As shown in fig. 1, the structure of the inverted P-well SiC MOSFET cell is used to enhance the avalanche capability of the device, and as shown in fig. 2, the structure of the SiC MOSFET cell is used to enhance the short circuit capability of the device, which is a narrow JFET region. In addition, much research and development is being paid attention to improving various performances of devices, but many research and development neglects synchronous improvement advantages in terms of device sizes, namely, the size is reduced on traditional devices, or various devices such as avalanche capability, short-circuit protection capability, on-resistance and the like are only researched, which can cause the devices to lose each other, and research and development shows that the research and development is not related to device file wholesale leakage which improves avalanche capability, short-circuit capability and reduces on-resistance and combines smaller cell sizes, and after materials and performances are applied to the limit, in view of performances of the devices, a body diode of the traditional VDMOSFET device mainly consists of PN junctions, and the turn-on voltage of the traditional VDMOSFET device is relatively large. The Crss of the conventional VDMOSFET is also large because of the large facing area of the gate (G-pole) and drain (D-pole). The larger Crss directly leads to larger parameters such as Ciss, coss and the like of the device, thereby increasing the switching loss of the device, and further improving the avalanche capability when the overshoot of drain-source voltage occurs by utilizing new performance improvement instead of simple structure superposition.

Disclosure of Invention

In view of the above, the present invention aims to provide a shielding buried trench U-trench SIC MOSFET structure for increasing source contact of a JFET region, wherein a shielding structure and source contact are added at the bottom and top of the JFET region, and a buried trench U-trench is added at the source region of the device, so that ohmic contact between a P-well and an N-well is required to be simultaneously shorted from horizontal to vertical, thereby reducing the size of a single repeated cell, and the source region is added with the buried trench U-trench structure, so that the source size of the device can be greatly reduced, thereby reducing the size of the whole cell, increasing the current density of the device, and in addition, since dielectric layers at both sides of the gate are laminated and deposited in the buried trench, compared with the U-trench, the breakdown by the gate source voltage due to the single thinness of dielectric layers at the sides of the gate can be avoided, and the device performance is more stable and superior; the added shielding structure is in contact with the source electrode, so that on one hand, the width of the JFET region is greatly shortened at the bottom of the JFET region, the current path width of the device when the device is short-circuited is reduced through a depletion effect at the bottom of the JFET region, the short-circuit saturation current of the device is greatly reduced, and the short-circuit capacity of the SiC MOSFET is further improved; on the other hand, through the combined action of the reverse bias Schottky junction and the shielding structure, the extremely strong electric field formed under the JFET region when the drain-source voltage overshoot occurs is weakened or even eliminated, the avalanche capacity of the device is further improved, the polycrystalline silicon gate at the top end of the JFET region of the VDMOSFET is split by the source contact arrangement, the facing area of the G pole and the D pole is reduced, the Crss of the silicon carbide VDMOSFET is greatly reduced, the voltage drop of the body diode of the SiC MOSFET device is reduced, the body diode of the original structure is changed into the surge injection structure of the existing Schottky diode, and the anti-surge capacity of the body diode is improved; meanwhile, the new structure reduces the opposite area of the gate electrode and the drain electrode, and can reduce the switching loss of the device.

In order to solve the technical problems, the invention provides a shielding buried trench U-groove SIC MOSFET structure for increasing source contact of a JFET region, which comprises a silicon carbide epitaxial layer, P wells which are equidistantly distributed in a well shape through ion implantation and are of a P-type semiconductor, a JFET region is formed between adjacent P wells, the middle part of each P well is formed into P+ of the P-type semiconductor through the same ion implantation with extremely high concentration, two sides of each P+ are formed into N wells of the N-type semiconductor through the ion implantation with extremely high concentration, the N wells are in contact with the P+ and are not close to the side face of each P well, a gate oxide layer is formed above the region, a polycrystalline silicon gate is deposited on the gate oxide layer, a dielectric layer is deposited on the gate oxide layer, the gate oxide layer and the polycrystalline silicon gate are at least extended above the N wells, the silicon carbide epitaxial layer is provided with a source electrode covering the dielectric layer, the lower side of the silicon carbide epitaxial layer is provided with an N substrate, the lower side of the N substrate is provided with a drain electrode, the same structure in a unit range longitudinally corresponding to a polysilicon gate is defined as MOS unit cells for facilitating understanding, the silicon carbide epitaxial layer comprises a plurality of parallel MOS unit cells, a buried trench is etched and drilled on the N well, a U groove is communicated under the buried trench in an etching way, the U groove penetrates through the N well and goes deep into the P well, a metal source electrode is deposited in the U groove, the source electrode is simultaneously shorted with ohmic contacts of the N well and the P well, the dielectric layers of adjacent polysilicon gates are combined and deposited in the buried trench to deeply embed the source electrode, so that the ohmic contacts of the source electrode and the N well and the P well are simultaneously shorted from transverse to longitudinal, the dielectric layers on the side surfaces of the polysilicon gates are simultaneously omitted, the cross section of the JFET region is in a column-shaped outline, the column-shaped outline is at least provided with a thick-diameter section and a thin-diameter section so as to form a shielding structure, the thick-diameter section is in contact with a gate oxide layer of the MOS unit cell, the position of the polysilicon gate on the JFET region is broken so as to form two sections of polysilicon gates, and the source electrode is in direct contact with the JFET region through the two sections of polysilicon gates so as to form a Schottky junction.

In some embodiments, preferably, the large diameter section and the small diameter section are arranged from top to bottom and are communicated sequentially.

In some embodiments, the diameter of the large diameter section and the diameter of the small diameter section are equal and/or the diameter of the large diameter section and the diameter of the small diameter section are unequal.

In some embodiments, preferably, the ion concentration of the thick-diameter section and the thin-diameter section of the JFET region is the same and high.

In some embodiments, the P-well is connected with a corresponding structure outside the JFET region in a mortise-tenon fit manner.

In some embodiments, preferably, the gate oxide layer is also broken by the schottky junction to form a dielectric layer 1 and a dielectric layer 2 respectively located below the two sections of the polysilicon gate, and the dielectric layer is also broken and respectively forms a dielectric layer 1 and a dielectric layer 2 respectively wrapping the two sections of the polysilicon gate.

In some embodiments, the dielectric layer is preferably SiO ₂ 。

In some embodiments, preferably, the ions implanted on the P-well are reverse implanted, i.e., the bottom ion concentration of the P-well is higher than the top ion concentration.

In some embodiments, preferably, the ions implanted in the P-well are Al ions or B ions, the p+ ions are Al ions or B ions with extremely high concentration, and the ions implanted in the N-well are P ions or N ions with extremely high concentration.

Compared with the prior art, the invention has the following advantages:

1. the shielding structure introduced by the invention is directly improved in the JFET region in the SiC MOSFET cell, and has simple structure and easy realization of the process.

2. According to the invention, the shielding structure and the source electrode contact are respectively added at the bottom and the top of the JFET region, and the buried channel U-shaped groove is added in the source electrode region of the device, so that the ohmic contact between the P well and the N well is changed from transverse to longitudinal by introducing the buried channel U-shaped groove structure, the single repeated cell size is reduced, the source electrode size of the device can be greatly reduced by adding the buried channel U-shaped groove structure in the source region, the whole cell size is further reduced, the current density of the device is increased, and in addition, as the dielectric layers at the two sides of the grid electrode are combined and deposited in the buried channel, compared with the U-shaped groove, the breakdown of the grid source voltage caused by the single thin dielectric layer at the side surface of the grid electrode can be avoided, and the device performance is more stable and superior; the added shielding structure is contacted with the source electrode, on one hand, the shielding structure can form a good pinch-off effect by utilizing the JFET of the small-diameter section at the bottom, and the distribution of a strong electric field below the grid oxide is effectively shielded, so that the avalanche capacity of the device is improved. The JFET current channel of the small-diameter section can be greatly depleted under the bias of a high drain source, so that the saturation current when the device is short-circuited is greatly reduced, the internal heat generation and heat accumulation when the device is short-circuited are effectively reduced, and the short-circuit capacity of the device is improved; on the other hand, through the combined action of the reverse bias Schottky junction and the shielding structure, the extremely strong electric field formed under the JFET region when the overshoot of drain-source voltage occurs is weakened or even eliminated, the avalanche capacity of the device is further improved, the Schottky contact terminal is introduced, the Schottky junction formed by the Schottky contact is started first when the body diode is connected with forward voltage, the body diode is conducted, the PN junction diode is started when the voltage is continuously increased, and the resistance is further reduced. The original PN junction part can be used as a surge injection part of the existing body diode, so that the loss of the switch is reduced. The structure is equivalent to changing a body diode of the original structure from a PN junction diode into a Schottky diode with an anti-surge current function, greatly improving the characteristics of the body diode of the device, separating a polysilicon gate of a JFET region, reducing the coverage area of a gate, directly reducing the Crss of the device, further reducing a series of electrical parameter values of Ciss, coss, qg, eon, eoff and the like of the device, enabling the performance of the device to be more excellent, protecting the device from various aspects and improving the practicability of the device in all directions.

3. The JFET region of the shielding structure can further improve the doping concentration of the JFET region of the thick-diameter section below the gate oxide, further reduce the resistance of an accumulation layer of the SiC MOSFET and the JFET resistance, and realize the SiC MOSFET with lower specific on-resistance.

4. The structure of the invention breaks through the difficult problem that the conventional SiC MOSFET has difficult cooperative optimization of the short-circuit capability and the on-resistance, and can greatly improve the comprehensive performance of the device

5. According to the structure, the buried groove U-shaped groove structure is introduced into the MOS cell, so that ohmic contact between the P well and the N well is required to be changed from transverse to longitudinal with short circuit between the P well and the N well, the size of a single repeated cell is reduced, the current density of the device is increased, and in addition, as the dielectric layers on two sides of the grid are combined and deposited into the buried groove, compared with the U-shaped groove, the buried groove U-shaped groove structure can avoid breakdown caused by grid source voltage due to single thin dielectric layer on the side face of the grid, and the device performance is more stable and superior.

Drawings

Fig. 1 is a schematic structural diagram of a conventional SiC MOSFET with a retrograde P-well implant profile.

Fig. 2 is a schematic diagram of a conventional SiC MOSFET structure with a narrow JFET region.

Fig. 3 is a top view of the source region of the two structures of fig. 1 and 2.

Fig. 4 is a schematic diagram of a shielded U-slot SiC MOSFET structure according to the present invention.

Fig. 5 is a schematic view of another structure of the shielding structure of the present invention.

Fig. 6 is a schematic view of another structure of the shielding structure of the present invention.

Fig. 7 is a schematic view of another structure of the shielding structure of the present invention.

Fig. 8 is a schematic view of another structure of the shielding structure of the present invention.

Fig. 9 is a schematic view of another structure of the shielding structure of the present invention.

Detailed Description

In order to facilitate understanding of the technical scheme of the present invention, the following detailed description is made with reference to the accompanying drawings and specific embodiments.

Referring to fig. 4, in this embodiment, a shielded buried channel U-channel SIC MOSFET structure with increased source contact in JFET region of the present invention is illustrated, first a general SIC MOSFET structure comprising a silicon carbide epitaxial layer with P-wells equally spaced in a well shape and being P-type semiconductors by ion implantation, JFET regions being formed between adjacent P-wells, p+ being formed in the middle of the P-well by the same ion implantation of extremely high concentration, two sides of p+ being formed in the P-type semiconductors by ion implantationThe very high concentration ion implantation forms into N-well of N-type semiconductor, N-well contacts P+, N-well is not close to the side of P-well, in the invention, P+ is implanted into Al ion or B ion, N-well is implanted into P ion or N ion, in the embodiment, P-well is implanted into Al ion, N-well is implanted into P ion, and in the invention, P-well is implanted into ion is inverted implantation, namely bottom ion concentration of P-well is higher than top concentration, grid oxygen layer is formed above JFET region, polysilicon grid is deposited on grid oxygen layer, medium layer is deposited on polysilicon grid, grid oxygen layer and polysilicon grid extend at least above N-well, source electrode covering medium layer is deposited on silicon carbide epitaxial layer, in the embodiment, medium layer is SiO ₂ The silicon carbide epitaxial layer has an N substrate on the underside and a drain on the underside, and for ease of understanding the same structure within a unit range vertically corresponding to the polysilicon gate is defined as MOS cells connected in parallel.

The JFET region for the existing SiC MOSFET structure that does not have avalanche breakdown resistance, lower shorting capability, and shorting capability and on-resistance that are difficult to co-optimize is a vertical well of relatively large width. In the invention, firstly, a buried trench is etched on an N well, a U groove is communicated below the buried trench, the U groove penetrates through the N well and goes deep into a P well, a metal source is deposited in the U groove, the source is in short circuit with ohmic contacts of the N well and the P well at the same time, the ohmic contacts of the source and the N well and the P well are in short circuit at the same time, and are changed into a longitudinal direction from a transverse direction, so that the size of a single repeated cell is reduced, the current density is increased, in addition, as compared with the U groove, the breakdown of a grid source voltage due to the fact that a dielectric layer at the side face of the grid is single is avoided, the device performance is more stable and superior, and then the improvement of avalanche capacity, the short circuit capacity and the reduction of on resistance are realized by adding the shielding structure of the SiC MOSFET structure, the cross section of the JFET region is in a column profile, the column profile is provided with at least one thick diameter section and one thin diameter section so as to form a shielding structure, the thick diameter section is contacted with the grid oxide layer of the MOS unit cell, the thick diameter section and the thin diameter section are arranged from top to bottom and are communicated sequentially, namely, no matter how large the connection difference value between the diameters of the thick diameter section and the thin diameter section is, the thick diameter section and the thin diameter section are always communicated continuously, in the invention, the diameter of the thick diameter section and the thin diameter section can be in an equal difference value, namely, can be in a uniformly decreasing shape from top to bottom like a trapezoid shape, or can be in a plurality of vertical columns with steps decreasing from top to bottom, as shown in figures 5 and 6, of course, the invention also considers that the diameter of the thick diameter section and the thin diameter section is in a non-equal difference value, namely, the diameter of the thick diameter section is suddenly changed to the thin diameter section with small diameter, or one section is continuously decreasing, and then the abrupt difference value is relatively large, such as stepped above below an inverted cone or stepped above to below the cone, as shown in fig. 7-9. In addition, in the invention, the part of the polysilicon grid on the GATE is broken to form two sections of polysilicon grids, the polysilicon grids at the two ends are respectively positioned on the corresponding channels to ensure the GATE function, the source electrode is directly contacted with the JFET region through the two sections of polysilicon grids to form a Schottky junction, the GATE oxide layer is broken by the Schottky junction to form the parts below the two sections of polysilicon grids, the dielectric layer is broken and respectively forms the dielectric layer 1 and the dielectric layer 2 which respectively wrap the two sections of polysilicon grids, and the direct contact area of the G electrode and the D electrode is reduced by splitting the polysilicon grid at the top end of the JFET region of the VDMOSFET, so that the Crss of the device is directly reduced, the Ciss, coss, qg, eon, eoff and other series of electrical parameter values of the device are further reduced, the switching loss of the device is further excellent, on the other hand, the Schottky contact is adopted at the top end of the JFET region, the turn-on voltage of the body diode of the silicon carbide MOSFET device can be greatly reduced, and thus the forward voltage drop of the body diode is reduced, and the turn-on resistance of the PN diode is further reduced when the Schottky contact is introduced at the top end of the JFET region, and the forward contact voltage of the Schottky junction is continuously turned on. The original PN junction part can be used as a surge injection part of the existing body diode. The structure is equivalent to changing the body diode of the original structure from a PN junction diode to a Schottky diode with the surge current resistance function, and greatly improves the body diode characteristic of the device, so that the ultra-strong electric field formed under the JFET region when the drain-source voltage overshoot occurs is weakened or even eliminated through the combined action of the reverse-biased Schottky junction and the shielding structure, and the avalanche capacity of the device is improved.

Specifically, the ion concentration corresponding to the thick-diameter section and the thin-diameter section of the JFET region is the same and high.

Specifically, the P-well is connected with the corresponding structure at the outer side of the JFET region in a mortise-tenon fit manner.

Working principle:

when the SiC MOSFET is subjected to avalanche breakdown, the JFET region has extremely high electric field distribution, strong impact ionization is generated in the device under the action of a strong electric field, a large number of electron-hole pairs possibly generate tunneling effect under the action of the electric field to enter gate oxide, and therefore the device is degraded in performance and even damaged due to extremely strong electric heating coupling effect. The structure of the invention introduces a shielding structure at the bottom of the JFET region, can form a good pinch-off effect by utilizing the JFET of the small-diameter section at the bottom, and effectively shields the distribution of a strong electric field below the gate oxide, thereby improving the avalanche capability of the device.

When a short circuit occurs in the SiC MOSFET, a high drain-source bias voltage causes a great saturation current to flow through the inside of the device, so that a great heat accumulation is instantaneously formed in the inside of the device, and further the performance degradation or the direct failure of the device is caused. The shielding structure introduced at the bottom of the JFET region can greatly deplete the JFET current channel of the small-diameter section under high drain-source bias voltage, and greatly reduce the saturation current when the device is in short circuit, so that the heat generation and heat accumulation in the device are effectively reduced, the short circuit capacity of the device is improved, and in addition, the ultra-strong electric field formed under the JFET region when the drain-source voltage overshoot occurs is weakened or even eliminated through the combined action of the reverse-bias Schottky junction and the shielding structure, and the avalanche capacity of the device is further improved.

In addition, the introduced shielding structure can form good shielding protection for the JFET region under the gate oxide, so that the doping concentration of the JFET region under the gate oxide can be further improved, the resistance of an accumulation layer of the SiC MOSFET and the JFET resistance are further reduced, and the SiC MOSFET with lower specific on resistance is realized.

Meanwhile, when the JFET region is in operation, a Schottky contact terminal is introduced into the JFET region, when the body diode is connected with forward voltage, the Schottky junction formed by the Schottky contact is started first, the body diode is conducted, when the voltage is continuously increased, the PN junction diode is started, the resistance is further reduced, and the original PN junction part can be used as a surge injection part of the existing body diode.

The foregoing is merely a preferred embodiment of the present invention, and the scope of the invention is defined by the claims, and those skilled in the art should also consider the scope of the present invention without departing from the spirit and scope of the invention.

Claims

1. A shielding type buried U-groove SIC MOSFET structure for increasing source contact of JFET region comprises a silicon carbide epitaxial layer, P wells which are equidistantly distributed on the silicon carbide epitaxial layer through ion implantation and are of P-type semiconductor, JFET regions are formed between adjacent P wells, P+ is formed in the middle of the P well through the same ion implantation with extremely high concentration to be P+ of the P-type semiconductor, N wells are formed on two sides of the P+ through ion implantation with extremely high concentration to be N-type semiconductor, the N wells are in contact with the P+ and are not close to the side face of the P well, a gate oxide layer is formed above the JFET regions, a polysilicon gate is deposited on the gate oxide layer, a dielectric layer is deposited on the polysilicon gate, the gate oxide layer and the polysilicon gate extend at least to be positioned above the N wells, a source electrode covering the dielectric layer is deposited on the silicon carbide epitaxial layer, the silicon carbide epitaxial layer is provided with an N substrate at the lower side, a drain electrode is arranged at the lower side of the N substrate, the same structure in a unit range longitudinally corresponding to a polysilicon gate is defined as the MOS unit cell for the convenience of understanding, the MOS unit cell comprises a plurality of MOS unit cells connected in parallel, the silicon carbide epitaxial layer is characterized in that a buried trench is etched on the N well, a U groove is communicated with the lower side of the buried trench in an etching way, the U groove penetrates through the N well and goes deep into the P well, a metal source electrode is deposited in the U groove and is in short circuit with the ohmic contact of the N well and the P well, a dielectric layer of the adjacent polysilicon gate electrode is merged and deposited into the buried groove to deeply embed the source electrode, so that the ohmic contact of the source electrode and the N well and the P well is simultaneously in short circuit and is changed from transverse direction to longitudinal direction, a dielectric layer on the side surface of the polysilicon gate electrode is omitted, the cross section of the JFET region is in a column-shaped profile, the column profile is provided with at least one thick-diameter section and one thin-diameter section to form a shielding structure, the thick-diameter section is in contact with the gate oxide layer of the MOS unit cell, the position of the polysilicon gate on the JFET region is broken to form two sections of polysilicon gates, and the source electrode is in direct contact with the JFET region through the two sections of polysilicon gates to form a Schottky junction.

2. The shielded buried trench U-channel SIC MOSFET structure of claim 1 wherein said large diameter section and said small diameter section are disposed from top to bottom and are in sequential communication.

3. The shielded buried trench U-channel SIC MOSFET structure of claim 1, wherein the diameter of the thick-diameter section and the diameter of the thin-diameter section are of equal magnitude and/or the diameter of the thick-diameter section and the diameter of the thin-diameter section are of unequal magnitude.

4. The shielded buried trench U-channel SIC MOSFET structure of claim 1 in which the JFET region source contact is increased, wherein the JFET region has a high concentration and the large and small diameter sections have the same ion concentration.

5. The shielded buried trench U-channel SIC MOSFET structure of claim 1 in which the P-well is in mortise-tenon fit connection with a corresponding structure outside the JFET region.

6. The shielded buried channel U-channel SIC MOSFET structure of claim 1, wherein said gate oxide layer is also interrupted by said schottky junction to form dielectric layers 1 and 2 respectively surrounding said polysilicon gates respectively under said polysilicon gates of both segments, said dielectric layers being also interrupted.

7. The shielded buried channel U-channel SIC MOSFET structure of claim 1 wherein said dielectric layer is SiO ₂ 。

8. The shielded buried-trench U-channel SIC MOSFET structure of claim 1 in which the source contact of the JFET region is increased, wherein the implanted ions on the P-well are reverse implanted, i.e., the bottom ion concentration of the P-well is higher than the top ion concentration.

9. The shielded buried channel U-channel SIC MOSFET structure of claim 1, wherein the P-well implanted ions are Al or B ions, the p+ implant is a very high concentration of Al or B ions, and the N-well implanted ions are a very high concentration of P or N ions.