CN117712176A - Shielded well groove SiC VDMOSFET structure with hexagonal low body diode voltage drop - Google Patents

Shielded well groove SiC VDMOSFET structure with hexagonal low body diode voltage drop Download PDF

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CN117712176A
CN117712176A CN202410025590.7A CN202410025590A CN117712176A CN 117712176 A CN117712176 A CN 117712176A CN 202410025590 A CN202410025590 A CN 202410025590A CN 117712176 A CN117712176 A CN 117712176A
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well
sic
body diode
diameter section
hexagonal
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许一力
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Beijing Qingxin Micro Energy Storage Technology Co ltd
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Beijing Qingxin Micro Energy Storage Technology Co ltd
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode

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Abstract

The invention discloses a shielded well groove SiC VDMOSFET structure with a hexagonal low body diode voltage drop, which comprises a plurality of hexagonal MOS cells connected in parallel, wherein well grooves are introduced into the hexagonal MOS cells, the size of a single repeated cell is reduced, the current density is increased, source electrode contact is added at the top of a JFET region, the opposite parts of a grid electrode and a drain electrode are eliminated, the grid-drain capacitance is greatly reduced, the body diode voltage drop of a SiC MOSFET device is directly reduced, the body diode of the original structure is changed into the surge injection structure of the traditional Schottky diode, and the surge resistance of the body diode is improved; and a shielding structure is added at the bottom of the JFET region, so that the current path width of the device when the device is short-circuited is reduced through a depletion effect at the bottom of the JFET region, the short-circuit saturation current of the device is greatly reduced, and the short-circuit capacity of the SiC MOSFET is further improved.

Description

Shielded well groove SiC VDMOSFET structure with hexagonal low body diode voltage drop
Technical Field
The invention relates to the technical field of on-chip structure improvement of avalanche breakdown resistance and short circuit resistance of SiC MOSFETs, in particular to a shielding type well SiC VDMOSFET structure with a hexagonal low body diode voltage drop.
Background
The SiC MOSFET device has the remarkable advantages of high frequency and low loss, and has very wide application in the fields of electric automobiles, photovoltaic inverters, charging piles and the like. Nevertheless, the continued development of SiC MOSFETs still requires faster switching speeds in order to allow higher switching frequencies, lower gate drain capacitance to reduce switching losses, and smaller cell sizes to reduce the on-resistance of the same size devices.
However, on one hand, the extremely fast switching speed of the SiC MOSFET causes the problem that the device is extremely easy to generate the overshoot of the drain-source voltage in the turn-off process; on the other hand, when the load short circuit occurs in the electric drive system, the short circuit fault occurs in the SiC MOSFET, and the instantaneous high-voltage high current is extremely easy to cause the short circuit failure of the device.
At present, few methods for simultaneously optimizing avalanche capability and short circuit capability of a SiC MOSFET device are adopted, and most of the methods are still optimized and improved based on single robustness. For example, methods of optimizing P-well doping morphology, optimizing terminal electric field distribution and the like for adjusting cell structure parameters are generally adopted, or methods of optimizing driving to prevent device from generating drain-source voltage overshoot and the like in the device turn-off process are adopted to improve the avalanche capability of the SiC MOSFET or inhibit device from generating drain-source voltage overshoot, and methods of shortening a JFET region or integrating a short-circuit protection function in a driving circuit and the like are adopted to improve the short-circuit fault ride-through capability of the SiC MOSFET in an actual power supply system. These methods generally improve only one robustness of the device and can introduce negative effects on other performance of the device. For example, shortening the JFET width may cause the SiC MOSFET device to increase in specific on-resistance, resulting in increased device on-loss. The inverted P-well SiC MOSFET cell structure used to enhance the avalanche capability of the device is shown in fig. 1, and the narrow JFET region SiC MOSFET cell structure used to enhance the shorting capability of the device is shown in fig. 2.
The structure has no intrinsic pertinence to the gate-drain capacitance and the on-resistance of the device, and the narrow JFET region is designed, so that although the gate-drain capacitance of a single cell is reduced due to the reduction of the JFET region of the single cell, the on-resistance of the device is sacrificed, and whether the overall gate-drain capacitance is reduced or not is considered when a large number of cells form the device with the same on-resistance.
Disclosure of Invention
In view of the above, the present invention aims to provide a shielded well groove SiC VDMOSFET structure with a hexagonal low body diode voltage drop, which reduces the area occupation ratio of a source region in a device by changing a cell from a long strip shape to a hexagonal shape, and simultaneously etches a well groove in the source region, changes the ohmic contact from a transverse direction to a longitudinal direction, reduces the cell size of the device, and increases the current density of the device; the source electrode contact is added at the top of the JFET region, the opposite parts of the grid electrode and the drain electrode are eliminated, the grid-drain capacitance is greatly reduced, the voltage drop of the body diode of the SiC MOSFET device is directly reduced, the body diode of the original structure is changed into the surge injection structure of the existing Schottky diode, and the anti-surge capacity of the body diode is improved; and a shielding structure is added at the bottom of the JFET region, so that the current path width of the device when the device is short-circuited is reduced through a depletion effect at the bottom of the JFET region, the short-circuit saturation current of the device is greatly reduced, and the short-circuit capacity of the SiC MOSFET is further improved. In addition, through the combined action of the reverse-biased Schottky junction and the shielding structure, the extremely strong electric field formed under the JFET region when the drain-source voltage overshoot occurs can be weakened or even eliminated, the avalanche capacity of the device is improved, and the JFET region can be well protected, so that the doping concentration of the JFET region can be greatly improved, the JFET resistance is reduced, and the problem that the on-resistance and the short-circuit capacity of the device are difficult to cooperatively improve in the conventional SiC MOSFET structure optimization is solved.
In order to solve the technical problems, the invention provides a shielding type well groove SiC VDMOSFET structure with a hexagonal low body diode voltage drop, which comprises a silicon carbide epitaxial layer, P wells which are equidistantly distributed in a well shape through ion implantation and are of a P type semiconductor are formed between adjacent P wells, JFET regions are formed between the adjacent P wells, the middle part of each P well is formed into P+ of the P type semiconductor through the same ion implantation with extremely high concentration, N wells which are formed into N type semiconductor are contacted with the P+ through the ion implantation with extremely high concentration are formed at two sides of each P+ respectively, the N wells are not close to the side face of each P well, a grid oxide layer is formed above the grid oxide layer, a polycrystalline silicon grid electrode is deposited on the grid oxide layer, a medium layer is deposited on the grid electrode, the grid oxide layer and the polycrystalline silicon grid electrode are at least extended to be positioned above the N wells, the silicon carbide epitaxial layer is provided with a source electrode covering the dielectric layer, the lower side of the silicon carbide epitaxial layer is provided with an N substrate, the lower side of the N substrate is provided with a drain electrode, for the convenience of understanding, the same structure in a unit range longitudinally corresponding to a polysilicon gate is defined as a hexagonal MOS cell, the silicon carbide epitaxial layer comprises a plurality of parallel hexagonal MOS cells, the overlooking structure of the hexagonal MOS cells is regular hexagon, six sides of the hexagonal MOS cells are distributed at adjacent positions, at least one side of the adjacent hexagonal MOS cells is parallel, a well slot is etched and drilled on the N well, the well slot penetrates through the N well and extends into the P well, a source electrode of metal is deposited in the well slot, the source electrode is simultaneously shorted with ohmic contacts of the N well and the P well, so that the ohmic contacts of the source electrode and the N well and the P well are simultaneously shorted from transverse to longitudinal, the cross section of the JFET region is in a column-shaped outline, the column-shaped outline is at least provided with a thick-diameter section and a thin-diameter section so as to form a shielding structure, the thick-diameter section is in contact with a gate oxide layer of the hexagonal MOS unit cell, the position of the polysilicon gate on the JFET region is broken so as to form two sections of polysilicon gates, and the source electrode is in direct contact with the JFET region through the two sections of polysilicon gates so as to form a Schottky junction.
In some embodiments, preferably, the large diameter section and the small diameter section are arranged from top to bottom and are communicated sequentially.
In some embodiments, the diameter of the large diameter section and the diameter of the small diameter section are equal and/or the diameter of the large diameter section and the diameter of the small diameter section are unequal.
In some embodiments, preferably, the ion concentration of the thick-diameter section and the thin-diameter section of the JFET region is the same and high.
In some embodiments, the P-well is connected with a corresponding structure outside the JFET region in a mortise-tenon fit manner.
In some embodiments, the dielectric layer is preferably SiO 2 。
In some embodiments, preferably, the gate oxide layer is also broken by the schottky junction to form a dielectric layer 1 and a dielectric layer 2 respectively located below the two sections of the polysilicon gate, and the dielectric layer is also broken and respectively forms a dielectric layer 1 and a dielectric layer 2 respectively wrapping the two sections of the polysilicon gate.
In some embodiments, preferably, the ions implanted on the P-well are reverse implanted, i.e., the bottom ion concentration of the P-well is higher than the top ion concentration.
In some embodiments, preferably, the ions implanted in the P-well are Al ions or B ions, the p+ ions are Al ions or B ions with extremely high concentration, and the ions implanted in the N-well are P ions or N ions with extremely high concentration.
Compared with the prior art, the invention has the following advantages:
1. the shielding structure and the source electrode contact introduced by the invention are directly improved and formed in the JFET region in the SiC MOSFET cell, and the structure is simple, and the process is easy to realize.
2. According to the invention, the cell is changed from a strip shape into a hexagon, so that the area ratio of a source region in the device is reduced, and meanwhile, a well groove is etched in the source region, the ohmic contact is changed from the transverse direction to the longitudinal direction, the cell size of the device is reduced, and the current density of the device is increased; the source electrode contact is added at the top of the JFET region, the opposite parts of the grid electrode and the drain electrode are eliminated, the grid-drain capacitance is greatly reduced, the voltage drop of the body diode of the SiC MOSFET device is directly reduced, the body diode of the original structure is changed into the surge injection structure of the existing Schottky diode, and the anti-surge capacity of the body diode is improved; and a shielding structure is added at the bottom of the JFET region, so that the current path width of the device when the device is short-circuited is reduced through a depletion effect at the bottom of the JFET region, the short-circuit saturation current of the device is greatly reduced, and the short-circuit capacity of the SiC MOSFET is further improved. In addition, through the combined action of the reverse-biased Schottky junction and the shielding structure, the extremely strong electric field formed under the JFET region when the drain-source voltage overshoot occurs can be weakened or even eliminated, the avalanche capacity of the device is improved, and the JFET region can be well protected, so that the doping concentration of the JFET region can be greatly improved, the JFET resistance is reduced, and the problem that the on-resistance and the short-circuit capacity of the device are difficult to cooperatively improve in the conventional SiC MOSFET structure optimization is solved.
3. The JFET region of the shielding structure can further improve the doping concentration of the JFET region of the thick-diameter section below the gate oxide, further reduce the resistance of an accumulation layer of the SiC MOSFET and the JFET resistance, and realize the SiC MOSFET with lower specific on-resistance.
4. The structure of the invention breaks through the difficult problem that the conventional SiC MOSFET has difficult cooperative optimization of the short-circuit capability and the on-resistance, and can greatly improve the comprehensive performance of the device
5. According to the structure, the well groove structure is introduced into the hexagonal MOS cell, so that ohmic contact between the P well and the N well is required to be changed from transverse short circuit to longitudinal short circuit between the P well and the N well, the size of a single repeated cell is reduced, the current density of the device is increased, the shielding structure is introduced into the JFET region at the bottom of the side face of the P well on the SiC MOSFET of the hexagonal cell, the area occupation ratio of the source region is reduced, the current density of the device is increased, and the on-resistance is further reduced.
6. The source electrode contact arrangement also breaks the polysilicon gate at the top end of the JFET region of the VDMOSFET, reduces the facing area of the G electrode and the D electrode, greatly reduces Crss, ciss, coss, on loss Eon, off loss Eoff, qg and Qgd of the silicon carbide VDMOSFET, reduces the voltage drop of the body diode of the SiC MOSFET device, changes the body diode with the original structure into the surge injection structure of the traditional Schottky diode, and increases the surge resistance of the body diode; meanwhile, the new structure reduces the opposite area of the gate electrode and the drain electrode, and can reduce the switching loss of the device.
Drawings
Fig. 1 is a schematic structural diagram of a conventional SiC MOSFET with a retrograde P-well implant profile.
Fig. 2 is a schematic diagram of a conventional SiC MOSFET structure with a narrow JFET region.
Fig. 3 is a top view of the source region of the two structures of fig. 1 and 2.
Fig. 4 is a schematic top view and cross-sectional structure of a six-sided shielded well SiC MOSFET of the present invention.
Fig. 5 is a schematic diagram of a cross-sectional structure of a six-sided shielded well SiC MOSFET of the present invention.
Fig. 6 is a schematic top view of a six-sided shielded well SiC MOSFET of the present invention.
Fig. 7 is a schematic view of another structure of the shielding structure of the present invention.
Fig. 8 is a schematic view of another structure of the shielding structure of the present invention.
Fig. 9 is a schematic view of another structure of the shielding structure of the present invention.
Fig. 10 is a schematic view of another structure of the shielding structure of the present invention.
Fig. 11 is a schematic view of another structure of the shielding structure of the present invention.
Detailed Description
In order to facilitate understanding of the technical scheme of the present invention, the following detailed description is made with reference to the accompanying drawings and specific embodiments.
Referring to fig. 4-6, a six-sided low body diode drop shielded well channel SiC VDMOSFET structure of the present invention is illustrated in this embodiment, and first a general SiC MOSFET structure includes a silicon carbide epitaxial layer, P-wells which are equidistantly distributed in a well shape and are P-type semiconductors by ion implantation on the silicon carbide epitaxial layer, JFET regions are formed between adjacent P-wells, P + is formed in the middle of the P-well by the same ion implantation of extremely high concentration, N-wells are formed in N-type semiconductors by ion implantation of extremely high concentration on both sides of the P +, the N-wells are in contact with the P + and the N-wells are not close to the sides of the P-well, and in the present invention, the ions implanted in the P-wells are Al ions or B ions, the p+ implant is an extremely high concentration of Al or B ions, the N-well implant is an extremely high concentration of P or N ions, in this embodiment the P-well implant is Al ions, the N-well implant is an extremely high concentration of P ions, and in the present invention the implant on the P-well is an inverted implant, i.e. the bottom ion concentration of the P-well is higher than the top concentration, the JFET region is formed with a gate oxide layer over which a polysilicon gate is deposited, a dielectric layer is deposited over the polysilicon gate, the gate oxide layer and polysilicon gate extend at least over the N-well, and a source overlying the dielectric layer is deposited over the silicon carbide epitaxial layer, in this embodiment the dielectric layer is SiO 2 The silicon carbide epitaxial layer is provided with an N substrate at the lower side, a drain electrode is arranged below the N substrate, the same structure in a unit range longitudinally corresponding to the polysilicon gate is defined as hexagonal MOS unit cells for convenience of understanding, the hexagonal MOS unit cells are connected in parallel, in the invention, the hexagonal MOS unit cells are in a regular hexagon overlooking structure, hexagonal MOS unit cells are distributed at the adjacent positions of six sides of the hexagonal MOS unit cells, and at least one side of the adjacent hexagonal MOS unit cells are parallel.
The JFET region for the existing SiC MOSFET structure that does not have avalanche breakdown resistance, lower shorting capability, and shorting capability and on-resistance that are difficult to co-optimize is a vertical well of relatively large width. In the invention, firstly, a well groove is etched on an N well, the well groove penetrates through the N well and goes deep into a P well, a metal source electrode is deposited in the well groove, the source electrode is in short circuit with the ohmic contacts of the N well and the P well at the same time, so that the ohmic contacts of the source electrode and the N well and the P well are in short circuit at the same time, the size of a single repeated cell is reduced, the current density is further increased, then the avalanche capacity, the short circuit capacity and the conduction resistance are improved by adding the shielding structure into the SiC MOSFET structure, the cross section of the JFET region is in a column-shaped profile, the column-shaped profile is at least provided with a thick-diameter section and a thin-diameter section to form the shielding structure, the thick-diameter section is in contact with a gate oxide layer of the hexagonal MOS cell, the diameter of the thick diameter section and the diameter of the thin diameter section are arranged from top to bottom and are sequentially communicated, namely, no matter how large the connection difference value between the diameters of the thick diameter section and the thin diameter section is, the diameter of the thick diameter section and the diameter of the thin diameter section are always continuously communicated, in the invention, the thick diameter section and the diameter of the thin diameter section can be uniformly reduced from top to bottom like a trapezoid shape, or can be a plurality of vertical columns with steps reduced from top to bottom like a trapezoid shape, as shown in figures 7 and 8, of course, the invention also considers that the diameters of the thick diameter section and the thin diameter section are non-uniform, namely, the diameter of the thick diameter section is a thin diameter section with a very large diameter suddenly changed to a very small diameter, or the diameter of one section is continuously reduced and then the abrupt change difference value is relatively large, as shown in figures 9-11. In addition, in the invention, the part of the polysilicon grid on the GATE is broken to form two sections of polysilicon grids, the polysilicon grids at the two ends are respectively positioned on the corresponding channels to ensure the GATE function, the source electrode is directly contacted with the JFET region through the two sections of polysilicon grids to form a Schottky junction, the GATE oxide layer is broken by the Schottky junction to form the parts below the two sections of polysilicon grids, the dielectric layer is broken and respectively forms the dielectric layer 1 and the dielectric layer 2 which respectively wrap the two sections of polysilicon grids, and the direct contact area of the G electrode and the D electrode is reduced by splitting the polysilicon grid at the top end of the JFET region of the VDMOSFET, so that the Crss of the device is directly reduced, the Ciss, coss, qg, eon, eoff and other series of electrical parameter values of the device are further reduced, the switching loss of the device is further excellent, on the other hand, the Schottky contact is adopted at the top end of the JFET region, the turn-on voltage of the body diode of the silicon carbide MOSFET device can be greatly reduced, and thus the forward voltage drop of the body diode is reduced, and the turn-on resistance of the PN diode is further reduced when the Schottky contact is introduced at the top end of the JFET region, and the forward contact voltage of the Schottky junction is continuously turned on. The original PN junction part can be used as a surge injection part of the existing body diode. The structure is equivalent to changing a body diode of an original structure from a PN junction diode into a Schottky diode with an anti-surge current function, and greatly improves the body diode characteristic of the device, so that the extremely strong electric field formed under a JFET region when the drain-source voltage overshoots occur is weakened or even eliminated through the combined action of the reverse-bias Schottky junction and a shielding structure, the avalanche capacity of the device is improved, and finally, the extremely strong electric field formed under the JFET region when the drain-source voltage overshoots occur can be weakened or even eliminated through the combined action of the reverse-bias Schottky junction and the shielding structure, the avalanche capacity of the device is improved, and good protection can be formed for the JFET region, so that the doping concentration of the JFET region can be greatly improved, the resistance is reduced, and the problem that the on-resistance and the short-circuit capacity of the device are difficult to cooperatively improve in the structural optimization of a conventional SiC JFET MOSFET is broken through.
Specifically, the ion concentration corresponding to the thick-diameter section and the thin-diameter section of the JFET region is the same and high.
Specifically, the P-well is connected with the corresponding structure at the outer side of the JFET region in a mortise-tenon fit manner.
Working principle:
when the SiC MOSFET is subjected to avalanche breakdown, the JFET region has extremely high electric field distribution, strong impact ionization is generated in the device under the action of a strong electric field, a large number of electron-hole pairs possibly generate tunneling effect under the action of the electric field to enter gate oxide, and therefore the device is degraded in performance and even damaged due to extremely strong electric heating coupling effect. The structure of the invention introduces a shielding structure at the bottom of the JFET region, can form a good pinch-off effect by utilizing the JFET of the small-diameter section at the bottom, and effectively shields the distribution of a strong electric field below the gate oxide, thereby improving the avalanche capability of the device.
When a short circuit occurs in the SiC MOSFET, a high drain-source bias voltage causes a great saturation current to flow through the inside of the device, so that a great heat accumulation is instantaneously formed in the inside of the device, and further the performance degradation or the direct failure of the device is caused. The shielding structure introduced at the bottom of the JFET region can greatly deplete the JFET current channel of the small-diameter section under high drain-source bias voltage, and greatly reduce the saturation current when the device is in short circuit, thereby effectively reducing the internal heat generation and heat accumulation when the device is in short circuit and improving the short circuit capacity of the device.
The reverse bias Schottky junction and the shielding structure act together, so that an extremely strong electric field formed under the JFET region when the overshoot of drain-source voltage occurs can be weakened or even eliminated, and the avalanche capacity of the device is further improved.
In addition, the introduced shielding structure can form good shielding protection for the JFET region below the gate oxide, so that the doping concentration of the JFET region below the gate oxide can be further improved, the resistance of an accumulation layer of the SiC MOSFET and the JFET resistance are further reduced, the SiC MOSFET with lower specific on-resistance is realized, the hexagonal cell structure is adopted, the area occupation ratio of a source region is reduced, the current density of a device is increased, and the on-resistance is further reduced.
The foregoing is merely a preferred embodiment of the present invention, and the scope of the invention is defined by the claims, and those skilled in the art should also consider the scope of the present invention without departing from the spirit and scope of the invention.

Claims (9)

1. A shielded well groove SiC VDMOSFET structure with a hexagonal low body diode voltage drop comprises a silicon carbide epitaxial layer, P wells which are equidistantly distributed on the silicon carbide epitaxial layer through ion implantation and are of P-type semiconductors, JFET regions are formed between adjacent P wells, P+ of the P-type semiconductors is formed in the middle of the P wells through the same ion implantation with extremely high concentration, N wells are formed on two sides of the P+ through the ion implantation with extremely high concentration and are in contact with the P+, the N wells are not close to the side face of the P wells, a gate oxide layer is formed above the JFET regions, a polysilicon gate is deposited on the gate oxide layer, a dielectric layer is deposited on the polysilicon gate, the gate oxide layer and the polysilicon gate extend at least to be positioned above the N wells, a source electrode covering the dielectric layer is deposited on the silicon carbide epitaxial layer, the silicon carbide epitaxial layer is provided with an N substrate at the lower side, a drain electrode is arranged below the N substrate, the same structure in a unit range longitudinally corresponding to a polysilicon gate is defined as a hexagonal MOS cell for facilitating understanding, the silicon carbide epitaxial layer is characterized in that the hexagonal MOS cell is in a regular hexagon overlooking structure, six sides of the hexagonal MOS cell are distributed with the hexagonal MOS cell in adjacent positions, at least one side of the adjacent hexagonal MOS cell is parallel, a well slot is etched on the N well, the well slot penetrates through the N well and extends into the P well, a metal source electrode is deposited in the well slot, the source electrode is simultaneously shorted with the ohmic contacts of the N well and the P well, the ohmic contacts of the source electrode and the N well and the P well are simultaneously shorted from transverse to longitudinal, the cross section of the area is in a column-shaped JFET, the column profile is provided with at least one thick-diameter section and one thin-diameter section to form a shielding structure, the thick-diameter section is in contact with the gate oxide layer of the hexagonal MOS cell, the position of the polysilicon gate on the JFET region is broken to form two sections of polysilicon gates, and the source electrode is in direct contact with the JFET region through the two sections of polysilicon gates to form a Schottky junction.
2. The shielded well-trench SiC VDMOSFET structure of claim 1 wherein said large diameter section and said small diameter section are arranged from top to bottom and communicate sequentially.
3. A six sided low body diode drop shielded well SiC VDMOSFET structure according to claim 1 wherein the diameter of the large diameter section and the small diameter section are of equal differential value and/or the diameter of the large diameter section and the small diameter section are of unequal differential value.
4. The six sided low body diode drop shielded well channel SiC VDMOSFET structure of claim 1 wherein the larger and smaller diameter sections of the JFET region have the same ion concentration and are of high concentration.
5. The shielded well-trench SiC VDMOSFET structure of claim 1 wherein said P-well is in a mortise-tenon fit morphology with a corresponding structure outside of said JFET region.
6. The six sided low body diode drop shielded well channel SiC VDMOSFET structure of claim 1 wherein said gate oxide layer is also broken by said schottky junction to form dielectric layers 1 and 2 respectively surrounding said polysilicon gates of two segments respectively, said dielectric layers being broken.
7. The shielded well-trench SiC VDMOSFET structure of claim 1 wherein said dielectric layer is SiO 2 。
8. The shielded well-trench SiC VDMOSFET structure of claim 1 wherein the ions implanted on said P-well are reverse implanted, i.e., the bottom ion concentration of said P-well is higher than the top ion concentration.
9. The shielded well-trench SiC VDMOSFET structure of claim 1, wherein said P-well implanted ions are Al or B ions, said p+ implant is very high concentration Al or B ions, and said N-well implanted ions are very high concentration P or N ions.
CN202410025590.7A 2024-01-08 2024-01-08 Shielded well groove SiC VDMOSFET structure with hexagonal low body diode voltage drop Pending CN117712176A (en)

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