JP2011258635A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2011258635A
JP2011258635A JP2010129825A JP2010129825A JP2011258635A JP 2011258635 A JP2011258635 A JP 2011258635A JP 2010129825 A JP2010129825 A JP 2010129825A JP 2010129825 A JP2010129825 A JP 2010129825A JP 2011258635 A JP2011258635 A JP 2011258635A
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layer
type
region
drift layer
semiconductor device
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Hiroshi Watanabe
寛 渡邊
Kenichi Otsuka
健一 大塚
Narihisa Miura
成久 三浦
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Abstract

PROBLEM TO BE SOLVED: To achieve reduced channel resistance and improved breakdown voltage of a gate insulating film in a vertical semiconductor device in which p-type semiconductor regions at cell corners are connected to each other.SOLUTION: The semiconductor device comprises: an n-type drift layer 2 formed on a surface of an SiC substrate; a plurality of p-type base layers 3 selectively formed on the surface of the n-type drift layer 2; n-type source regions 4 that are selectively formed on surfaces of the p-type base layers 3, and define the surfaces of the p-type base layers 3 sandwiched between the regions and the n-type drift layer 2 as channel regions; a gate electrode 6 formed over from the channel regions to the n-type drift layer 2 via a gate insulating film 5; and a p-type semiconductor layer 12 formed in such a way that, in a region of the n-type drift layer 2 surrounded by the p-type base layers 3 in a plane view, the p-type semiconductor layer 12 is extended from a predetermined part of the p-type base layers 3 to the center of the region.

Description

この発明は、パワーＭＯＳＦＥＴに関するものである。   The present invention relates to a power MOSFET.

ＳｉＣ基板を用いたパワーＭＯＳＦＥＴでは、例えばｎ型ＳｉＣ基板の表面に複数のセルが縦横に配列される。各セルは基板表層部にｐ型ベース層、さらにその内側の表層部にｎ型ソース層を形成し、その上面にはゲート絶縁膜、ゲート電極およびソース電極、裏面にドレイン電極を形成して作成される。ｎ型半導体基板とｎ型ソース層との間のｐ型ベース層表面をチャネル領域といい、その距離をチャネル長と定義する。チャネル領域のうちｎ型半導体基板とｐ型ベース層との境界の長さ（周囲長）が長いほど、またセルピッチが小さいほど単位面積当たりのチャネル抵抗は減少する。ソース電極はソースコンタクト層を介してｐ型コンタクト層及びｎ型コンタクト層に電気的に接触している。   In a power MOSFET using a SiC substrate, for example, a plurality of cells are arranged vertically and horizontally on the surface of an n-type SiC substrate. Each cell is formed by forming a p-type base layer on the substrate surface layer, an n-type source layer on the inner surface layer, a gate insulating film, a gate electrode and a source electrode on the top surface, and a drain electrode on the back surface. Is done. The surface of the p-type base layer between the n-type semiconductor substrate and the n-type source layer is called a channel region, and the distance is defined as the channel length. In the channel region, the channel resistance per unit area decreases as the boundary length (peripheral length) between the n-type semiconductor substrate and the p-type base layer is longer, and as the cell pitch is smaller. The source electrode is in electrical contact with the p-type contact layer and the n-type contact layer through the source contact layer.

特許文献１には、Ｓｉ基板を用いて製造されたｎ型ＤＭＯＳ（Ｄｏｕｂｌｅ−Ｄｉｆｆｕｓｅｄ ＭＯＳ）素子において、ｐ型用ソースコンタクト部とｎ型用ソースコンタクト部が分離して配置され、セルコーナー部のｐ型半導体領域にｐ型ソースコンタクト部を配置した縦型半導体装置が記載されている。これは、ｐ型ベース層を部分的に接続して１つの連続した領域とし、ソース電極と接続するｐ型ベース層と同一導電型の抜き取り領域を形成することで、寄生トランジスタの動作を抑制し、破壊耐量を向上させる方法として示されている。   In Patent Document 1, in an n-type DMOS (Double-Diffused MOS) device manufactured using a Si substrate, a p-type source contact portion and an n-type source contact portion are arranged separately, and a cell corner portion is formed. A vertical semiconductor device is described in which a p-type source contact portion is disposed in a p-type semiconductor region. This is because the p-type base layer is partially connected to form one continuous region, and the extraction region of the same conductivity type as the p-type base layer connected to the source electrode is formed, thereby suppressing the operation of the parasitic transistor. It is shown as a method of improving the breakdown tolerance.

また、特許文献２には、セルコーナー部が接続されたｐ型半導体領域に第２のチャネル領域を設け、かつ第２のチャネル領域表面にもソース領域とソース電極を設けて第２のセルとしたパワーＭＯＳＦＥＴが記載されている。これは、第２のセルを設けない場合に対して単位面積当たりのチャネル周囲長が長くなり、チャネル抵抗を減少することができる構造として示されている。   Further, in Patent Document 2, a second channel region is provided in a p-type semiconductor region to which a cell corner portion is connected, and a source region and a source electrode are provided on the surface of the second channel region. A power MOSFET is described. This is shown as a structure in which the channel perimeter per unit area becomes longer and the channel resistance can be reduced compared to the case where the second cell is not provided.

特開平５−１０２４８７号公報Japanese Patent Laid-Open No. 5-102487 特開平１−２３８１７３号公報JP-A-1-238173

しかしながら、特許文献１ではセルコーナー部のｐ型半導体領域内にチャネル領域が形成されていない為、ｐ型半導体領域はセルとして機能せず、単位面積当たりのチャネル抵抗が増大するという問題がある。   However, in Patent Document 1, since the channel region is not formed in the p-type semiconductor region at the cell corner, there is a problem that the p-type semiconductor region does not function as a cell and the channel resistance per unit area increases.

また、特許文献２では、互いに接続されたセルコーナー部にチャネル領域が形成された第２のセルが設けられているが、四方がセルで囲まれたｎ型半導体領域のサイズ（長辺と短辺）はセルのサイズとほぼ同じになり、セルのサイズと独立に決定することが出来ない。その結果、セルで囲まれたｎ型半導体領域上（特に、平面視における中央部付近）のゲート絶縁膜に電界集中が生じて、耐圧が低下するという課題がある。   Further, in Patent Document 2, a second cell in which a channel region is formed in a cell corner portion connected to each other is provided. However, the size (long side and short side) of an n-type semiconductor region surrounded on all four sides by the cell. (Side) is almost the same as the cell size and cannot be determined independently of the cell size. As a result, there is a problem in that electric field concentration occurs in the gate insulating film on the n-type semiconductor region surrounded by the cells (particularly, in the vicinity of the central portion in plan view), and the breakdown voltage decreases.

本発明は、上述の問題点に鑑みてなされたものであり、セルコーナー部のｐ型半導体領域が互いに接続された縦型の半導体装置において、チャネル抵抗の低減とゲート絶縁膜の絶縁破壊電圧の向上を両立することを目的としている。   The present invention has been made in view of the above-described problems, and in a vertical semiconductor device in which the p-type semiconductor regions at the cell corners are connected to each other, the channel resistance is reduced and the breakdown voltage of the gate insulating film is reduced. The aim is to achieve both improvements.

本発明の半導体装置は、ＳｉＣ基板表面に形成された第１導電型のドリフト層と、ドリフト層表面に選択的に複数形成された、第２導電型のベース層と、ベース層表面に選択的に形成された領域であって、当該領域とドリフト層とで挟まれたベース層表面をチャネル領域として規定する第１導電型のソース領域と、チャネル領域上からドリフト層上に渡って、絶縁膜を介して形成されたゲート電極と、平面視でベース層に囲まれたドリフト層の領域において、当該領域の中心部と前記ベース層とを繋ぐ第２導電型の第１半導体層と、を備える。   The semiconductor device of the present invention includes a first conductivity type drift layer formed on the surface of the SiC substrate, a plurality of second conductivity type base layers selectively formed on the drift layer surface, and selective on the surface of the base layer. A source region of a first conductivity type that defines a base layer surface sandwiched between the region and the drift layer as a channel region, and an insulating film extending from the channel region to the drift layer And a first conductive semiconductor layer of a second conductivity type that connects the center of the region and the base layer in the region of the drift layer surrounded by the base layer in plan view. .

本発明の半導体装置は、平面視でベース層に囲まれたドリフト層の領域において、当該領域の中心部と前記ベース層とを繋ぐ第２導電型の第１半導体層を備えるため、ゲート絶縁膜の絶縁破壊電圧が向上する。   Since the semiconductor device of the present invention includes the first semiconductor layer of the second conductivity type that connects the center of the region and the base layer in the region of the drift layer surrounded by the base layer in plan view, the gate insulating film Improves the dielectric breakdown voltage.

本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す断面図である。It is sectional drawing which shows the SiC semiconductor device which concerns on this invention. 本発明に係るＳｉＣ半導体装置を示す平面図である。It is a top view which shows the SiC semiconductor device which concerns on this invention.

（実施の形態１）
＜構成＞
本実施の形態の半導体装置であるＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）の断面図を図１５に、平面図を図１〜図７に示す。図１はＭＯＳＦＥＴの表面パターンを示す平面図であり、図２〜図７は図１の平面図と同位置における異なる層のパターンを示している。図１５（ａ）は、図１のＡ−Ａ’断面図であり、図１５（ｂ）は図１のＢ−Ｂ’断面図である。 (Embodiment 1)
<Configuration>
FIG. 15 is a sectional view of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is a semiconductor device of the present embodiment, and FIGS. FIG. 1 is a plan view showing a surface pattern of a MOSFET, and FIGS. 2 to 7 show patterns of different layers at the same position as the plan view of FIG. 15A is a cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 15B is a cross-sectional view taken along the line BB ′ in FIG.

図１５に示すように、ＭＯＳＦＥＴは、高濃度のｎ型不純物を含むｎ＋型ドレイン層１ａとｎ＋型ドレイン層１ａ上に形成される比較的低濃度のｎ−型ドリフト層２からなるＳｉＣ基板１を備える。さらに、ｎ−型ドリフト層２の表層部に形成されるｐ型ベース層３と、ｐ型ベース層３の表層部で、その外周部から所定距離だけ離れた内側に形成されるｎ＋型ソース層４（図４参照）と、ｎ＋型ソース層４を貫通してｐ型ベース層３と接触するｐ＋型コンタクト層１３とを備える。ｐ＋型コンタクト層１３はｐ型ベース層３よりも高いｐ型不純物濃度を有する。ｐ型ベース層３、ｎ＋型ソース層４、ｐ＋型コンタクト層１３が形成される領域がセル領域となり、図１に示すようにセル領域はＳｉＣ基板１上に複数形成される。図２に示すように、ｐ型ベース層３はｎ−型ドリフト層２上に、角部を互いに接続した千鳥格子状に配設される。図６に示すように、ｐ＋型コンタクト層１３はｎ＋型ソース層４に囲まれるように形成される。   As shown in FIG. 15, the MOSFET includes an SiC substrate 1 comprising an n + type drain layer 1a containing a high concentration n-type impurity and a relatively low concentration n− type drift layer 2 formed on the n + type drain layer 1a. Is provided. Furthermore, the p-type base layer 3 formed in the surface layer portion of the n − -type drift layer 2, and the n + -type source layer formed inside the surface layer portion of the p-type base layer 3 at a predetermined distance from the outer peripheral portion. 4 (see FIG. 4) and a p + -type contact layer 13 that penetrates the n + -type source layer 4 and contacts the p-type base layer 3. The p + -type contact layer 13 has a higher p-type impurity concentration than the p-type base layer 3. A region where the p-type base layer 3, the n + -type source layer 4 and the p + -type contact layer 13 are formed becomes a cell region, and a plurality of cell regions are formed on the SiC substrate 1 as shown in FIG. As shown in FIG. 2, the p-type base layer 3 is disposed on the n − -type drift layer 2 in a staggered pattern with corners connected to each other. As shown in FIG. 6, the p + type contact layer 13 is formed so as to be surrounded by the n + type source layer 4.

ＭＯＳＦＥＴは、４つの格子のｐ型ベース層３に囲まれたｎ−型ドリフト層２の領域において、表面から離間した内部に形成されるｐ型半導体層１２と、表層部に形成されるｎ＋型半導体層１４をさらに備える。ｐ型ベース層３の表面において、ｎ＋型ソース層４とｎ＋型半導体層１４の間の領域がチャネル領域となる。しかし、ｎ＋型半導体層１４を設けない場合には、ｎ＋型ソース層４とｎ−型ドリフト層２の間がチャネル領域となる。ｐ型半導体層１２は図３に示すように、ｐ型ベース層３に囲まれたｎ−型ドリフト層２の領域において、当該領域の中心部とｐ型ベース層３の角部（セルコーナー部）とを線状に繋いでいる。なお、当該領域の中心部はｐ型ベース層３とｐ型半導体層１２によって繋がっていれば良く、図１８に示すように各セルコーナー部の全てと繋がっている必要はない。ｎ＋型半導体層１４は、図５に示すように、ｐ型ベース層３に囲まれたｎ−型ドリフト層２の領域の全面を覆うように形成される。   In the region of the n − type drift layer 2 surrounded by the p type base layer 3 of four lattices, the MOSFET includes a p type semiconductor layer 12 formed inside spaced apart from the surface, and an n + type formed in the surface layer portion. A semiconductor layer 14 is further provided. On the surface of the p-type base layer 3, a region between the n + -type source layer 4 and the n + -type semiconductor layer 14 becomes a channel region. However, when the n + type semiconductor layer 14 is not provided, the channel region is between the n + type source layer 4 and the n − type drift layer 2. As shown in FIG. 3, the p-type semiconductor layer 12 includes a central portion of the region and a corner (cell corner portion) of the p-type base layer 3 in the region of the n − -type drift layer 2 surrounded by the p-type base layer 3. ) In a line. Note that the central portion of the region only needs to be connected by the p-type base layer 3 and the p-type semiconductor layer 12, and does not need to be connected to all the cell corner portions as shown in FIG. As shown in FIG. 5, the n + type semiconductor layer 14 is formed so as to cover the entire surface of the n − type drift layer 2 surrounded by the p type base layer 3.

また、ＭＯＳＦＥＴは、チャネル領域及びｎ−型ドリフト層２上に形成されるゲート絶縁膜５と、ゲート絶縁膜５上に形成されるゲート電極６（図７参照）と、ゲート電極６上に形成される層間絶縁膜７（図１参照）と、ゲート絶縁膜の開口においてｎ＋型ソース層４及びｐ＋型コンタクト層１３にオーミック接続されたソースコンタクト電極９と、層間絶縁膜７上に形成され、且つソースコンタクト電極９を介してｎ＋型ソース層４及びｐ＋型コンタクト層１３とオーミック接続するソース電極８とを備える。   The MOSFET is formed on the channel region and the n − type drift layer 2, the gate electrode 6 (see FIG. 7) formed on the gate insulating film 5, and the gate electrode 6. An interlayer insulating film 7 (see FIG. 1) to be formed, a source contact electrode 9 ohmically connected to the n + type source layer 4 and the p + type contact layer 13 in the opening of the gate insulating film, and the interlayer insulating film 7. The source electrode 8 is ohmically connected to the n + type source layer 4 and the p + type contact layer 13 via the source contact electrode 9.

さらに、ＭＯＳＦＥＴは、ｎ＋型ドレイン層１の裏面に形成されるドレイン電極１１を備える。   Further, the MOSFET includes a drain electrode 11 formed on the back surface of the n + -type drain layer 1.

ＳｉＣ基板１にＳｉ基板を用いる従来の縦型半導体装置では、ｎ−型ドリフト層２の不純物濃度をあげると電界強度が増加してしまうため、ｎ−型ドリフト層２がＳｉＣである縦型半導体装置と比較してｎ−型ドリフト層２の不純物濃度を１／１００程度にする必要がある。この場合、ｎ−型ドリフト層２の抵抗が増加するため、実効的なｎ−型ドリフト層２の抵抗を下げるべくセル領域以外のｎ−型ドリフト層２の単位面積当たりの割合を大きくする必要があった。例えば、セル一辺の長さを数１０μｍ以上にする必要があり、そうしたとしても、セル領域以外のｎ−型ドリフト層２の単位面積当たりの割合を大きくすると、チャネルの周囲長が減少するため十分にチャネル抵抗を下げられないという問題があった。   In a conventional vertical semiconductor device using a Si substrate as the SiC substrate 1, the electric field strength increases when the impurity concentration of the n − type drift layer 2 is increased. Therefore, the vertical semiconductor device in which the n − type drift layer 2 is SiC. Compared to the device, the impurity concentration of the n − type drift layer 2 needs to be about 1/100. In this case, since the resistance of the n − type drift layer 2 increases, it is necessary to increase the ratio per unit area of the n − type drift layer 2 other than the cell region in order to reduce the effective resistance of the n − type drift layer 2. was there. For example, the length of one side of the cell needs to be several tens of μm or more. Even in such a case, if the ratio per unit area of the n − type drift layer 2 other than the cell region is increased, the peripheral length of the channel is sufficiently reduced. However, the channel resistance cannot be lowered.

しかし、本実施の形態ではＳｉＣ基板を用いることによって、ｎ−型ドリフト層２の不純物濃度を上げても絶縁破壊電界強度が確保でき、さらにＳｉを用いた半導体装置では実現できない一辺のサイズが１０μｍ以下のセルにおいて、さらなるチャネル抵抗の低減とゲート絶縁膜の絶縁破壊電圧の向上の両立を目指す。   However, in this embodiment, by using the SiC substrate, the breakdown electric field strength can be secured even if the impurity concentration of the n − type drift layer 2 is increased, and the size of one side that cannot be realized by a semiconductor device using Si is 10 μm. In the following cells, we aim to further reduce the channel resistance and improve the breakdown voltage of the gate insulating film.

＜製法＞
図８〜図１５を用いて、本実施の形態に係る半導体装置の製造工程を説明する。図８（ａ）〜図１５（ａ）は、各製造工程における図１のＡ−Ａ’断面図であり、図８（ｂ）〜図１５（ｂ）は、各製造工程における図１のＢ−Ｂ’断面図である。 <Production method>
A manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. 8A to 15A are cross-sectional views taken along the line AA ′ of FIG. 1 in each manufacturing process, and FIGS. 8B to 15B are views of FIG. It is -B 'sectional drawing.

はじめに、図８に示すように、表層にｎ＋型ドレイン層１ａを含有する炭化珪素基板１を用意し、ｎ＋型ドレイン層１ａの表面上に、厚さ１０μｍでｎ型不純物濃度が１×１０16／ｃｍ3のＳｉＣ層であるｎ−型ドリフト層２をエピタキシャル成長させる。 First, as shown in FIG. 8, a silicon carbide substrate 1 containing an n + -type drain layer 1a as a surface layer is prepared. On the surface of the n + -type drain layer 1a, a thickness of 10 μm and an n-type impurity concentration is 1 × 10 16. An n − type drift layer 2 which is an SiC layer of / cm 3 is epitaxially grown.

次に、ｎ−型ドリフト層２の表面上にフォトリソグラフィを用いて第１レジストパターンを形成した上で、ｐ型の不純物であるＡｌイオンをｎ−型ドリフト層２にイオン注入する（第１イオン注入工程）。   Next, after forming a first resist pattern on the surface of the n − type drift layer 2 using photolithography, Al ions, which are p type impurities, are ion-implanted into the n − type drift layer 2 (first first). Ion implantation step).

このイオン注入により、ｎ−型ドリフト層２の表面側で第１レジストパターンに覆われていない部分にｐ型ベース層３が形成される。この状態を上面から見ると、図２に示すように各セルのｐ型ベース層３の角部が互いに接続された格子状に形成されている。セルのサイズは、例えば正方形のｐ型ベース層３の一辺の長さを９μｍとする。   By this ion implantation, the p-type base layer 3 is formed on the surface of the n − -type drift layer 2 that is not covered with the first resist pattern. When this state is viewed from above, as shown in FIG. 2, the corners of the p-type base layer 3 of each cell are formed in a lattice shape connected to each other. As for the size of the cell, for example, the length of one side of the square p-type base layer 3 is 9 μm.

第１イオン注入工程では、ｎ−型ドリフト層２の表面から深さ０．８μｍまでＡｌイオンの濃度が２×１０18個／ｃｍ3で一定（ボックスプロファイルという）となるようにＡｌイオンを注入する。イオン注入時のＳｉＣ基板１の温度は２５℃とする。 In the first ion implantation step, Al ions are implanted so that the concentration of Al ions is constant at 2 × 10 18 ions / cm 3 from the surface of the n − type drift layer 2 to a depth of 0.8 μm (referred to as a box profile). To do. The temperature of the SiC substrate 1 during ion implantation is set to 25 ° C.

次に、ｎ−型ドリフト層２の主表面上にフォトリソグラフィを用いて第２レジストパターンを形成した上で、ｐ型不純物となるＡｌイオンをｎ−型ドリフト層２にイオン注入する（第２イオン注入工程）。   Next, after forming a second resist pattern on the main surface of the n − -type drift layer 2 using photolithography, Al ions to be p-type impurities are ion-implanted into the n − -type drift layer 2 (second Ion implantation step).

このイオン注入により、図９に示すように、ｎ−型ドリフト層２の表面側で第２レジストパターンに覆われていない部分にｐ型半導体層１２が形成される。この状態を上面から見ると、図３に示すようにｎ−型ドリフト層２の中央部と、隣接するｐ型ベース層３の角部を接続するようにｐ型半導体層１２は形成される。上面から見たｐ型半導体層１２の最小幅は、例えば１μｍとする。   By this ion implantation, as shown in FIG. 9, the p-type semiconductor layer 12 is formed on the surface side of the n − -type drift layer 2 in a portion not covered with the second resist pattern. When this state is viewed from above, the p-type semiconductor layer 12 is formed so as to connect the central portion of the n − -type drift layer 2 and the corner portion of the adjacent p-type base layer 3 as shown in FIG. The minimum width of the p-type semiconductor layer 12 as viewed from above is, for example, 1 μm.

第２イオン注入工程では、ｎ−型ドリフト層２の表面から深さ０．４μｍ〜０．８μｍまでＡｌイオンの濃度が２×１０18個／ｃｍ3で一定となるように、ｎ−型ドリフト層２の表面から離間した内部にＡｌイオンが注入される。イオン注入時のＳｉＣ基板１の温度は２５℃とする。 In the second ion implantation step, the n − type drift is performed so that the concentration of Al ions is constant at 2 × 10 18 ions / cm 3 from the surface of the n − type drift layer 2 to a depth of 0.4 μm to 0.8 μm. Al ions are implanted into the interior away from the surface of the layer 2. The temperature of the SiC substrate 1 during ion implantation is set to 25 ° C.

つづいて、第２レジストパターンを除去した後、上記の過程で形成されたＳｉＣ基板１の主表面上にフォトリソグラフィを用いて第３レジストパターンを形成した上で、ｎ型不純物となる窒素イオンをｐ型ベース層３にイオン注入する（第３イオン注入工程）。   Subsequently, after removing the second resist pattern, a third resist pattern is formed on the main surface of the SiC substrate 1 formed in the above-described process using photolithography, and then nitrogen ions serving as n-type impurities are introduced. Ions are implanted into the p-type base layer 3 (third ion implantation step).

このイオン注入により、図４、図１０に示すようにｐ型ベース層３内にｎ＋型ソース層４が形成される。例えば、ｎ＋型ソース層４の１辺の長さは８μｍとすると、ｐ型ベース層の１辺の長さは９μｍであるからチャネル長は０．５μｍとなる。   By this ion implantation, an n + type source layer 4 is formed in the p type base layer 3 as shown in FIGS. For example, if the length of one side of the n + -type source layer 4 is 8 μm, the length of one side of the p-type base layer is 9 μm, so the channel length is 0.5 μm.

第３イオン注入工程では、窒素イオンの濃度が、ｎ−型ドリフト層２の表面から深さ０．３μｍまで３×１０19／ｃｍ3で一定となるようにイオンを注入する。イオン注入時のＳｉＣ基板１の温度は２５℃とする。 In the third ion implantation step, ions are implanted so that the concentration of nitrogen ions is constant at 3 × 10 19 / cm 3 from the surface of the n − -type drift layer 2 to a depth of 0.3 μm. The temperature of the SiC substrate 1 during ion implantation is set to 25 ° C.

さらに、第３レジストパターンを除去した後、ＳｉＣ基板の表面上にフォトリソグラフィを用いて第４レジストパターンを形成した上で、ｎ型不純物となる窒素イオンをｐ型ベース層３に囲まれたｎ−型ドリフト層２にイオン注入する（第４イオン注入工程）。このイオン注入により、図１１に示すようにｎ−型ドリフト層２内にｎ＋型半導体層４を形成する。この状態を上面から見ると、図５に示すようにｐ型ベース層３に囲まれた領域にｎ＋型半導体層４が形成されている。   Further, after removing the third resist pattern, a fourth resist pattern is formed on the surface of the SiC substrate using photolithography, and then nitrogen ions that become n-type impurities are surrounded by the p-type base layer 3. Ions are implanted into the − type drift layer 2 (fourth ion implantation step). By this ion implantation, an n + type semiconductor layer 4 is formed in the n − type drift layer 2 as shown in FIG. When this state is viewed from above, an n + -type semiconductor layer 4 is formed in a region surrounded by the p-type base layer 3 as shown in FIG.

第４イオン注入工程では、窒素イオンの濃度はｎ−型ドリフト層２の濃度よりも高く、ｎ−型ドリフト層２の表面部を含み深さ０．３μｍまで１×１０17個／ｃｍ3で一定となるように注入する。イオン注入時のＳｉＣ基板１の温度は２５℃とする。 In the fourth ion implantation step, the concentration of nitrogen ions is higher than the concentration of n − type drift layer 2, including the surface portion of n − type drift layer 2, and 1 × 10 17 ions / cm 3 up to a depth of 0.3 μm. Inject to be constant. The temperature of the SiC substrate 1 during ion implantation is set to 25 ° C.

次に、第４レジストパターンを除去した後、ＳｉＣ基板１の表面上に酸化膜パターンを形成した上で、ｐ型の不純物となるＡｌイオンをｐ型ベース層３にイオン注入する（第５イオン注入工程）。このイオン注入により、図１１に示すように、ｎ＋型ソース層４を貫通してｐ型ベース層３と接続するｐ＋型コンタクト層１３が形成される。この状態を上面からみると、図６に示すようにｐ+型コンタクト層１３はｎ＋型ソース層４に囲まれて形成されている。   Next, after removing the fourth resist pattern, an oxide film pattern is formed on the surface of the SiC substrate 1, and then, Al ions that become p-type impurities are ion-implanted into the p-type base layer 3 (fifth ions). Injection process). By this ion implantation, as shown in FIG. 11, a p + type contact layer 13 that penetrates the n + type source layer 4 and is connected to the p type base layer 3 is formed. When this state is viewed from above, the p + -type contact layer 13 is formed surrounded by the n + -type source layer 4 as shown in FIG.

第５イオン注入工程では、Ａｌイオンの濃度が、ｎ−型ドリフト層２の表面から深さ０．４μｍまで３×１０20個／ｃｍ3で一定となるようにイオンを注入する。このイオン注入時のＳｉＣ基板１の温度は５００℃とする。 In the fifth ion implantation step, ions are implanted so that the concentration of Al ions is constant at 3 × 10 20 ions / cm 3 from the surface of the n − -type drift layer 2 to a depth of 0.4 μm. The temperature of the SiC substrate 1 during this ion implantation is set to 500 ° C.

この後、活性化アニール工程（図示せず）を行う。前工程の酸化膜パターンを除去した後、ｎ−型ドリフト層２などのＳｉＣ膜表面にカーボン保護層を形成し、第１イオン注入工程〜第５イオン注入工程で注入された不純物イオンを活性化するために、アルゴン（Ａｒ）ガス雰囲気中で、１７００℃、１０分間の熱処理（活性化アニール）を行う。活性化アニール後にカーボン保護層を除去する。   Thereafter, an activation annealing step (not shown) is performed. After removing the oxide film pattern in the previous process, a carbon protective layer is formed on the surface of the SiC film such as the n − type drift layer 2 to activate the impurity ions implanted in the first ion implantation process to the fifth ion implantation process. Therefore, heat treatment (activation annealing) is performed at 1700 ° C. for 10 minutes in an argon (Ar) gas atmosphere. The carbon protective layer is removed after the activation annealing.

ここで、図１２に示した第５イオン注入工程後の断面図において、第１イオン注入工程によりＡｌイオンがイオン注入されたｐ型ベース層３のうち、第３イオン注入工程により形成されたｎ+型ソース層４には、第１イオン注入工程で注入されたｐ型の不純物となるＡｌイオンと逆の導電型を与えるｎ型の不純物である窒素イオンが注入される。第３イオン注入工程で注入される窒素イオンの体積密度は第１イオン注入工程で注入されるＡｌイオンの体積密度より多いため、ｎ＋型ソース層４の導電型は活性化アニール工程の後にｎ型となる。   Here, in the cross-sectional view after the fifth ion implantation step shown in FIG. 12, of the p-type base layer 3 into which Al ions are implanted by the first ion implantation step, n formed by the third ion implantation step is formed. In the + -type source layer 4, nitrogen ions, which are n-type impurities having a conductivity type opposite to that of Al ions, which are p-type impurities implanted in the first ion implantation step, are implanted. Since the volume density of nitrogen ions implanted in the third ion implantation process is higher than the volume density of Al ions implanted in the first ion implantation process, the conductivity type of the n + -type source layer 4 is n-type after the activation annealing process. It becomes.

ｎ＋型ソース層４のうち、第５イオン注入工程により形成されたｐ＋型コンタクト層１３は、第３イオン注入工程で注入されたｎ型不純物となる窒素イオンと逆の導電型を与えるｐ型の不純物であるＡｌイオンが第５イオン注入工程で注入される。第５イオン注入工程で注入されるイオンの体積密度が第３イオン注入工程で注入されるイオンの体積密度より多いため、ｎ＋型ソース層４内のｐ＋型コンタクト層１３の導電型は活性化アニール工程の後にｐ型となる。   Of the n + type source layer 4, the p + type contact layer 13 formed by the fifth ion implantation step is a p type that provides a conductivity type opposite to that of the nitrogen ions that are n type impurities implanted in the third ion implantation step. Al ions as impurities are implanted in the fifth ion implantation step. Since the volume density of ions implanted in the fifth ion implantation step is higher than the volume density of ions implanted in the third ion implantation step, the conductivity type of the p + type contact layer 13 in the n + type source layer 4 is activated annealing. It becomes p-type after the process.

また、ｐ型ベース層３とｐ型半導体層１２については、第１イオン注入工程および第２イオン注入工程で注入されたＡｌイオンの体積密度がｎ−型ドリフト層２のｎ型不純物の体積密度よりも多いため、活性化アニール工程の後にｐ型の導電型になる。   For the p-type base layer 3 and the p-type semiconductor layer 12, the volume density of Al ions implanted in the first ion implantation step and the second ion implantation step is the volume density of n-type impurities in the n − type drift layer 2. Therefore, it becomes a p-type conductivity after the activation annealing step.

次に、図１３に示すように、ｎ−型ドリフト層２の表面を熱酸化して所望の厚みのゲート絶縁膜５を形成した後、ゲート絶縁膜５の上に導電性を付与した多結晶Ｓｉ膜を減圧ＣＶＤ法により形成し、これをパターニングすることによりゲート電極６を形成する（ゲート形成工程）。この状態を上面から見ると図７のようになる。ゲート電極６は、ｎ＋型半導体層１４とｐ型ベース層３と一部のｎ＋型ソース層４の上にゲート酸化膜５を介して形成される。   Next, as shown in FIG. 13, the surface of the n − -type drift layer 2 is thermally oxidized to form a gate insulating film 5 having a desired thickness, and then a polycrystal with conductivity provided on the gate insulating film 5. A Si film is formed by a low pressure CVD method, and this is patterned to form a gate electrode 6 (gate forming step). FIG. 7 shows this state as viewed from above. The gate electrode 6 is formed on the n + type semiconductor layer 14, the p type base layer 3, and a part of the n + type source layer 4 via the gate oxide film 5.

その後、図１４に示すように、ゲート電極６およびゲート絶縁膜５の上に酸化珪素からなる層間絶縁膜７を形成する。また、層間絶縁膜７およびゲート絶縁膜５に開口してｎ＋型ソース層４の一部とｐ＋型コンタクト層１３を露出し、その上にソースコンタクト層を堆積し、これを熱処理することによってソースコンタクト電極９を形成する。この状態を上面からみると図１のようになり、層間絶縁膜７の開口部がｎ＋型ソース層４の一部とｐ＋型コンタクト層１３の上に形成される。   Thereafter, as shown in FIG. 14, an interlayer insulating film 7 made of silicon oxide is formed on the gate electrode 6 and the gate insulating film 5. Further, a part of the n + type source layer 4 and the p + type contact layer 13 are exposed through the interlayer insulating film 7 and the gate insulating film 5, and a source contact layer is deposited thereon and heat-treated to thereby source the source. Contact electrode 9 is formed. When this state is viewed from the top, it becomes as shown in FIG. 1, and an opening of the interlayer insulating film 7 is formed on a part of the n + type source layer 4 and the p + type contact layer 13.

ソースコンタクト電極９には例えばＮｉを選択すると、ｎ＋型ソース層４およびｐ＋型コンタクト層１３に対してオーミックコンタクトを形成することができる。   For example, when Ni is selected for the source contact electrode 9, an ohmic contact can be formed with respect to the n + -type source layer 4 and the p + -type contact layer 13.

続いて、図１５に示すように、ソースコンタクト電極９上にソース電極８および図示しない内部配線を形成する。また、図示しないがゲート電極６上の層間絶縁膜７を開口し、ゲート電極６上の開口部にはゲート配線を形成する。最後に、ＳｉＣ基板１の裏面側に例えばＮｉ合金のドレイン電極１１を形成する（裏面電極形成工程）。   Subsequently, as shown in FIG. 15, the source electrode 8 and an internal wiring (not shown) are formed on the source contact electrode 9. Although not shown, an interlayer insulating film 7 on the gate electrode 6 is opened, and a gate wiring is formed in the opening on the gate electrode 6. Finally, a drain electrode 11 made of, for example, an Ni alloy is formed on the back surface side of the SiC substrate 1 (back surface electrode forming step).

以上の工程によって、本実施の形態の半導体装置である縦型のＳｉＣ−ＭＯＳＦＥＴが形成される。   Through the above steps, a vertical SiC-MOSFET which is a semiconductor device of the present embodiment is formed.

ｎ＋型半導体層１４はｎ−型ドリフト層２よりも低抵抗であり、チャネル領域を通る電流の経路を拡大する効果を奏し、ｐ型半導体層１２を設けることにより生じるｎ−型ドリフト層２の抵抗の増加を防ぐ。そのため、ｎ＋型半導体層１４は少なくともチャネル領域と接していれば良く、図１０〜図１５に示したようなｎ−型ドリフト層２の表層部だけでなく、その内部に設けても良い。また、ｐ型ベース領域３に囲まれたｎ−型ドリフト層２の領域において、電界強度が最も大きくなる中央部以外の領域に設けても良い。さらに、ｎ＋型半導体層１４はｐ型半導体層１２と離間して形成しているが、ｐ型半導体層１２を囲むように配置しても良い。特に、ｎ−型ドリフト層２内で最も抵抗が高くなるｐ型半導体層１２とｐ型ベース層３で挟まれる領域にｎ型半導体層１４を配置すると、ｎ−型ドリフト層２内の抵抗を大きく減らすことが可能である。なお、ｎ−型ドリフト層２の抵抗が許容できる値である場合は、ｎ＋型半導体層１４を形成しなくても良い。   The n + type semiconductor layer 14 has a lower resistance than the n − type drift layer 2, has an effect of expanding a current path through the channel region, and is formed by providing the p type semiconductor layer 12. Prevent increase in resistance. Therefore, the n + type semiconductor layer 14 only needs to be in contact with at least the channel region, and may be provided not only in the surface layer portion of the n − type drift layer 2 as shown in FIGS. Further, in the region of the n − type drift layer 2 surrounded by the p-type base region 3, it may be provided in a region other than the central portion where the electric field strength is the highest. Further, although the n + type semiconductor layer 14 is formed apart from the p type semiconductor layer 12, it may be arranged so as to surround the p type semiconductor layer 12. In particular, when the n-type semiconductor layer 14 is disposed in a region sandwiched between the p-type semiconductor layer 12 and the p-type base layer 3 having the highest resistance in the n − -type drift layer 2, the resistance in the n − -type drift layer 2 is reduced. It can be greatly reduced. If the resistance of the n − type drift layer 2 is an allowable value, the n + type semiconductor layer 14 may not be formed.

また、ｐ型半導体層１２はｎ−型ドリフト層２の内部に形成することとしたが、チャネル領域ではないセルコーナー部でｐ型ベース層３と接続する場合はチャネル抵抗に影響を与えないため、ｐ型半導体層１２をｎ−型ドリフト層２の表層部に形成しても良い。この場合、ｎ＋型半導体層１４は形成しないか（図１７）、ｎ−型ドリフト層２の内部に形成される。   In addition, the p-type semiconductor layer 12 is formed inside the n − -type drift layer 2. However, when the p-type semiconductor layer 12 is connected to the p-type base layer 3 at a cell corner that is not a channel region, the channel resistance is not affected. The p-type semiconductor layer 12 may be formed on the surface layer portion of the n − -type drift layer 2. In this case, the n + type semiconductor layer 14 is not formed (FIG. 17) or is formed inside the n − type drift layer 2.

また、第２、第４イオン注入工程において、ｐ型半導体層１２とｎ型半導体層１４へのイオン注入は密度が一定となるボックスプロファイルで行ったが、必ずしもボックスプロファイルに限定するものではない。例えばｐ型半導体層１２では、ｎ−型ドリフト層２の表層での濃度が内部の濃度よりも高くなるように、ｎ−型ドリフト層２の表層から内部へ離れるに従って、徐々にイオン注入濃度が高くなるようなプロファイルにしても良い。この場合、イオン注入に必要な加速電圧の種類を、例えばボックスプロファイルとして形成する際に必要な６種類から１種類に削減することができ、イオン注入工程のスループットが向上するという効果がある。   Further, in the second and fourth ion implantation steps, ion implantation into the p-type semiconductor layer 12 and the n-type semiconductor layer 14 is performed with a box profile having a constant density, but is not necessarily limited to the box profile. For example, in the p-type semiconductor layer 12, the ion implantation concentration gradually increases as the distance from the surface layer of the n − -type drift layer 2 increases so that the concentration in the surface layer of the n − -type drift layer 2 is higher than the internal concentration. You may make it a profile which becomes high. In this case, the type of acceleration voltage required for ion implantation can be reduced from, for example, six types necessary for forming a box profile to one type, and the throughput of the ion implantation process is improved.

＜効果＞
本発明の半導体装置である縦型ＳｉＣ−ＭＯＳＦＥＴによれば、以下の効果を奏する。すなわち、本実施の形態の半導体装置は、ＳｉＣ基板１表面に形成された第１導電型のドリフト層（ｎ−型ドリフト層２）と、ｎ−型ドリフト層２表面に選択的に複数形成された、第２導電型のベース層（ｐ型ベース層３）と、ｐ型ベース層３表面に選択的に形成された領域であって、当該領域とｎ−型ドリフト層２とで挟まれたｐ型ベース層３表面をチャネル領域として規定する第１導電型のソース領域（ｎ＋型ソース層４）と、チャネル領域上からｎ−型ドリフト層２上に渡って、ゲート絶縁膜５を介して形成されたゲート電極６と、平面視でｐ型ベース層３に囲まれたｎ−型ドリフト層２の領域において、当該領域の中心部とｐ型ベース層３とを繋ぐ第２導電型の第１半導体層（ｐ型半導体層１２）と、を備える。ｐ型ベース層３に囲まれたｎ−型ドリフト層２の領域の中心部が最も逆方向電界強度が高くなる領域であるが、この領域とｐ型ベース層３の所定部分をｐ型半導体層１２で接続することにより、ｎ−型ドリフト層２のサイズを小さくすることなくゲート絶縁膜５の逆方向電界強度が低減し、ゲート絶縁膜５の絶縁破壊電圧を高めるという効果を奏する。また、ｐ型半導体層１２はソース電極８と接続されたｐ型ベース層３と繋がっているため、ｐ型半導体層１２間の電位のばらつきが少なく、どのｐ型半導体層１２においても安定して電界強度を下げることが出来る。セルが多数集積された縦型半導体装置内のどこか１箇所のｐ型半導体装置１２の電界緩和効果が低減すれば、その場所のゲート絶縁膜に絶縁破壊が生じてしまうので、全てのｐ型半導体層１２の電位を安定に保つことは非常に重要である。また、半導体基板１にＳｉＣ基板を用いるため、Ｓｉ基板と比べてｎ−型ドリフト層２の不純物濃度を１／１００程度にすることができる。そのため、セルサイズの一辺を１０μｍ以下と小さくすることが出来る。 <Effect>
The vertical SiC-MOSFET which is the semiconductor device of the present invention has the following effects. That is, the semiconductor device of the present embodiment is selectively formed on the surface of the first conductivity type drift layer (n − type drift layer 2) formed on the surface of SiC substrate 1 and on the surface of n − type drift layer 2. A region selectively formed on the surface of the second conductivity type base layer (p-type base layer 3) and the p-type base layer 3 and sandwiched between the region and the n − -type drift layer 2 A first conductivity type source region (n + type source layer 4) defining the surface of the p type base layer 3 as a channel region, and a gate insulating film 5 from the channel region to the n− type drift layer 2. In the region of the formed gate electrode 6 and the n − -type drift layer 2 surrounded by the p-type base layer 3 in plan view, the second conductivity type second connecting the central portion of the region and the p-type base layer 3. 1 semiconductor layer (p-type semiconductor layer 12). The central portion of the region of the n − -type drift layer 2 surrounded by the p-type base layer 3 is a region having the highest reverse electric field strength. A predetermined portion of this region and the p-type base layer 3 is defined as a p-type semiconductor layer. By connecting at 12, the reverse electric field strength of the gate insulating film 5 is reduced without reducing the size of the n − type drift layer 2, and the breakdown voltage of the gate insulating film 5 is increased. Further, since the p-type semiconductor layer 12 is connected to the p-type base layer 3 connected to the source electrode 8, there is little variation in potential between the p-type semiconductor layers 12, and any p-type semiconductor layer 12 is stable. Electric field strength can be lowered. If the electric field relaxation effect of the p-type semiconductor device 12 at one location in the vertical semiconductor device in which a large number of cells are integrated is reduced, dielectric breakdown occurs in the gate insulating film at that location. It is very important to keep the potential of the semiconductor layer 12 stable. In addition, since a SiC substrate is used as the semiconductor substrate 1, the impurity concentration of the n − type drift layer 2 can be reduced to about 1/100 as compared with the Si substrate. Therefore, one side of the cell size can be reduced to 10 μm or less.

また、ｐ型ベース層３は、角部（セルコーナー部）を互いに接続した千鳥格子状に配設される。このように配置することによって、ｎ−型ドリフト層２はその周囲がセルで囲まれ、チャネル領域と接することにより、単位面積当たりのチャネル領域の周囲長が増大し、チャネル抵抗が低減する。   The p-type base layer 3 is arranged in a staggered pattern in which corner portions (cell corner portions) are connected to each other. By arranging in this way, the n − type drift layer 2 is surrounded by cells and is in contact with the channel region, so that the perimeter of the channel region per unit area increases and the channel resistance decreases.

さらに、ｐ型半導体層１２はｐ型ベース層３に囲まれたｎ−型ドリフト層の領域の中心部と、当該領域の外周と接触するｐ型ベース層３のセルコーナー部のうち少なくとも一つとを繋ぐ。セルコーナー部はチャネルとして機能していないため、第１半導体層１２はｐ型ベース層３と接触してもチャネル領域とは接触しない。つまり、チャネル抵抗を増加させずに耐圧を向上することができる。   Further, the p-type semiconductor layer 12 includes at least one of a central portion of a region of the n − -type drift layer surrounded by the p-type base layer 3 and a cell corner portion of the p-type base layer 3 in contact with the outer periphery of the region. Connect. Since the cell corner portion does not function as a channel, the first semiconductor layer 12 does not contact the channel region even if it contacts the p-type base layer 3. That is, the breakdown voltage can be improved without increasing the channel resistance.

また、ｐ型半導体層１２がｎ−型ドリフト層２の表面から離間して内部に形成されることにより、チャネル領域からｎ−型ドリフト層２への電流経路を妨げない。そのため、ｐ型半導体層１２はセルコーナー部でｐ型ベース層３と接続しなくとも良く、例えば図１６に示すようにセルの辺でｐ型ベース層３と接続することも可能である。このような場合でも、チャネル抵抗を増加させずに耐圧を向上することができる。   In addition, since the p-type semiconductor layer 12 is formed inside and spaced from the surface of the n − type drift layer 2, the current path from the channel region to the n − type drift layer 2 is not hindered. Therefore, the p-type semiconductor layer 12 does not need to be connected to the p-type base layer 3 at the cell corner portion. For example, as shown in FIG. 16, it can be connected to the p-type base layer 3 at the cell side. Even in such a case, the breakdown voltage can be improved without increasing the channel resistance.

あるいは、ｐ型半導体層１２がｎ−型ドリフト層２の表層部に形成される場合は、ｐ型半導体層１２がセルコーナー部でｐ型ベース層３と接続することによって、チャネル抵抗を増加させずに耐圧を向上することができる。   Alternatively, when the p-type semiconductor layer 12 is formed on the surface layer portion of the n − -type drift layer 2, the p-type semiconductor layer 12 is connected to the p-type base layer 3 at the cell corner portion, thereby increasing the channel resistance. The breakdown voltage can be improved.

また、半導体装置は、ｐ型ベース層３に囲まれたｎ−型ドリフト層２の表層部に配設され、ｎ−型ドリフト層２よりも不純物密度の高い第１導電型の第２半導体層（ｎ＋型半導体層１４）をさらに備える。ｎ＋型半導体層１４はｎ−型ドリフト層２よりも低抵抗であり、ｎ−型ドリフト層２の表層部で速やかに電流経路を拡大する効果があるため、ｐ型半導体層１２を設けることにより生じるｎ−型ドリフト層２の抵抗の増加を防ぐことが出来る。   The semiconductor device is disposed in the surface layer portion of the n − type drift layer 2 surrounded by the p type base layer 3, and has a first conductivity type second semiconductor layer having a higher impurity density than the n − type drift layer 2. (N + type semiconductor layer 14) is further provided. By providing the p-type semiconductor layer 12, the n + -type semiconductor layer 14 has a lower resistance than the n − -type drift layer 2 and has the effect of quickly expanding the current path at the surface layer portion of the n − -type drift layer 2. The increase in resistance of the n − type drift layer 2 can be prevented.

１ ＳｉＣ基板、１ａ ｎ＋型ドレイン層、２ ｎ−型ドリフト層、３ ｐ型ベース層、４ ｎ＋型ソース層、５ ゲート絶縁膜、６ ゲート電極、７ 層間絶縁膜、８ ソース電極、９ ソースコンタクト電極、１２ ｐ型半導体層、１３ ｐ＋型半導体層、１４ ｎ＋型半導体層。   1 SiC substrate, 1a n + type drain layer, 2 n− type drift layer, 3 p type base layer, 4 n + type source layer, 5 gate insulating film, 6 gate electrode, 7 interlayer insulating film, 8 source electrode, 9 source contact Electrode, 12 p-type semiconductor layer, 13 p + type semiconductor layer, 14 n + type semiconductor layer.

Claims (6)

ＳｉＣ基板表面に形成された第１導電型のドリフト層と、
前記ドリフト層表面に選択的に複数形成された、第２導電型のベース層と、
前記ベース層表面に選択的に形成された領域であって、当該領域と前記ドリフト層とで挟まれた前記ベース層表面をチャネル領域として規定する第１導電型のソース領域と、
前記チャネル領域上から前記ドリフト層上に渡って、絶縁膜を介して形成されたゲート電極と、
平面視で前記ベース層に囲まれた前記ドリフト層の領域において、当該領域の中心部と前記ベース層とを繋ぐ第２導電型の第１半導体層と、を備える半導体装置。 A first conductivity type drift layer formed on the surface of the SiC substrate;
A plurality of second conductivity type base layers selectively formed on the surface of the drift layer;
A region selectively formed on the surface of the base layer, the first conductivity type source region defining the base layer surface sandwiched between the region and the drift layer as a channel region;
A gate electrode formed through an insulating film over the drift region from the channel region;
A semiconductor device comprising: a first semiconductor layer of a second conductivity type that connects a central portion of the region and the base layer in a region of the drift layer surrounded by the base layer in plan view. 前記ベース層は、角部を互いに接続した千鳥格子状に配設される、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the base layer is arranged in a staggered pattern with corners connected to each other. 前記第１半導体層は、前記ベース層に囲まれた前記ドリフト層の領域の中心部と、当該領域の外周と接触する前記ベース層の前記角部のうち少なくとも一つの角部とを繋ぐ請求項２に記載の半導体装置。   The said 1st semiconductor layer connects the center part of the area | region of the said drift layer enclosed by the said base layer, and the at least 1 corner | angular part of the said corner | angular part of the said base layer which contacts the outer periphery of the said area | region. 2. The semiconductor device according to 2. 前記第１半導体層は、前記ドリフト層の表面から離間して内部に形成される、請求項１〜３のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first semiconductor layer is formed inside and spaced from a surface of the drift layer. 前記第１半導体層は、前記ドリフト層の表層部に形成される、請求項１〜３のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first semiconductor layer is formed in a surface layer portion of the drift layer. 前記ベース層に囲まれた前記ドリフト層の表層部に配設され、前記ドリフト層よりも不純物密度の高い第１導電型の第２半導体層をさらに備える、請求項１〜５のいずれかに記載の半導体装置。   6. The semiconductor device according to claim 1, further comprising a second semiconductor layer of a first conductivity type disposed in a surface layer portion of the drift layer surrounded by the base layer and having a higher impurity density than the drift layer. Semiconductor device.
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US10211330B2 (en) 2012-03-30 2019-02-19 Fuji Electric Co., Ltd. Vertical high voltage semiconductor apparatus and fabrication method of vertical high voltage semiconductor apparatus
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US10263105B2 (en) 2013-08-08 2019-04-16 Fuji Electric Co., Ltd. High voltage semiconductor device
JP2019216252A (en) * 2013-09-20 2019-12-19 モノリス セミコンダクター インコーポレイテッド High voltage MOSFET device and method of manufacturing the device
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US11417760B2 (en) 2017-12-21 2022-08-16 Wolfspeed, Inc. Vertical semiconductor device with improved ruggedness
US11489069B2 (en) 2017-12-21 2022-11-01 Wolfspeed, Inc. Vertical semiconductor device with improved ruggedness
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