JP2020013916A - Semiconductor device - Google Patents

Abstract

To provide a MOS semiconductor device incorporating a SBD in the same semiconductor substrate, capable of restraining parasitic pin diode operation.SOLUTION: Between adjacent gate electrodes 9 of a vertical MOSFET of planar gate structure, a planar SBD20 having a conductive layer 21 in Schottky contact with a JFET region 3a is provided. In the n-type current diffusion region 3 of the MOSFET, first through third p-type regions 7, 41, 42 are provided selectively. On the drain side in the p-type base region 4, the n-type source region 5 and the p-type contact region 6, the first p-type region 7 opposes these regions in the depth direction in contact therewith. The second and third p-type regions 41, 42 are placed at positions opposing the first p-type region 7 in the depth direction Z, and form a multilayer lamination structure. The width L2 of third p-type region 42 (width of the lowermost p-type region) is narrower than the width L11 of the first p-type region 7, and is 8 μm or less.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  A semiconductor having a wider band gap than silicon (Si) (hereinafter, referred to as a wide band gap semiconductor) has a higher maximum electric field strength than silicon, and is therefore expected to be a semiconductor material capable of sufficiently reducing on-resistance. Further, in a power semiconductor device using a wide band gap semiconductor as a semiconductor material, it is required to reduce on-resistance, suppress forward characteristic deterioration, and reduce reverse recovery loss.

  The suppression of the forward characteristic deterioration and the reduction of the reverse recovery loss are the same as those of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS field effect transistor having an insulating gate having a three-layer structure of metal-oxide-semiconductor). This can be realized by incorporating a Schottky Barrier Diode (SBD) in a semiconductor chip.

  A conventional semiconductor device will be described by way of an example in which silicon carbide is used as a semiconductor material. FIG. 14 is a cross-sectional view showing the structure of a conventional semiconductor device. The conventional semiconductor device shown in FIG. 14 is a vertical MOSFET having a planar gate structure in which a gate electrode 109 is provided in a flat plate shape on the front surface of a semiconductor substrate (semiconductor chip) 130 made of silicon carbide. An SBD (hereinafter, referred to as a plane SBD) 120 arranged in a flat plate shape on the front surface of the substrate 130 is incorporated.

Semiconductor substrate 130 is an epitaxial substrate in which silicon carbide layers 131 and 132 to be n ⁻ type drift region 102 and p type base region 104 are sequentially epitaxially grown on n ⁺ type starting substrate 101 made of silicon carbide. An n-type current diffusion region 103 is provided on a surface layer of n ⁻ -type silicon carbide layer 131 opposite to n ⁺ -type starting substrate 101 side. The n-type current diffusion region 103 has a function of reducing carrier spreading resistance. The portion of the n ⁻ -type silicon carbide layer 131 other than the n-type current diffusion region 103 is the n ⁻ -type drift region 102. Inside the n-type current diffusion region 103, a lowermost p ⁺ -type region 107 is selectively provided.

As the p-type silicon carbide layer 132, an n ⁺ -type source region 105 and a p ⁺⁺ -type contact region 106 that penetrate the p-type silicon carbide layer 132 in the depth direction Z and reach the n ⁻ -type silicon carbide layer 131 are respectively selected. Is provided. Further, p-type silicon carbide layer 132 has an n-type region separated from n ⁺ -type source region 105 and p ⁺⁺ -type contact region 106. This n-type region penetrates silicon carbide layer 132 in the depth direction Z, contacts n-type current diffusion region 103 of the lower layer between adjacent lowermost p ⁺ -type regions 107, and Of the current diffusion region 103 (JFET region 103a).

A portion of the p-type silicon carbide layer 132 other than the n ⁺ -type source region 105, the p ⁺⁺ -type contact region 106 and the JFET region 103a is a p-type base region 104. Each of regions 103a, 104 to 107 formed in silicon carbide layers 131 and 132 has a direction parallel to the front surface of semiconductor substrate 130 when viewed from the front surface side of semiconductor substrate 130 (hereinafter, a first direction). Are arranged in a linear layout extending in X. The n ⁺ -type source region 105 is parallel to the front surface of the semiconductor substrate 130 and extends in a direction Y (hereinafter, referred to as a second direction) Y orthogonal to the first direction X with the p-type base region 104 interposed therebetween. It faces the area 103a.

p ⁺⁺ -type contact region 106, the n ⁺ -type source region 105 is disposed on the opposite side of the JFET region 103a side, in contact with the n ⁺ -type source region 105. The JFET region 103a is a region between the adjacent p-type base regions (the p-type base region 104 and the lowermost p ⁺ -type region 107 described later) of the n-type current diffusion region 103. Bottom p ⁺ -type region 107 is a p ⁺ -type region disposed most drain side inside the n-type current diffusion region 103, p type base region 104, n ⁺ -type source region 105 and the p ⁺⁺ -type contact The drain side (drain electrode 113 side) of the region 106 is provided in contact with these regions.

The lowermost p ⁺ -type region 107 covers the entire drain side of the p-type base region 104, the n ⁺ -type source region 105, and the p ⁺⁺ -type contact region 106. A gate electrode 109 is provided on a surface of the p-type base region 104 between the n ⁺ -type source region 105 and the JFET region 103a (the n-type current diffusion region 103) via a gate insulating film. The conductive layer 111 makes ohmic contact with the n ⁺ type source region 105 and the p ⁺⁺ type contact region 106. The conductive layer 121 makes a Schottky contact with the JFET region 103a. The source electrode 112 is electrically connected to the conductive layers 111 and 121.

The plane SBD 120 is a diode that exhibits a rectifying function due to Schottky contact between the JFET region 103a and the conductive layer 121, and is disposed between the adjacent gate electrodes 109 with the JFET region 103a interposed therebetween. By arranging the plane SBD 120 between the gate electrodes 109, the p ⁺⁺ type contact region 106, the lowermost p ⁺ type region 107, the n type current diffusion region 103, the n ⁻ type drift region 102, and the n ⁺ type starting substrate (n Forward deterioration due to the operation of a parasitic pin (p-intrinsic-n) diode formed at the pn junction with the ( ⁺ type drain region) 101 is suppressed.

In FIG. 14, the conductive layer 111 that makes ohmic contact with the semiconductor substrate 130 and the conductive layer 121 that makes Schottky contact with the semiconductor substrate 130 are indicated by different hatchings. Symbols R _JFET and R _D are a MOSFET JFET (Junction FET) resistance and a MOSFET drift resistance (resistance of the n ⁻ type drift region 102), respectively. AA is one unit cell of the MOSFET.

As another example of a vertical MOSFET of the conventional planar gate structure, inside the n-type drift layer, p-type base region, the depth p ⁺ -type contact region (p ⁺ -type contact region contacting the source electrode and the ohmic) A device has been proposed in which a p-type layer having the same width as the p ⁺ -type contact region is selectively provided directly below (in the drain side) of a portion opposed in the direction, in contact with the p-type base region (for example, See Patent Document 1 (paragraph 0019, 0041, FIG. 1).)

In the following Patent Document 1, when a surge voltage occurs, a breakpoint of a parasitic pn diode formed by a pn junction between a p-type base region and an n-type drift layer becomes a p-type layer immediately below the p-type base region. By drawing the current flowing inside the semiconductor substrate when a surge voltage occurs from the p-type layer immediately below the p-type base region to the source electrode through the path passing through the p ⁺ -type contact region, current concentration on the surface channel layer is suppressed and the breakdown voltage is reduced. Has been improved.

Further, as a conventional vertical MOSFET having a planar gate structure, an n-type current diffusion region having an impurity concentration higher than that of an n ⁻ -type drift region is provided only in the JFET region, thereby reducing the spread resistance of carriers in the JFET region. (For example, refer to Patent Document 2 below (paragraph 0083, FIG. 21)).

JP 2009-016601 A JP 2017-055145 A

In the conventional vertical MOSFET having a planar gate structure (see FIG. 14), when the carrier spreading resistance Rsp of the n-type current diffusion region 103 is high in the portion immediately below the lowermost p ⁺ -type region 107, the p-type base region 104, A forward voltage is easily applied to a parasitic pin diode including the lowermost p ⁺ -type region 107, the n-type current diffusion region 103, the n ⁻ -type drift region 102, and the n ⁺ -type starting substrate 101. This parasitic pin diode operates when a forward voltage exceeding the built-in potential (built-in potential) of the pn junction between the lowermost p ⁺ type region 107 and the n ⁻ type drift region 102 is applied.

The spreading resistance Rsp of carriers in the n-type current diffusion region 103 is determined by the width L101 of the lowermost p ⁺ -type region 107. The width L101 of the lowermost p ⁺ -type region 107 is defined as the direction from the current path of the forward current of the plane SBD 120 flowing from the n-type current diffusion region 103 toward the n ⁺ -type starting substrate 101 to the p ⁺⁺ -type contact region 106 side. This is the length of the lowermost p ⁺ -type region 107 in the direction Y (that is, the width between the JFET regions immediately below the adjacent plane SBD 120).

It has been confirmed by the inventor that if the width L101 of the lowermost p ⁺ -type region 107 is large, the spreading resistance Rsp of carriers in the n-type current diffusion region 103 is high, and the above-mentioned parasitic pin diode is easy to operate. The width L101 of the lowermost p ⁺ -type region 107 depends on the conditions (particularly the width of these regions) of the p-type base region 104, the n ⁺ -type source region 105, and the p ^++- type contact region 106 in the MOSFET having the planar gate structure. Because it is determined, it is difficult to narrow.

For example, when the cell pitch L102 of the MOSFET is about 10 μm, the width L101 of the lowermost p ⁺ -type region 107 is 8 μm or more. When the width L101 of the lowermost p ⁺ -type region 107 is 8 μm or more, a large current (parasitic pn diode) flows from the lowermost p ⁺ -type region 107 toward the n ⁺ -type starting substrate 101 (depth direction Z) as described later. It has been confirmed by the inventor that it is difficult to suppress the parasitic pn diode operation when the operating current flows (see FIGS. 6 and 7).

  FIG. 15 is a cross-sectional view showing another example of the conventional semiconductor device. FIG. 15 shows a simplified version of the vertical MOSFET of FIG. In Patent Document 1 as well, similarly to the conventional vertical MOSFET shown in FIG. 14, the width of the lowermost portion 107 'of the p-type base region 104' (specifically, the width of the lowermost portion 107 'of the p-type base region 104'). , JFET region 103a ′ to another adjacent unit cell, L101 ′), determines the carrier spreading resistance Rsp ′ of n-type drift region 102 ′.

To lower the carrier spreading resistance Rsp 'of the n ^- type drift region 102', the impurity concentration of the n ^-- type drift region 102 'may be increased. However, as the impurity concentration of the n-type drift region 102' is increased, the breakdown voltage becomes higher. Will decrease. On the other hand, if the impurity concentration of the n-type drift region 102 'is reduced to obtain a predetermined breakdown voltage, the carrier spreading resistance Rsp' of the n-type drift region 102 'increases.

Also, in Patent Document 1, the width (= 2 × L101 ′) of the lowermost part 107 ′ of the p-type base region 104 ′ is determined by the p ⁺ -type contact region 106 ′, the n ⁺ -type source region 105 ′, and the channel region 104a. 'Depends on the width. Therefore, similarly to the conventional vertical MOSFET shown in FIG. 14, there is a problem that it is difficult to suppress a parasitic pn diode operation formed at a pn junction between the p-type base region 104 'and the n-type drift region 102'. Occurs.

The channel region 104a 'is a portion of the p-type base region 104' between the n ⁺ -type source region 105 'and the JFET region 103a'. In FIG. 15, reference numeral 101 ′ denotes an n ⁺ -type starting substrate that is an n ⁺ -type drain region. Reference numerals 108 'to 113' denote a gate insulating film, a gate electrode, an interlayer insulating film, a conductive layer in ohmic contact with a semiconductor substrate, a source electrode, and a drain electrode, respectively.

  An object of the present invention is to provide a MOS-type semiconductor device having a built-in SBD on the same semiconductor substrate and capable of suppressing the operation of a parasitic pin diode, in order to solve the above-described problems of the related art. Aim.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention includes a transistor and a Schottky barrier diode, and has the following features. A first conductive first semiconductor layer made of a semiconductor having a wider band gap than silicon is provided on a front surface of a semiconductor substrate made of a semiconductor having a wider band gap than silicon. A first conductivity type first semiconductor region having a higher impurity concentration than the first semiconductor layer is provided on a surface layer of the first semiconductor layer opposite to the semiconductor substrate. On the opposite side of the first semiconductor layer with respect to the semiconductor substrate side, a second conductivity type second semiconductor layer made of a semiconductor having a wider band gap than silicon is provided. The second semiconductor layer covers the first semiconductor region. The second semiconductor region of the first conductivity type penetrates the second semiconductor layer in the depth direction and reaches the first semiconductor layer.

  The third semiconductor region of the first conductivity type is selectively provided in the second semiconductor layer separately from the second semiconductor region. The third semiconductor region penetrates the second semiconductor layer in a depth direction, reaches the first semiconductor layer, and forms a part of the first semiconductor region. The third semiconductor region has a higher impurity concentration than the first semiconductor layer. The fourth semiconductor region of the second conductivity type is a portion of the second semiconductor layer other than the second semiconductor region and the third semiconductor region. A gate electrode is provided on a surface of a portion of the fourth semiconductor region interposed between the second semiconductor region and the third semiconductor region via a gate insulating film. The first electrode is electrically connected to the second semiconductor region and the fourth semiconductor region. The second electrode is provided on a back surface of the semiconductor substrate.

  The transistor has the first and second semiconductor layers, the first to fourth semiconductor regions, the gate electrode, and the first and second electrodes. The Schottky barrier diode includes the third semiconductor region and a conductive layer that is in Schottky contact with the third semiconductor region and is electrically connected to the first electrode. A fifth semiconductor region of a second conductivity type and a first to third buried regions of a second conductivity type, each having a higher impurity concentration than the fourth semiconductor region, are selectively provided inside the first semiconductor region. ing. The fifth semiconductor region is arranged to face the second semiconductor region and the fourth semiconductor region in a depth direction, and a surface of the second semiconductor region and the fourth semiconductor region on the second electrode side is arranged. cover. Two or more first buried regions are arranged closer to the second electrode than the fifth semiconductor region.

  The two or more first buried regions are opposed to the fifth semiconductor region in a depth direction, and are stacked in multiple stages from the first electrode side to the second electrode side to be in contact with each other to form a stacked structure. . The second buried region is disposed apart from the fifth semiconductor region and the first buried region, and faces the third semiconductor region in a depth direction. The third buried region is disposed between a lowermost buried region of the first buried region closest to the second electrode and the second buried region. The second buried region is connected. The uppermost buried region of the first buried region that is arranged closest to the first electrode is in contact with the fifth semiconductor region. The width of the lowermost buried region is smaller than the width of the fifth semiconductor region.

Further, a semiconductor device according to the present invention, in the above-described invention, comprises the fourth semiconductor region, the fifth semiconductor region, the first buried region, the third semiconductor region, the first semiconductor layer, and the semiconductor substrate. The critical current density of the parasitic diode is 3000 A / cm ² or more. The cell pitch of the transistor is 10 μm. The width of the lowermost buried region is 8 μm or less.

  Further, in the semiconductor device according to the present invention, in the above-described invention, the gate electrode is arranged in a linear layout extending in a first direction parallel to a front surface of the semiconductor substrate. The first buried region and the second buried region are arranged in a linear layout extending in the first direction. The third buried region is arranged in a linear layout extending in a second direction parallel to the front surface of the semiconductor substrate and orthogonal to the lowermost buried region. Make a layout. A diagonal length of a rectangular planar portion of the lowermost buried region facing the third buried region in the second direction is 8 μm or less.

  Further, in the semiconductor device according to the present invention, in the above-described invention, the gate electrode is arranged in a linear layout extending in a first direction parallel to a front surface of the semiconductor substrate. The first buried region and the second buried region are arranged in a linear layout extending in the first direction. The third buried region is arranged in a linear layout extending in a second direction parallel to the front surface of the semiconductor substrate and orthogonal to the lowermost buried region. Make a layout. The diagonal length of a rectangular divided portion obtained by dividing a rectangular planar portion facing the third embedded region in the second direction by a center line parallel to the second direction in the lowermost embedded region is It is characterized by being 8 μm or less.

  Further, in the semiconductor device according to the present invention, in the above-described invention, the rectangular planar shape portion of the lowermost buried region facing the third buried region in the second direction is the rectangular planar shape. It is characterized in that it has a planar shape having a cutout portion in which the vertex of the portion is cut out so as to be recessed toward the center of the rectangular planar shape portion.

  Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, a sixth semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region is further provided inside the first semiconductor region. And

  Further, in the semiconductor device according to the present invention, in the above-described invention, the first semiconductor layer reaches the first semiconductor layer by penetrating the second semiconductor layer in a depth direction, and the third semiconductor region is formed with respect to the second semiconductor region. On the opposite side, a seventh semiconductor region of a second conductivity type, which is disposed in contact with the second semiconductor region and has a higher impurity concentration than the second semiconductor layer, is further provided. The fourth semiconductor region is a portion of the second semiconductor layer other than the second semiconductor region, the third semiconductor region, and the seventh semiconductor region. The fifth semiconductor region is selectively provided to face the second semiconductor region, the fourth semiconductor region, and the seventh semiconductor region in a depth direction, and further includes the second semiconductor region, the fourth semiconductor region. And covering a surface of the seventh semiconductor region on the second electrode side.

  According to the above-described invention, the first buried region is arranged in multiple stages immediately below the fifth semiconductor region (on the second electrode side), and the number of parasitic JFETs in contact with the drift region in the unit cell is increased to two or more. The spread resistance of carriers in the third semiconductor region during the forward operation of the parasitic pin diode is determined by the width of the first buried region (lowest buried region) disposed closest to the second electrode. In addition, since the width of the lowermost buried region does not depend on the conditions of the third, fourth, and seventh semiconductor regions, the width can be set to, for example, about 8 μm or less, which is smaller than the width of the fifth semiconductor region. For this reason, the spreading resistance of the carriers in the third semiconductor region during the forward operation of the parasitic pin diode can be suppressed.

  ADVANTAGE OF THE INVENTION According to the semiconductor device concerning this invention, it is a MOS type semiconductor device which built-in SBD in the same semiconductor substrate, and has the effect that a parasitic pin diode operation can be suppressed.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment; FIG. 2 is a plan view showing a layout of a part of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate; FIG. 4 is a plan view showing another example of the layout of a part of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate; FIG. 4 is a plan view showing another example of the layout of a part of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate; FIG. 5 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment; FIG. 4 is a characteristic diagram showing a relationship between a distance between a pin diode and a unipolar element arranged on the same semiconductor substrate and a bipolar current. FIG. 13 is a cross-sectional view illustrating a cross-sectional structure of a sample used for verification in FIG. FIG. 11 is a cross-sectional view illustrating a structure of a conventional semiconductor device. FIG. 11 is a cross-sectional view illustrating another example of a conventional semiconductor device.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, a layer or a region entitled with n or p means that electrons or holes are majority carriers, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region to which they are not added. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1)
The semiconductor device according to the first embodiment is configured using a semiconductor having a wider band gap than silicon (Si) (referred to as a wide band gap semiconductor). The structure of the semiconductor device according to the first embodiment will be described using a case where, for example, silicon carbide (SiC) is used as a wide band gap semiconductor. FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment. FIG. 1 shows a cross-sectional structure of one unit cell (element unit) of a MOSFET and a half of another unit cell adjacent to both sides of the unit cell (FIGS. 2 to 2). 8).

  FIG. 1 shows only a part of the unit cells arranged in the active region, and does not show an edge termination region surrounding the periphery of the active region (the same applies to FIG. 11). The active region is a region where the main current of the MOSFET flows. The edge termination region is a region between the active region and the side surface of the semiconductor substrate (semiconductor chip) 30, and is a region that relaxes an electric field on the front surface side of the semiconductor substrate 30 and maintains a withstand voltage (withstand voltage). is there. A general withstand voltage structure such as a guard ring, a field plate, or RESURF is arranged in the edge termination region. The withstand voltage is a limit voltage at which the semiconductor device does not malfunction or break down.

The semiconductor device according to the first embodiment shown in FIG. 1 is a vertical MOSFET having a planar gate structure in which a gate electrode 9 is provided in a flat plate shape on a front surface of a semiconductor substrate 30 made of silicon carbide. An SBD (planar SBD) 20 arranged in a flat plate shape on the front surface of the substrate 30 is incorporated. Semiconductor substrate 30 includes n ⁻ -type drift substrate 2 and p-type base region (fourth semiconductor region) 4 each having silicon carbide layers 31 and 32 on front surface of n ⁺ -type starting substrate 1 made of silicon carbide. This is an epitaxial substrate that has been epitaxially grown.

An n-type current diffusion region (first semiconductor region) 3 is provided on a surface layer of n ⁻ -type silicon carbide layer 31 opposite to n ⁺ -type starting substrate 1. The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 3 is formed by, for example, ion implantation of n-type impurities into the n ⁻ -type silicon carbide layer 31 in a direction parallel to the front surface of the semiconductor substrate 30 (lateral direction: first and second (Directions X, Y). The portion of n ⁻ -type silicon carbide layer 31 other than n-type current diffusion region 3 is n ⁻ -type drift region 2.

A first p ⁺ -type region (fifth semiconductor region) 7 is selectively provided in a surface region of the n-type current diffusion region 3. The first p ⁺ -type region 7 functions as the p-type base region of the MOSFET together with the p-type base region 4. Further, inside the n-type current diffusion region 3, the second to fourth p ⁺ -type regions 41 to 43 are located deeper on the drain side (drain electrode (second electrode) 13 side) than the first p ⁺ -type region 7. Each is selectively provided. The 1p ⁺ -type region 7 and the 2～4P ⁺ -type region 41 to 43 is fixed to the source electrode (first electrode) 12 of the voltage (source potential) via a p ⁺⁺ type contact region 6 to be described later . The second and third p ⁺ -type regions (first buried regions) 41 and 42 spread the carriers in the n-type current diffusion region 3 immediately below the third p ⁺ -type region 42 (drain side) during the forward operation of the parasitic pin diode. It has a function of reducing the resistance Rsp.

P-type silicon carbide layer 32 is provided, for example, on the entire surface of n ⁻ -type silicon carbide layer 31 opposite to n ⁺ -type starting substrate 1 in the active region, and covers first p ⁺ -type region 7. That is, in the edge termination region, the front surface of semiconductor substrate 30 is the surface of silicon carbide layer 31 opposite to n ⁺ type starting substrate 1 (not shown). In the p-type silicon carbide layer 32, an n ⁺ -type source region (second semiconductor region) 5 and a p ⁺⁺ -type contact region (seventh semiconductor region) are provided at positions facing the first p ⁺ -type region 7 in the depth direction Z. ) 6 are selectively provided. N ⁺ -type source region 5 and p ⁺⁺ -type contact region 6 penetrate silicon carbide layer 32 in depth direction Z to reach first p ⁺ -type region 7. The depth direction Z is a direction (vertical direction) from the front surface to the back surface of the semiconductor substrate 30.

Further, p-type silicon carbide layer 32 is separated from n ⁺ -type source region 5 and p ⁺⁺ -type contact region 6 and is an n-type region (hereinafter referred to as an n-type) formed by ion-implanting p-type silicon carbide layer 32. A return region (a third semiconductor region) is provided. The n-type repetition region penetrates the p-type silicon carbide layer 32 in the depth direction Z and contacts the portion of the n-type current diffusion region 3 sandwiched between the adjacent first p ⁺ -type regions 7. And a part of the current diffusion region 3 (JFET region 3a). A portion of the p-type silicon carbide layer 32 other than the n ⁺ -type source region 5, the p ^{+ +} -type contact region 6 and the n-type counter region (JFET region 3 a) is a p-type base region 4.

The JFET region 3a, the p-type base region 4, the n ⁺ -type source region 5, the p ⁺⁺ -type contact region 6, and the first to fourth p ⁺ -type regions 7, 41 to 43 are formed from the front side of the semiconductor substrate 30. When viewed, they are arranged in a linear layout extending in a direction (first direction) X parallel to the front surface of the semiconductor substrate 30. The portion of the n-type current diffusion region 3 sandwiched between adjacent p-type base regions (the p-type base region 4 and the first p ⁺ -type region 7) is the JFET region 3a. The n ⁺ -type source region 5 is opposed to the JFET region 3a with the p-type base region 4 interposed therebetween in a direction (second direction) Y parallel to the front surface of the semiconductor substrate 30 and orthogonal to the first direction X. I do.

p ⁺⁺ -type contact region 6, the n ⁺ -type source region 5, on the opposite side of the JFET region 3a side, are arranged in contact with the n ⁺ -type source regions 5. Specifically, n ⁺ -type source region 5 are arranged on both sides of the second direction Y of the p ⁺⁺ type contact region 6, the n ⁺ -type source region 5, opposite to that p ⁺⁺ -type contact region 6 side A p-type base region 4 is arranged on the side. JFET region 3a is arranged on the opposite side of p-type base region 4 from n ⁺ -type source region 5 side. That is, the n ⁺ -type source region 5, the p-type base region 4, and the JFET region 3a are symmetrically arranged on both sides of the p ⁺⁺ -type contact region 6 in the second direction Y.

The first p ⁺ -type region 7 is opposed to the p-type base region 4, the n ⁺ -type source region 5, and the p ⁺⁺ -type contact region 6 in the depth direction on the drain side of these regions. Further, the first p ⁺ -type region 7 is in contact with the drain side of the p-type base region 4, the n ⁺ -type source region 5, and the p ^++- type contact region 6, and covers the entire surface of these regions on the drain side. That is, the width (width in the second direction Y) L11 of the first p ⁺ -type region 7 is set depending on each width of the p-type base region 4, the n ⁺ -type source region 5, and the p ^++- type contact region 6. You. Specifically, the width L11 of the first p ⁺ -type region 7 is substantially the sum of the widths of the p-type base region 4, the n ⁺ -type source region 5, and the p ^++- type contact region 6.

The second and third p ⁺ -type regions 41 and 42 are arranged at positions facing the first p ⁺ -type region 7 in the depth direction Z, and are stacked in multiple stages from the source side (source electrode 12 side) to the drain side. A laminated structure. Specifically, the second p ⁺ -type region (uppermost buried region) 41 is located immediately below the first p ⁺ -type region 7 and at a position facing the p ⁺⁺ -type contact region 6 in the depth direction Z. It is arranged in contact with the ⁺ type region 7. The portion sandwiched between the adjacent second p ⁺ -type regions 41 is disposed facing the JFET region 3a in the depth direction Z, contacts the JFET region 3a, and functions as the JFET region 3b.

The third p ⁺ -type region (lowest buried region) 42 is formed in the second p ⁺ -type region 41 immediately below the second p ⁺ -type region 41 and at a position facing the p ⁺⁺ -type contact region 6 in the depth direction Z. It is arranged in contact. The portion sandwiched between the adjacent third p ⁺ -type regions 42 is arranged to face the JFET region 3b in the depth direction Z, contacts the JFET region 3b, and functions as the JFET region 3c. The third p ⁺ type region 42 is located closer to the source than the interface between n ⁻ type drift region 2 and n type current diffusion region 3. By providing the second and third p ⁺ -type regions 41 and 42, the number of JFET regions per unit cell (JFET regions 3a to 3c) can be increased.

The widths L1 and L2 of the second and third p ⁺ -type regions 41 and 42 (the widths in the second direction Y) depend on the respective widths of the p-type base region 4, the n ⁺ -type source region 5 and the p ^++- type contact region 6. Can be set. For this reason, by increasing the number of JFET regions per unit cell so as to be stacked in the depth direction Z, the width of the lowermost p ⁺ -type region with respect to the current path of the forward current in the plane SBD 20 is set to the first p ⁺ The width can be smaller than the width L11 of the mold region 7. The lowermost p ⁺ -type region is the most drain region among the first to third p ⁺ -type regions 7, 41, and 42 facing the p ⁺⁺ -type contact region 6 in the depth direction Z inside the n-type current diffusion region 3. The p ⁺ -type region (ie, the third p ⁺ -type region 42) arranged on the side. The width of the lowermost p ⁺ -type region refers to the lowermost p ⁺ -type region in the second direction Y from the current path of the forward current in the plane SBD 20 flowing from the n-type current diffusion region 3 toward the n ⁺ -type starting substrate 1. , Specifically, the width L2 of the third p ⁺ -type region 42.

The widths L1 and L2 of the second and third p ⁺ -type regions 41 and 42 are smaller than the width L11 of the first p ⁺ -type region 7. The widths L1 and L2 of the second and third p ⁺ -type regions 41 and 42 may be larger than the width L12 of the p ⁺⁺ -type contact region 6. The smaller the width L2 of the third p ⁺ -type region 42, the better. The reason is that as the width L2 of the third p ⁺ -type region 42, which is the lowermost p ⁺ -type region, is reduced, the spreading resistance Rsp of the carrier in the n-type current diffusion region 3 during the forward operation of the parasitic pin diode described later increases. This is because it can be lowered. Specifically, when the cell pitch (width of the unit cell in the second direction Y) L10 of the MOSFET is 10 μm, the width L2 of the third p ⁺ type region 42 is, for example, about 8 μm or less. The width L2 of the 3p ⁺ -type region 42 may be the same as the width L1 of the 2p ⁺ -type region 41 may be narrower than the width L1 of the 2p ⁺ -type region 41.

The 4p ⁺ -type region (second buried region) 43, the sandwiched between the 3p ⁺ -type region 42 adjacent portion (i.e. JFET region 3c), the 2, 3P ⁺ -type regions 41 and 42 and the 1p ⁺ It is arranged apart from the mold region 7. A plurality of fourth p ⁺ -type regions 43 may be arranged between the p ⁺ -type regions 42 in the second direction Y with the n-type current diffusion region 3 interposed therebetween. The fourth p ⁺ -type region 43 is connected to the third p ⁺ -type region 42 at a portion not shown. A connection portion between the third p ⁺ -type region 42 and the fourth p ⁺ -type region 43 (fifth p ⁺ -type region (third buried region) 44: see FIGS. 8 to 10) is viewed from the front side of the semiconductor substrate 30. The layout will be described in a third embodiment described later. The width (width in the second direction Y) L3 of the fourth p ⁺ type region 43 may be the same as the width L2 of the third p ⁺ type region 42.

A gate electrode 9 is provided on a surface of the p-type base region 4 between the n ⁺ -type source region 5 and the JFET region 3a (the n-type current diffusion region 3) with a gate insulating film 8 interposed therebetween. The gate electrodes 9 are arranged in a stripe layout extending in the first direction X when viewed from the front surface side of the semiconductor substrate 30. An interlayer insulating film 10 is provided on the entire front surface of the semiconductor substrate 30 so as to cover the gate electrode 9. In the interlayer insulating film 10, first and second contact holes 10 a reaching the front surface of the semiconductor substrate 30 through the interlayer insulating film 10 and the gate insulating film 8 in the depth direction Z between the adjacent gate electrodes 9. , 10b are provided.

The first and second contact holes 10a and 10b are arranged in a linear layout extending in the first direction X when viewed from the front side of the semiconductor substrate 30, for example. In addition, the first contact holes 10a and the second contact holes 10b are alternately arranged in the second direction Y. The n ⁺ type source region 5 and the p ⁺⁺ type contact region 6 are exposed in the first contact hole 10a. Inside the first contact hole 10a, the n ⁺ -type source regions 5 are exposed to the respective gate electrodes 9 arranged on both sides in the second direction Y. For example, p ⁺⁺ is provided between these n ⁺ -type source regions 5. The mold contact region 6 is exposed.

Inside the first contact hole 10a, on the front surface of the semiconductor substrate 30 (the surface of the n ⁺ -type source region 5 and the p ^{+ +} -type contact region 6), a conductive material that makes ohmic contact with the semiconductor substrate 30 is provided. A layer 11 is provided. The JFET region 3a (the n-type current diffusion region 3) is exposed in the second contact hole 10b. Inside the second contact hole 10b, on the front surface of the semiconductor substrate 30 (the surface of the JFET region 3a), a conductive layer 21 that makes Schottky contact with the semiconductor substrate 30 is provided. By arranging the conductive layers 11 and 21 in this manner, one plane SBD 20 is arranged in each unit cell A of the MOSFET.

Specifically, a plane SBD 20 exhibiting a rectifying action by Schottky contact between the JFET region 3a and the conductive layer 21 is arranged between the gate electrodes 9 adjacent to each other across the JFET region 3a. The plane SBD 20 includes a p ⁺⁺ -type contact region 6, first to third p ⁺ -type regions 7, 41, 42, an n-type current spreading region 3, an n ⁻ -type drift region 2, and an n ⁺ -type starting substrate 1 (n ⁺ ) of the MOSFET. When a forward bias is applied to the parasitic pin diode including the drain region, the transistor is turned on at a lower voltage than the parasitic pin diode and earlier than the parasitic pin diode. Therefore, by providing the planar SBD 20 on the JFET region 3a between the gate electrodes 9, the parasitic pin diode operation of the MOSFET is suppressed.

Two gate electrodes 9 adjacent to each other with the plane SBD 20 interposed therebetween, and ohmic contacts (electrical contact parts between the semiconductor unit and the conductive layer 11) of the gate electrodes 9 on the opposite side to the plane SBD 20 side. One unit cell A of the MOSFET is configured. In FIG. 1, the conductive layer 11 in ohmic contact with the semiconductor substrate 30 and the conductive layer 21 in Schottky contact with the semiconductor substrate 30 are indicated by different hatchings (the same applies to FIG. 11). In FIG. 1, reference characters R _JFET and R _D denote a MOSFET JFET resistance (resistance of the JFET regions 3a to 3c) and a MOSFET drift resistance (resistance of the n ⁻ -type drift region 2), respectively.

The source electrode 12 is provided on the front surface of the semiconductor substrate 30 so as to be embedded in the first and second contact holes 10a and 10b. Source electrode 12 is in contact with conductive layer 11, and is electrically connected to n ⁺ -type source region 5 and p ⁺⁺ -type contact region 6 via conductive layer 11. The source electrode 12 is in contact with the conductive layer 21 and is electrically connected to the JFET region 3a via the conductive layer 21. Source electrode 12 and conductive layers 11 and 21 are electrically insulated from gate electrode 9 by interlayer insulating film 10. A drain electrode 13 is provided on the back surface of the n ⁺ type starting substrate 1 (the back surface of the semiconductor substrate 30), which is an n ⁺ type drain region.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 2 to 7 are cross-sectional views illustrating the semiconductor device according to the first embodiment in a state in which the semiconductor device is being manufactured. First, as shown in FIG. 2, an n ⁺ type starting substrate (starting wafer) 1 serving as an n ⁺ type drain region is prepared. Next, n ⁻ -type silicon carbide layer 31 is epitaxially grown on the front surface of n ⁺ -type starting substrate 1. Next, as shown in FIG. 3, third and fourth p ⁺ -type regions 42 and 43 are selectively formed in the surface layer of n ⁻ -type silicon carbide layer 31 by photolithography and ion implantation of p-type impurities. .

Next, by photolithography and ion implantation of an n-type impurity, an n-type region (hereinafter, referred to as a part of the n-type current diffusion region 3) is formed in the surface layer of the n ⁻ -type silicon carbide layer 31 over the entire active region, for example. An n-type partial region 51 is formed. At this time, the depth of the n-type portion region 51 is preferably more deeper than the depth of the 3,4P ⁺ -type region 43, the drain side of the 3,4P ⁺ -type region 42, 43 (n ⁺ -type starting substrate 1 Side) The whole is covered with an n-type partial region 51. The portion of n ⁻ -type silicon carbide layer 31 closer to the drain than n-type partial region 51 becomes n ⁻ -type drift region 2. The order of forming the n-type partial region 51 and the third and fourth p ⁺ -type regions 42 and 43 may be interchanged.

Next, as shown in FIG. 4, n ^- further n on the -type silicon carbide layer 31 ^- -type silicon carbide layer is epitaxially grown, n ^- the thickness of the -type silicon carbide layer 31. Next, in a portion 31a where the thickness of the n ⁻ -type silicon carbide layer 31 is increased by photolithography and ion implantation of a p-type impurity, a portion facing the lower third p ⁺ -type region 42 in the depth direction Z is in depth reaching the first 3p ⁺ -type region 42 is selectively formed a first 2p ⁺ -type region 41.

Next, by photolithography and ion implantation of an n-type impurity, the n ⁻ -type silicon carbide layer 31 is increased in thickness to a portion 31 a, for example, over the entire active region at a depth reaching the lower n-type partial region 51. , An n-type partial region 52 to be a part of the n-type current diffusion region 3 is formed. The impurity concentration of n-type partial region 52 is substantially the same as that of n-type partial region 51. The order of forming the n-type partial region 52 and the second p ⁺ -type region 41 may be interchanged.

Next, as shown in FIG. 5, n ^- on type silicon carbide layer 31, further the n ^- -type silicon carbide layer is epitaxially grown, n ^- the thickness of the -type silicon carbide layer 31. Next, in the portion 31b where the thickness of the n ⁻ -type silicon carbide layer 31 is increased by photolithography and ion implantation of a p-type impurity, a portion facing the lower second p ⁺ -type region 41 in the depth direction Z is The first p ⁺ -type region 7 is selectively formed at a depth reaching the second p ⁺ -type region 41.

Next, by photolithography and ion implantation of n-type impurities, the n ⁻ -type silicon carbide layer 31 is increased in thickness to a portion 31 b, for example, over the entire active region at a depth reaching the lower n-type partial region 52. , An n-type partial region 53 which becomes a part of the n-type current diffusion region 3 is formed. The impurity concentration of n-type partial region 53 is substantially the same as n-type partial regions 51 and 52. The order of forming the n-type partial region 53 and the first p ⁺ -type region 7 may be interchanged.

Instead of increasing the thickness of the -type silicon carbide layer 31, n ^{- -} n described above with the two n-type silicon carbide layer having the same impurity concentration as the n-type current diffusion region 3 on the -type silicon carbide layer 31 is epitaxially grown Is also good. In this case, ion implantation for forming n-type partial regions 52 and 53 can be omitted, and first and second p ⁺ -type regions 7 and 41 may be formed each time each n-type silicon carbide layer is epitaxially grown. .

Next, as shown in FIG. 6, an n-type or p-type silicon carbide layer 32 is epitaxially grown to a predetermined thickness on n ⁻ -type silicon carbide layer 31. Here, a case where p-type silicon carbide layer 32 is epitaxially grown will be described as an example. Thus, semiconductor substrate (semiconductor wafer) 30 is formed by sequentially depositing n ⁻ -type silicon carbide layer 31 and silicon carbide layer 32 on the front surface of n ⁺ -type starting substrate 1. First to fourth p ⁺ -type regions 7, 41 to 43 formed by ion implantation are selectively embedded in n ⁻ -type silicon carbide layer 31 of semiconductor substrate 30.

Next, as shown in FIG. 7 repeats the process for a set of photolithography and ion implantation under different conditions, the surface layer of the p-type silicon carbide layer 32, n ⁺ -type source region 5, p ⁺⁺ type Contact region 6 and n-type partial region 54 are selectively formed. The n-type partial region 54 becomes a part of the n-type current diffusion region 3. The order of forming the n ⁺ type source region 5, the p ⁺⁺ type contact region 6, and the n type partial region 54 may be changed.

At this time, the n ⁺ type source region 5 and the p ^{+ +} type contact region 6 are formed at a depth reaching the first lower p ⁺ type region 7. The n-type partial region 54 is formed at a depth reaching the lower n-type partial region 53. A portion of the p-type silicon carbide layer 32 other than the n ⁺ -type source region 5, the p ^{+ +} -type contact region 6 and the n-type partial region 54 becomes the p-type base region 4. The n-type partial regions 51 to 54 are connected in the depth direction Z to form an n-type current diffusion region 3.

Next, heat treatment (activation annealing) for activating impurities is performed on all regions formed by ion implantation. Next, for example, the front surface of the semiconductor substrate 30 is thermally oxidized to form the gate insulating film 8. Next, a polysilicon layer is deposited (formed) on the gate insulating film 8 and patterned, and a portion of the polysilicon layer to be the gate electrode 9 is replaced with the n ⁺ -type source region 5 and the n ⁺ -type source region 5 of the p-type base region 4. It is left only on the surface of the portion sandwiched with the mold current diffusion region 3.

Next, an interlayer insulating film 10 is deposited (formed) on the entire front surface of the semiconductor substrate 30 so as to cover the gate electrode 9. Next, the interlayer insulating film 10 and the gate insulating film 8 are partially removed by photolithography and etching, and the first and the first layers reaching the semiconductor substrate 30 through the interlayer insulating film 10 and the gate insulating film 8 in the depth direction Z. Two contact holes 10a and 10b are formed. The n ⁺ -type source region 5 and the p ^{+ +} -type contact region 6 are exposed in the first contact hole 10a, and the n-type current diffusion region 3 (JFET region 3a) is exposed in the second contact hole 10b.

  Next, a conductive layer 11 that is in ohmic contact with the semiconductor substrate 30 is formed inside the first contact hole 10a. A conductive layer 21 that is in Schottky contact with the semiconductor substrate 30 is formed inside the second contact hole 10b. Next, the source electrode 12 is formed on the front surface of the semiconductor substrate 30 in the active region so as to be embedded in the first and second contact holes 10a and 10b. The drain electrode 13 is formed on the entire back surface of the semiconductor substrate 30. Thereafter, the semiconductor wafer is diced (cut) into individual chips to complete the MOSFET shown in FIG.

Next, a layout of a connection portion (fifth p ⁺ type region 44) between the third p ⁺ type region 42 and the fourth p ⁺ type region 43 when viewed from the front surface side of the semiconductor substrate 30 will be described. FIG. 8 is a plan view showing a layout of a part of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate. 9 and 10 are plan views illustrating another example of the layout of a part of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate. 8 to 10 show a layout of a fifth p ⁺ -type region 44 connecting the third p ⁺ -type region 42 and the fourth p ⁺ -type region 43.

As described above, the third and fourth p ⁺ -type regions 42 and 43 are arranged in a linear layout extending in the first direction X. Further, the fourth p ⁺ -type region 43 is arranged in a portion (JFET region 3c) sandwiched between the adjacent third p ⁺ -type regions 42. That is, the third and fourth p ⁺ -type regions 42 and 43 are alternately and repeatedly arranged in the second direction Y and arranged in a striped layout extending in the first direction X. The third p ⁺ -type region 42 and the fourth p ⁺ -type region 43 are connected by a fifth p ⁺ -type region 44.

The fifth p ⁺ -type region 44 is arranged in a linear layout extending in the second direction Y between the adjacent third p ⁺ -type region 42 and fourth p ⁺ -type region 43, and the third 3, 4 p ⁺ -type region 42 , 43. A plurality of fifth p ⁺ -type regions 44 may be provided separately from each other between the same adjacent third p ⁺ -type region 42 and fourth p ⁺ -type region 43. The width (width in the first direction) L4 of the fifth p ⁺ type region 44 may be, for example, the same as the width L2 of the third p ⁺ type region 42. 8 to 10, the third to fifth p ⁺ -type regions 42 to 44 are shown by hatching. 8 to 10, the portion other than the hatching is the n-type current diffusion region 3 (JFET region 3c).

The arrangement of the fifth p ⁺ type region 44 can be variously changed. For example, as shown in FIG. 8, the fifth p ⁺ -type regions 44 may be adjacent to each other in the second direction Y with the third p ⁺ -type region 42 interposed therebetween. In this case, a portion of the n-type current diffusion region 3 that faces the first p ⁺ -type region 7 in the depth direction Z (see FIG. 1) has a third p ⁺ -type region 42 and a region orthogonal to the third p ⁺ -type region 42. The fifth p ⁺ -type region 44 adjacent to the third p ⁺ -type region 42 is arranged in a cross-shaped layout. The diagonal length L5 of the rectangular planar shape portion (cross-shaped central portion) 42a of the third p ⁺ type region 42 facing the fifth p ⁺ type region 44 in the second direction Y is set to about 8 μm or less. .

Further, as shown in FIG. 9, the fifth p ⁺ -type regions 44 may be arranged so as not to be adjacent to each other in the second direction Y with the third p ⁺ -type region 42 interposed therebetween. In this case, a portion of the n-type current diffusion region 3 that faces the first p ⁺ -type region 7 in the depth direction Z (see FIG. 1) has a third p ⁺ -type region 42 and a region orthogonal to the third p ⁺ -type region 42. And the fifth p ⁺ -type region 44 is arranged in a T-shaped layout. A rectangular divided portion 42c of the third p ⁺ -type region 42, which is obtained by dividing a rectangular planar shape portion 42b facing the fifth p ⁺ -type region 44 in the second direction Y by a center line Y 'parallel to the second direction Y. Is set to about 8 μm or less.

Also, when placed between the 3p ⁺ -type region 42 and a second 5p ⁺ -type region 44 to the cross-shaped layout (see FIG. 8), of the 3p ⁺ -type region 42, the 5p ⁺ -type region in a second direction Y The substantially rectangular planar shape portion 42a 'facing the 44 is notched so that each vertex of the substantially rectangular planar shape portion 42a' is recessed toward the center of the substantially rectangular planar shape portion 42a '( A planar shape having a notch 45 may be used. Accordingly, the diagonal length of the substantially rectangular planar shape portion 42a 'of the third p ⁺ type region 42 facing the fifth p ⁺ type region 44 in the second direction Y (the substantially rectangular planar shape portion 42a') The distance L5 ′ between the cutouts 45 located on the diagonal lines of the third and fifth p ⁺ -type regions 42 and 44 can be shorter than the widths L2 and L4 of the third and fifth p ⁺ -type regions 42 and 44.

Even when the first 3p ⁺ -type region 42 and a second 5p ⁺ -type region 44 is arranged (see FIG. 9) to the T-shaped layout, of the 3p ⁺ -type region 42, the 5p ⁺ -type region in a second direction Y The rectangular planar shape portion 42 a ′ facing the 44 may have a planar shape having a cutout 45 at each vertex in contact with the fifth p ⁺ type region 44. In this case, a rectangular planar portion 42b of the third p ⁺ -type region 42 facing the fifth p ⁺ -type region 44 in the second direction Y is divided by a center line Y 'parallel to the second direction Y. The length L6 of the diagonal line of the divided portion 42c can be shorter than the widths L2 and L4 of the third and fifth p ⁺ -type regions 42 and 44. FIG. 10 shows a case where the planar shape of the notch 45 is circular, but the planar shape of the notch 45 can be variously changed.

As described above, according to the first embodiment, in the n-type current diffusion region, the p-type base region, the n ⁺ -type source region, and the p ^{+ +} -type contact region are directly in contact with these regions. is disposed immediately below the first 1p ⁺ -type region whose width is determined depending on the conditions of these regions (impurity concentration and width), is arranged a 2, 3P ⁺ -type region is stacked in multiple stages in the depth direction ing. The first 2, 3P ⁺ -type regions arranged in multiple stages immediately below the first 1p ⁺ -type region, the parasitic JFET (n-type current diffusion region in contact with the drift region in the unit cell, the 2p ⁺ -type region and the 4p ⁺ -type region , Or between the second p ⁺ -type region and the fourth p ⁺ -type region), the number of regions is increased to two or more, so that the n-type current diffusion during the forward operation of the parasitic pin diode is increased. The spreading resistance of carriers in the region is determined by the width of the lowermost p ⁺ -type region (third p ⁺ -type region). Further, the width of the lowermost p ⁺ -type region does not depend on the conditions of the p-type base region, the n ⁺ -type source region, and the p ^{+ +} -type contact region, and is therefore about 8 μm or less, which is smaller than the width of the first p ⁺ -type region. can do. Therefore, the spreading resistance of carriers in the n-type current diffusion region during forward operation of the parasitic pin diode can be suppressed, and a large current (for example, an operating current of about 3000 A / cm ² or more) flows through the parasitic pin diode. Even in this case, the operation of the parasitic pin diode can be suppressed.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 11 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that an n ⁺ -type region having a higher impurity concentration than the n-type current diffusion region 3 (the (Six semiconductor regions) 61 are provided.

The n ⁺ -type region 61 has a depth from the front surface of the semiconductor substrate 30 to the drain-side surface of the lowermost p ⁺ -type region (the third p ⁺ -type region 42) inside the n-type current diffusion region 3. The semiconductor substrate 30 is uniformly arranged in a direction (lateral direction) parallel to the front surface of the semiconductor substrate 30. For example, the n ⁺ -type region 61 may be arranged in the depth direction Z with a thickness t over, for example, the JFET regions 3a and 3b. In this case, the n ⁺ -type region 61 is formed in the first and second p ⁺ -type regions 7 and 41. Touch

As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained. According to the second embodiment, the JFET resistance (the resistance of the JFET region) is reduced by providing the n ⁺ -type region having a higher impurity concentration than the n-type current diffusion region inside the n-type current diffusion region. be able to.

(Example)
Next, the upper limit value of the width L2 of the third p ⁺ type region 42 was verified. FIG. 12 is a characteristic diagram showing a relationship between a distance between a pin diode and a unipolar element arranged on the same semiconductor substrate and a bipolar current. The horizontal axis in FIG. 12 is the distance C between the pin diode 70a and the unipolar element 70b in FIG. The vertical axis in FIG. 12 represents the ratio of the current amount of the bipolar element (not shown) arranged on the semiconductor substrate 75 to the current amount of the unipolar element 70b (= current amount of the bipolar element / current amount of the unipolar element).

If the ratio of the current amount of the bipolar element disposed on the semiconductor substrate 75 to the current amount of the unipolar element 70b (hereinafter, referred to as bipolar current ratio) is less than 10% in the range B1, the forward deterioration due to the pin diode operation occurs. It has been confirmed by the inventor that there is no bipolar current or the amount of bipolar current is small enough to obtain characteristics that can withstand the recommended specifications (such as years of use) of the product. Therefore, when the bipolar current ratio is in the range B2 of 1 × 10 ⁻¹ or more (that is, when the current amount of the bipolar element is 10% or more larger than the current amount of the unipolar element 70b), the bipolar element is sequentially operated by the pin diode operation. It is assumed that direction degradation has occurred.

FIG. 13 is a cross-sectional view showing a cross-sectional structure of a sample used for verification in FIG. The sample shown in FIG. 13 has a unipolar element 70b built in the same semiconductor substrate 75 as a bipolar element (not shown). Semiconductor substrate 75 is a silicon carbide epitaxial substrate obtained by epitaxially growing n ⁻ -type layer 72 on n ⁺ -type starting substrate 71 made of silicon carbide. In the surface layer of the n ⁻ type layer 72 opposite to the n ⁺ type starting substrate 71 side (surface layer on the front surface of the semiconductor substrate 75), two p-type regions 73 are selectively separated from each other. Formed. The width w _JFET of a portion (hereinafter referred to as a JFET region) 74 of the n ⁻ -type layer 72 sandwiched between the two p-type regions 73 was set to 1.0 μm.

A bipolar element, not shown, disposed on the same semiconductor substrate 75 is a vertical element comprising an n-type current diffusion region 3, a p-type base region 4, and an n ⁺ -type source region 5 of a MOSFET according to the present invention (see FIG. 1). Is assumed to be a parasitic npn bipolar transistor (body diode). The pin diode 70a formed by the pn junction of the p-type region 73 with the n ⁻ -type layer 72 and the n ⁺ -type starting substrate 71 is connected to the p-type base region 4 and the first to the first of the MOSFET (see FIG. 1) according to the present invention. It is assumed that this is a parasitic pn diode formed by a pn junction between the 3p ⁺ -type regions 7, 41, and 42 and the n-type current diffusion region 3. It is assumed that the unipolar element 70b including the JFET region 74 and the conductive layer (not shown) is the plane SBD 20 in FIG.

When the bipolar element is turned on in the sample shown in FIG. 13, the bipolar current ratio (the ratio of the amount of current of the bipolar element arranged on the semiconductor substrate 75 to the amount of current of the unipolar element 70b), the pin diode 70a and the unipolar element 70b, Is shown in FIG. The distance C between the pin diode 70a and the unipolar element 70b corresponds to the width L2 of the third p ⁺ -type region 42 of the MOSFET according to the present invention (see FIG. 1). FIG. 12 shows a plurality of results obtained by variously changing the critical current density Jc of the bipolar element. In FIG. 13, the direction of the arrow denoted by reference numeral 76 is the direction in which the pin diode 70a moves away from the unipolar element 70b (that is, the direction in which the distance C between the pin diode 70a and the unipolar element 70b increases).

From the results shown in FIG. 12, it was confirmed that the longer the distance C between the pin diode 70a and the unipolar element 70b, the easier the bipolar current flows. The reason is that the n ⁻ -type layer 72 becomes a resistance by the length of the distance C, and the on-resistance of the unipolar element 70b increases. This result becomes more conspicuous as the critical current density Jc of the bipolar element is increased. However, even when the critical current density Jc of the bipolar element is increased to, for example, about 3000 A / cm ² or more, the pin diode 70a and the unipolar element 70b If the distance C from the substrate is 8 μm or less, it is confirmed that the bipolar current does not flow or the amount of the bipolar current is small enough to say that the forward deterioration due to the operation of the pin diode 70a has not occurred.

Therefore, in the present invention, if the width L2 of the third p ⁺ -type region 42, which is the lowermost p ⁺ -type region of the MOSFET having the planar gate structure, is about 8 μm or less, no bipolar current flows, or the recommended product specifications It can be seen that the current amount of the bipolar current is small enough to obtain characteristics that can withstand (eg, years of use).

  In the above, the present invention can be variously modified without departing from the spirit of the present invention. In each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are variously set according to required specifications and the like. Further, in each of the above-described embodiments, the MOS gates of the unit cells are linearly arranged in a direction parallel to the front surface of the semiconductor substrate (that is, the MOS gates of all the unit cells arranged are arranged in a striped layout). This is described as an example, but the present invention is not limited to this, and a plurality of MOS gates may be arranged in a matrix layout when viewed from the front surface of the semiconductor substrate.

That is, when arranging a plurality of MOS gate in a matrix layout, p ⁺ -type region opposed to the p ⁺⁺ -type contact region in the depth direction inside the n-type current diffusion region (first 1～3P ⁺ -type region) Are arranged in a ring surrounding the periphery of the JFET region. Therefore, similar to the above embodiments, the same effect can be obtained if the width of the lowermost p ⁺ -type region is set to about 8 μm or less. Further, when the MOS gates of the plurality of unit cells are arranged in a matrix layout, the surface area of the plane SBD may be smaller than when the plurality of MOS gates are arranged in a stripe layout.

In each embodiment described above, MOSFET of each unit depending on the conditions of the (p-type base region, n ⁺ -type source regions and the p ⁺⁺ -type contact region) width is determined by the p ⁺ -type region (second 1p ⁺ In the example described above, two p ⁺ -type regions (second and third p ⁺ -type regions) independent of the conditions of each part of the MOSFET are arranged in multiple stages on the drain side of the MOSFET region). Even when three or more p ⁺ -type regions that do not depend on the conditions of each part of the MOSFET are arranged in multiple stages, the p ⁺ -type region located at the most drain side of the three or more p ⁺ -type regions The same effect can be obtained by setting the width of the (lowest p ⁺ type region) to about 8 μm or less.

  Further, in each of the above-described embodiments, an example is described in which a silicon carbide epitaxial substrate obtained by epitaxially growing a silicon carbide layer on a starting substrate made of silicon carbide is used. Each region to be formed may be formed on the silicon carbide substrate by, for example, ion implantation or the like. Further, the present invention has a similar effect when applied to a wide band gap semiconductor (for example, gallium (Ga) or the like) other than silicon carbide. Further, the present invention can be similarly established even when the conductivity types (n-type and p-type) are reversed.

  As described above, the semiconductor device according to the present invention is useful for a MOS type semiconductor device having a planar gate structure in which a planar SBD is built in the same semiconductor substrate, and is particularly suitable for a MOSFET.

Reference Signs List 1 n ⁺ type starting substrate 2 n ⁻ type drift region 3 n type current diffusion region 3 a to 3 c JFET region 4 p type base region 5 n ⁺ type source region 6 p ⁺⁺ type contact region 7, 41 to 44 n type current diffusion P ⁺ -type region formed (embedded) by ion implantation in the region 8 gate insulating film 9 gate electrode 10 interlayer insulating film 10a, 10b contact hole 11, 21 conductive layer 12 source electrode 13 drain electrode 20 planar SBD
Reference Signs List 30 semiconductor substrate 31 n ⁻ -type silicon carbide layer 31a, 31b Increased thickness of n ⁻ -type silicon carbide layer 32 p-type silicon carbide layer 42a, 42a ′, 42b Lower second p ⁺ -type region in second direction A rectangular planar portion facing the connecting portion (fifth p ⁺ type region) 42c A rectangular divided portion of the rectangular planar portion facing the connecting portion in the second direction of the lowermost p ⁺ type region 45 the lower p ⁺ -type region, the notch of the rectangular planar shape portion facing the connecting portion in the second direction 51 to 54 n-type partial regions 61 n ⁺ -type region a unit cell of a MOSFET L1 to L4, L11 n-type current formed by ion implantation into the diffusion region (buried) width of the p ⁺ -type region L5, L5 ', L6 of the bottom p ⁺ -type region, the portion of the rectangular plane shape which faces the connecting portion in the second direction Y Length of diagonal line of cell pitch of L10 MOSFET A direction (first direction) in which each region and the gate electrode constituting the XMOS gate extend linearly in a direction parallel to the front surface of the semiconductor substrate
Y A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction)
Y 'A center line parallel to the second direction of the lowermost p ⁺ -type region of the rectangular planar shape facing the connecting portion in the second direction Z Depth direction

Claims (7)

A semiconductor substrate made of a semiconductor having a wider band gap than silicon;
A first semiconductor layer of a first conductivity type, which is provided on the front surface of the semiconductor substrate and is made of a semiconductor having a wider band gap than silicon;
A first conductivity type first semiconductor region having a higher impurity concentration than the first semiconductor layer, provided on a surface layer of the first semiconductor layer opposite to the semiconductor substrate side;
A second conductivity-type second semiconductor layer made of a semiconductor having a wider band gap than silicon, provided on the first semiconductor layer on a side opposite to the semiconductor substrate side and covering the first semiconductor region;
A second semiconductor region of a first conductivity type that penetrates the second semiconductor layer in a depth direction and reaches the first semiconductor layer;
The second semiconductor layer is selectively provided separately from the second semiconductor region, and penetrates the second semiconductor layer in a depth direction to reach the first semiconductor layer, and a part of the first semiconductor region is formed. A third semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor layer;
A second semiconductor type fourth semiconductor region which is a portion of the second semiconductor layer other than the second semiconductor region and the third semiconductor region;
A gate electrode provided on a surface of a portion of the fourth semiconductor region interposed between the second semiconductor region and the third semiconductor region via a gate insulating film;
A first electrode electrically connected to the second semiconductor region and the fourth semiconductor region;
A transistor having a second electrode provided on the back surface of the semiconductor substrate;
A Schottky barrier diode including: the third semiconductor region; and a conductive layer that is in Schottky contact with the third semiconductor region and is electrically connected to the first electrode.
With
Inside the first semiconductor region,
An impurity, which is opposed to the second semiconductor region and the fourth semiconductor region in a depth direction and covers surfaces of the second semiconductor region and the fourth semiconductor region on the side of the second electrode, which are more impurity than the fourth semiconductor region; A fifth semiconductor region of a second conductivity type having a high concentration;
It is arranged closer to the second electrode than the fifth semiconductor region, is opposed to the fifth semiconductor region in the depth direction, and is stacked in multiple stages from the first electrode side to the second electrode side. Two or more first buried regions of a second conductivity type having an impurity concentration higher than that of the fourth semiconductor region and in contact with each other to form a laminated structure;
A second buried of a second conductivity type having a higher impurity concentration than the fourth semiconductor region, which is arranged apart from the fifth semiconductor region and the first buried region and faces the third semiconductor region in a depth direction. Area and
The lowermost buried region and the second buried region, which are disposed between the lowermost buried region of the first buried region closest to the second electrode and the second buried region, And a third buried region of the second conductivity type having a higher impurity concentration than the fourth semiconductor region, which are connected to each other, are selectively provided, respectively.
An uppermost buried region of the first buried region, which is disposed closest to the first electrode, is in contact with the fifth semiconductor region,
The width of the lowermost buried region is smaller than the width of the fifth semiconductor region. The critical current density of the parasitic diode including the fourth semiconductor region, the fifth semiconductor region, the first buried region, the third semiconductor region, the first semiconductor layer, and the semiconductor substrate is 3000 A / cm ² or more;
The cell pitch of the transistor is 10 μm,
2. The semiconductor device according to claim 1, wherein the width of the lowermost buried region is 8 μm or less. The gate electrode is arranged in a linear layout extending in a first direction parallel to a front surface of the semiconductor substrate;
The first buried region and the second buried region are arranged in a linear layout extending in the first direction.
The third buried region is arranged in a linear layout extending in a second direction parallel to the front surface of the semiconductor substrate and orthogonal to the lowermost buried region. Make a layout,
3. The semiconductor according to claim 1, wherein a length of a diagonal line of a rectangular planar portion of the lowermost buried region facing the third buried region in the second direction is 8 μm or less. 4. apparatus. The gate electrode is arranged in a linear layout extending in a first direction parallel to a front surface of the semiconductor substrate;
The first buried region and the second buried region are arranged in a linear layout extending in the first direction.
The third buried region is arranged in a linear layout extending in a second direction parallel to the front surface of the semiconductor substrate and orthogonal to the lowermost buried region. Of the layout,
A diagonal length of a rectangular divided portion obtained by dividing a rectangular planar shape portion of the lowermost embedded region facing the third embedded region in the second direction by a center line parallel to the second direction is: The semiconductor device according to claim 1, wherein the thickness is 8 μm or less.   The rectangular planar shape portion of the lowermost buried region facing the third buried region in the second direction is formed by setting a vertex of the rectangular planar shape portion to a center side of the rectangular planar shape portion. 5. The semiconductor device according to claim 3, wherein the semiconductor device has a planar shape having a notched portion cut out so as to be concave.   6. The semiconductor device according to claim 1, further comprising a sixth semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region inside the first semiconductor region. 7. Semiconductor device. The second semiconductor region is disposed in contact with the second semiconductor region on the side opposite to the third semiconductor region with respect to the second semiconductor region, reaching the first semiconductor layer through the second semiconductor layer in the depth direction. A seventh semiconductor region of a second conductivity type having an impurity concentration higher than that of the second semiconductor layer;
The fourth semiconductor region is a portion of the second semiconductor layer other than the second semiconductor region, the third semiconductor region, and the seventh semiconductor region,
The fifth semiconductor region is selectively provided to face the second semiconductor region, the fourth semiconductor region, and the seventh semiconductor region in a depth direction, and further includes the second semiconductor region, the fourth semiconductor region. 7. The semiconductor device according to claim 1, wherein the semiconductor device covers a surface of the seventh semiconductor region on the second electrode side. 8.

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