JP2012235001A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an electric field applied to a gate insulating film when a reverse bias is applied, and to reduce the channel resistance while making the distribution of the on current uniform in a semiconductor device having a MOS structure.SOLUTION: A MOSFET has a plurality of well regions 20 formed in a drift layer 2, and a region contiguous to the region between the well regions 20 in the drift layer 2 becomes a junction termination extension (JTE) region. A source region 12, a source extension region 10 connected with the source region 12, and a junction field effect transistor (JFET) extension region 11 connected with a JFET region are formed in each well region 20, and the region between the source extension region 10 and the JFET extension region 11 becomes a channel region. The JFET extension regions 11 of adjoining well regions 20 are separated from each other.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a gate electrode of a metal / insulator / semiconductor junction structure (MOS structure) and a manufacturing method thereof.

  Silicon carbide (SiC) semiconductor devices, especially field-effect transistors (MOSFETs) having metal / insulator / semiconductor junction structure (MOS structure) gate electrodes, are applied to power electronics. In addition, low loss is required from the viewpoint of energy saving of onboard equipment. In particular, reduction of loss (on-loss) during energization, that is, reduction of on-resistance is an important issue. As a method for reducing the on-resistance, it is possible to reduce the channel resistance and the resistance (JFET resistance) in the JFET (Junction Field Effect Transistor) region.

  For example, Patent Document 1 discloses a configuration in which a silicon carbide semiconductor device including a MOSFET is provided with an impurity diffusion layer into which impurities of a conductivity type different from a well are introduced so as to straddle adjacent wells and a JFET region therebetween. ing. According to this configuration, the MOSFET channel length is shortened and the resistance of the JFET region is suppressed. Therefore, even if the JFET region is reduced for the purpose of miniaturizing the element structure, an increase in the resistance of the JFET region can be suppressed, and rather the on-resistance of the semiconductor device can be reduced.

JP 2006-303323 A

  In the silicon carbide semiconductor device of Patent Document 1, the impurity diffusion layer is formed across adjacent wells and a JFET region therebetween, and the impurity region is disposed on the entire JFET region. Thereby, the effect of reducing the JFET resistance can be obtained, but when a reverse bias is applied to the semiconductor device, the electric field applied to the gate insulating film in contact with the upper surface of the impurity diffusion layer is increased. Therefore, there is a risk that the reliability of the gate insulating film is lowered.

  The present invention has been made to solve the above-described problems. In a semiconductor device having a MOS structure, the electric field applied to the gate insulating film when a reverse bias is applied is suppressed, and the channel resistance is reduced and the on-current distribution is reduced. The purpose is to equalize.

  A semiconductor device according to the present invention includes a semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, and a second conductivity type well region selectively formed on an upper surface of the drift layer. , A JFET region which is a region adjacent to the well region of the drift layer, a first conductivity type source region selectively formed on the upper surface of the well region, and the source region in the upper surface of the well region A first conductivity type source extension region formed in a part of the first conductivity type, a first conductivity type JFET extension region formed in a part of the upper surface of the well region over the JFET region, and the drift A gate electrode disposed on the layer via a gate insulating film and extending over the JFET extension region and the source extension region. A plurality of well regions including the source region, the source extension region, and the JFET extension region, and the gate electrode straddles the adjacent well region and the JFET region therebetween. The JFET extension regions of each of the adjacent well regions formed in this manner are separated from each other.

  According to the semiconductor device of the present invention, since the JFET extension region is not formed over the entire upper portion of the JFET region in contact with the gate insulating film, the electric field generated in the gate insulating film when a reverse bias is applied is suppressed, and the reliability of the device is improved. . Further, since the region between the JFET extension region and the source extension region that can be formed by ion implantation in the same process becomes a channel region, the channel length can be defined by the mask width of the ion implantation. Therefore, the channel length can be made short and uniform, and the channel resistance can be reduced and the on-current distribution can be made uniform.

1 is a top view of a silicon carbide semiconductor device according to a first embodiment. FIG. 4 is a plan view of a cross section near the surface in the silicon carbide semiconductor device according to the first embodiment. 1 is a longitudinal sectional view of an end portion of a silicon carbide semiconductor device according to a first embodiment. 3 is a longitudinal sectional view of a unit cell of the silicon carbide semiconductor device according to the first embodiment. FIG. FIG. 3 is a plan view of a cross section near the surface of a unit cell of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a plan view of a cross section near the surface of a unit cell of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a plan view of a cross section near the surface of a unit cell of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a plan view of a cross section near the surface of a unit cell of the silicon carbide semiconductor device according to the first embodiment. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. It is a figure which shows an example of the numerical calculation result of the impurity concentration distribution of the well region edge part vicinity of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a figure which shows an example of the numerical calculation result of the impurity concentration distribution of the well region edge part vicinity of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a figure which shows an example of the numerical calculation result of the impurity concentration distribution of the well region edge part vicinity of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. It is a figure which shows the electron micrograph before thinning process of the implantation mask in manufacture of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a figure which shows the electron micrograph of the implantation mask after the thinning process in manufacture of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a figure which shows the dimensional change of the implantation mask before and behind the thinning process in the manufacture of the silicon carbide semiconductor device according to the first embodiment. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process for the silicon carbide semiconductor device according to the first embodiment. FIG. 1 is a longitudinal sectional view of a silicon carbide semiconductor device according to a first embodiment. 1 is a longitudinal sectional view of a silicon carbide semiconductor device according to a first embodiment. 1 is a longitudinal sectional view of a silicon carbide semiconductor device according to a first embodiment. 1 is a longitudinal sectional view of a silicon carbide semiconductor device according to a first embodiment. 1 is a longitudinal sectional view of a silicon carbide semiconductor device according to a first embodiment. 1 is a longitudinal sectional view of a silicon carbide semiconductor device according to a first embodiment. FIG. 6 is a longitudinal sectional view of a silicon carbide semiconductor device according to a second embodiment. FIG. 10 is a longitudinal sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 6 is a longitudinal sectional view of a silicon carbide semiconductor device according to a third embodiment. FIG. 12 is a longitudinal sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the third embodiment. FIG. 12 is a longitudinal sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the third embodiment. FIG. 6 is a longitudinal sectional view of a silicon carbide semiconductor device according to a fourth embodiment. FIG. 14 is a longitudinal sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the fourth embodiment. FIG. 14 is a longitudinal sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the fourth embodiment.

  Embodiments of the present invention will be described below. In this specification, a semiconductor element having a MOS structure is defined as a “semiconductor device” in a narrow sense, and a power module incorporating the semiconductor element is also defined as a “semiconductor device” in a broad sense. As a power module, for example, an inverter formed by mounting a semiconductor element, a free wheel diode connected in reverse parallel thereto, a control circuit for generating and applying a gate voltage of the semiconductor element, and the like on a lead frame and sealing it There are modules.

  In each embodiment, a semiconductor device formed using a silicon carbide semiconductor will be described. However, the present invention relates to a semiconductor device formed using another semiconductor (wide band gap semiconductor) having a larger band gap than silicon. It can also be applied to. Examples of wide band gap semiconductors include gallium nitride, aluminum nitride, and diamond in addition to silicon carbide.

  In the following description, n-type is defined as "first conductivity type" and p-type is defined as "second conductivity type" as the impurity conductivity type, but the first conductivity type is p-type and the second conductivity type is n-type. It may be.

<Embodiment 1>
FIG. 1 is a top view of the silicon carbide semiconductor device according to the first embodiment. Specifically, it schematically shows a configuration of a MOSFET chip top surface including a plurality of unit cells of switching elements having a MOS structure. ing.

  As shown in FIG. 1, a gate pad 45 for applying a gate voltage from an external control circuit (not shown) is disposed in the vicinity of the center of one side of the upper surface of the MOSFET chip 5. A source pad 41 is disposed at the center of the upper surface of the chip 5. The source pad 41 is formed on the active region where a plurality of unit cells, which are the minimum unit structure of the MOSFET, are arranged so as to be connected to the source regions of the plurality of unit cells. It will be connected in parallel. Around the source pad 41, a gate wiring 44 connected to the gate pad 45 is formed. The gate voltage applied to the gate pad 45 from the external control circuit is supplied to the gate electrode of each unit cell through the gate pad 45 and the gate wiring 44.

  Note that in a MOSFET as a normal product, electrodes for temperature sensors and current sensors are often formed on the chip 5, but the presence or absence of these electrodes is not shown here because it is not related to the present invention. ing. In the present invention, the position and number of the gate pads 45, the shape of the gate wiring 44, the shape and number of the source pads 41, and the like may be arbitrary, and there may be various cases for each product.

  FIG. 2 is a plan view schematically showing a cross section of the silicon carbide MOSFET according to the first embodiment in the vicinity of the surface (upper surface) inside the silicon carbide. An active region in which a plurality of MOSFET unit cells are arranged in parallel includes a second conductivity type termination well region 27, a second conductivity type termination low resistance region 28, and a second conductivity type JTE (Junction Termination Extension) region 50. Surrounding and spaced from the JTE region 50, the first conductivity type field stop region 13 further surrounds them.

  Although the present embodiment shows a configuration in which unit cells isolated from each other are arranged in the active region of the silicon carbide semiconductor, a configuration in which unit cells are connected in a comb shape without being isolated from each other may be used. In FIG. 2, each unit cell is square, and the unit cells are arranged in a staggered manner by shifting the unit cell pitch by a half cycle for each row of adjacent unit cells. The shape and arrangement may be arbitrary. For example, the unit cells may be rectangular or hexagonal, and may be arranged at equal pitches in the vertical and horizontal directions.

  FIG. 3 is a vertical cross-sectional view of the end portion of the MOSFET according to the present embodiment, for example, a cross-sectional view along the line AA shown in FIG. FIG. 4 is a longitudinal sectional view of an active region where a MOSFET unit cell is arranged, for example, a sectional view taken along line BB in FIG.

  As shown in FIGS. 3 and 4, the silicon carbide MOSFET according to the present embodiment includes a first conductivity type semiconductor substrate 1 and a first conductivity type drift layer 2 which is an epitaxial layer formed thereon. It is formed using an epitaxial substrate. A drain electrode 43 is disposed on the back surface (lower surface) of the semiconductor substrate 1 via an ohmic electrode 42. A plurality of second conductivity type well regions 20 are selectively formed on the surface (upper surface) portion of the drift layer 2. On the surface of the well region 20, a first conductivity type source region 12 and a second conductivity type well contact region 21 that penetrates the source region 12 and reaches the well region 20 therebelow are formed. In the drift layer 2, a portion adjacent to the well region 20 (region sandwiched between the well regions 20 adjacent to each other) becomes a JFET region.

  A source extension region 10 of the first conductivity type that is connected to the source region 12 (a part thereof overlaps with the source region 12) is selectively formed on the surface portion in the well region 20. A first conductivity type JFET extension region 11 is selectively formed at the end of the well region 20 so as to be connected to the JFET region (a part of which overlaps the JFET region). In the MOSFET of this embodiment, a region sandwiched between the source extension region 10 and the JFET extension region 11 is a channel region.

  The present invention is characterized in that the JFET extension region 11 is disposed separately for each well region 20 without straddling adjacent well regions 20. That is, the JFET extension regions 11 formed at the end portions of the well regions 20 are not connected to each other, and an interval is provided.

  Therefore, the JFET region includes a portion 6 surrounded by the JFET extension region 11 and a portion 7 surrounded by the well region 20 therebelow, as indicated by a dotted line in FIG. Hereinafter, the portion 6 of the JFET region surrounded by the JFET extension region 11 is referred to as a “first JFET region”, and the portion 7 of the JFET region surrounded by the well region 20 is referred to as a “second JFET region”.

  As shown in FIG. 2, the second conductivity type termination well region 27 is formed on the surface of the drift layer 2 on the outer peripheral portion (termination portion) of the chip 5 so as to surround the active region where the plurality of unit cells are arranged. A second conductive type terminal low resistance region 28 is formed on the surface of the terminal well region 27. A second conductivity type JTE region 50 is formed so as to surround the termination well region 27, and a first conductivity type field stop region 13 is formed outside the JTE region 50.

  On the drift layer 2, a gate insulating film 30 covering a part of the well region 20 and the termination well region 27, and a field oxide film 31 covering a region other than the gate insulating film 30, such as the outer peripheral portion of the chip 5, Is formed. On the gate insulating film 30, a gate electrode 35 extending above the channel region (region between the source extension region 10 and the JFET extension region 11) is formed. The gate insulating film 30 and the gate electrode 35 cover the JFET region and are disposed across the adjacent well region 20.

  The gate electrode 35 is covered with an interlayer insulating film 32, and a source pad 41 functioning as a source electrode and a gate wiring 44 are disposed on the interlayer oxide film 32. The source pad 41 is connected to the source region 12 and the well contact region 21 of each unit cell through an ohmic electrode 40 through a contact hole formed in the interlayer insulating film 32. The source pad 41 is also connected to the terminal low resistance region 28 through the ohmic electrode 40 through a contact hole formed in the interlayer insulating film 32.

  As shown in FIG. 3, the gate electrode 35 extends to the field oxide film 31 on the outer periphery of the chip 5, and is connected to the gate wiring 44 through a contact hole formed in the interlayer oxide film 32. Thereby, the gate electrode 35 is electrically connected to the gate pad 45 shown in FIG.

  Here, as shown in FIG. 4, the center of the JFET region between the well regions 20 is defined as a unit cell boundary. That is, a MOSFET element formed using one well region 20 belongs to each unit cell.

  5 to 7 are plan views each schematically showing a cross section near the surface of the unit cell. 5 shows a cross section taken along line CC in FIG. 4, FIG. 6 shows a cross section taken along line DD in FIG. 4, and FIG. 7 shows a cross section taken along line EE in FIG.

  As shown in these drawings, in each unit cell, a square well region 20 is provided, and a source region 12 and a well contact region 21 are formed at the center thereof. The source extension region 10 is formed in a frame shape straddling the outer periphery of the source region 12, and the JFET extension region 11 is formed in a frame shape straddling the outer periphery of the well region 20.

  As described above, the channel region of the MOSFET is a surface portion of a region surrounded by the source extension region 10 and the JFET extension region 11. That is, the distance L1 between the source extension region 10 and the JFET extension region 11 shown in FIG. 6 is the channel length of the MOSFET. Although the gate electrode 35 shown in FIG. 5 is formed so as to cover the channel region, the gate electrode 35 straddles adjacent unit cells as shown in FIG. It has a mesh pattern in which holes are opened.

  Here, the width of the first JFET region 6 surrounded by the JFET extension regions 11 (that is, the interval between adjacent JFET extension regions 11) is L2. Since the boundary of the unit cell is the central portion of the JFET region, the distance between the end of the JFET extension region 11 and the end of the unit cell is expressed as L2 / 2 as shown in FIG. If the width of the second JFET region 7 surrounded by the well region 20 is L3, the distance between the end of the source region 12 and the end of the unit cell is expressed as L3 / 2 as shown in FIG.

  As described above, the present invention is characterized in that the JFET extension region 11 is isolated for each well region 20. That is, the width L2 of the first JFET region 6 is larger than 0 (L2> 0). Although various aspects of the relationship between the width L2 of the first JFET region 6 and the width L3 of the second JFET region 7 can be considered, details will be described later.

  A further characteristic point of the present invention is that the distance between the end of the JFET extension region 11 and the end of the well region 20, that is, a value half of the absolute value of the difference between L2 and L3 (| L2-L3 | / 2). Is constant within each unit cell and equal in all unit cells.

  5 to 7, each element of the unit cell is drawn as a square whose four corners are each 90 degrees. However, when such a pattern is formed by using the photoengraving technique, the element shown in FIG. (Corresponding to the same cross section as 6), the corner portion of each element is often rounded. In that case, considering the roundness generated at the outer peripheral corner portion of the source extension region 10, the channel length is made constant by intentionally rounding the inner peripheral corner portion of the JFET extension region 11 surrounding the source extension region 10. Is desirable.

  For example, as shown in FIG. 8, the radius of curvature of roundness generated by the photoengraving process at the outer corner of the source extension region 10 is r1. At this time, the JFET extension region 11 has an inner peripheral corner portion having a radius of curvature r2 that is larger by L1 than r1 (r2-r1 = L1), and the center position of r2 overlaps the center position of r1. The shape of the extension region 11 is designed. Then, the channel length in the unit cell becomes constant at all positions including the corner portions of the source extension region 10 and the JFET extension region 11. As a result, the distribution of current (ON current) that flows during conduction is made uniform, and a semiconductor device having desired characteristics can be obtained.

  Hereinafter, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment shown in FIGS. 1 to 4, specifically, the MOSFET, will be described with reference to FIGS. 9 to 35. In addition, the longitudinal cross-sectional views (FIGS. 9, 10, and 14 to 35) showing each process correspond to an arbitrary position where a large number of unit cells are arranged, not including the outer peripheral portion (terminal portion) of the chip 5. Specifically, an area of a portion straddling two unit cells is shown.

  First, a first conductivity type semiconductor substrate 1 is prepared. The surface of the semiconductor substrate 1 may be inclined by 8 ° or less with respect to the c-axis direction, or may not be inclined, and may have any plane orientation. Here, the semiconductor substrate 1 is a silicon carbide semiconductor. However, when the present invention is applied to other wide band gap semiconductors (for example, gallium nitride, aluminum nitride, diamond, etc.), the semiconductor substrate 1 made of a material corresponding thereto. Is used.

A drift layer 2 of the first conductivity type is formed on the semiconductor substrate 1 by epitaxial crystal growth. The impurity concentration of the first conductivity type in the drift layer 2 is, for example, about 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the thickness of the drift layer 2 is, for example, about 4 μm to 200 μm.

  Thereafter, an implantation mask 100 having an opening on the formation region of the well region 20 as shown in FIG. 9 is formed by using a photolithography technique. The implantation mask 100 may be formed of a photoresist or a silicon oxide film patterned using the photoresist as a mask. Then, ion implantation of impurities is performed using the implantation mask 100 to form the second conductivity type well region 20. Although illustration is omitted, the termination well region 27 (FIG. 3) may be formed at the same time as this ion implantation.

  During this implantation, the semiconductor substrate 1 may not be positively heated, or may be heated at 100 ° C. to 800 ° C. The impurity to be implanted is preferably nitrogen or phosphorus when the conductivity type of the impurity region to be formed (here, well region 20) is n-type, and aluminum or boron is preferable when the conductivity type is p-type. It is.

Further, the depth (thickness) of the well region 20 from the surface of the drift layer 2 is set to, for example, about 0.3 μm to 2.0 μm within a range not exceeding the bottom surface of the drift layer 2. The impurity concentration of the well region 20 is set to, for example, about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ in a range exceeding the impurity concentration of the drift layer 2. However, only in the vicinity of the outermost surface of well region 20, the impurity concentration of the second conductivity type of well region 20 is the first conductivity type of drift layer 2 in order to increase the conductivity in the channel region of the silicon carbide semiconductor device. It may be lower than the impurity concentration.

  Here, when the well region 20 is formed by using the implantation mask 100 having high perpendicularity, since the impurity is laterally scattered by the high acceleration energy implantation in the drift layer 2, the shape of the well region 20 is particularly intentional. If the substrate is not implanted into the substrate obliquely, a reverse taper shape is formed as shown in FIG. 10 (in the well region 20, a shape whose bottom is narrower than the top (for example, FIG. 14) is a “taper shape”, and the reverse shape. (For example, FIG. 10 is defined as “reverse taper shape”). The spread distance L4 of the implanted impurities in the lateral direction from the end of the implantation mask 100 can extend from around 0.3 μm to beyond.

For example, FIG. 11 shows the result of numerical calculation of the distribution when Al is implanted as an impurity into a silicon carbide substrate at an acceleration energy of 500 keV and a dose of 8 × 10 ¹³ cm ⁻² . FIG. 12 shows the distribution of Al in the horizontal direction (direction parallel to the surface of the substrate) at a depth of 0.5 μm from the substrate surface of the well region 20 formed under the conditions. For example, assuming that the impurity concentration of the first conductivity type of the drift layer 2 is 1 × 10 ¹⁶ cm ⁻³ , as can be seen from FIGS. 11 and 12, the drift layer 2 is about 0.3 μm from the mask edge under the above conditions. A well region 20 is formed extending to the side, and the well region 20 has an inversely tapered shape.

  FIG. 13 shows the same result obtained when multi-stage injection (multiple injections with different acceleration energies) is performed so that the Al concentration is substantially uniform over a depth of about 0.8 μm from the surface. However, it can be seen that the well region 20 extends in the horizontal direction by about 0.3 μm deep from the surface of the drift layer 2 and has an inversely tapered shape.

  Thus, when the well region 20 has an inversely tapered shape, the shielding effect of the JFET region is promoted by the depletion layer spreading from the vicinity of the bottom end of the well region 20 when the MOSFET is turned off, and the electric field generated in the gate insulating film 30 is reduced. The reliability of the semiconductor device is improved.

  In addition, when the well region 20 is formed by ion implantation of impurities such that a deep position away from the surface of the drift layer 2 has a concentration peak, as shown in FIG. The high concentration region) remains at a deep position away from the surface of the drift layer 2. That is, since the high concentration region does not reach the shallow portion of the well region 20 serving as the channel region, a MOSFET having a low threshold voltage and a low channel resistance can be obtained.

  By the way, the shape of the implantation mask 100 can be tapered, and this often occurs (for the implantation mask 100, a shape whose upper portion is narrower than the bottom (for example, FIG. 14) is defined as a “taper shape”). When the implantation mask 100 is tapered, the well region 20 formed by ion implantation of impurities using the implantation mask 100 as a mask has a tapered shape as shown in FIG.

  Further, when the well region 20 is formed by ion implantation of impurities such that a deep position away from the surface of the drift layer 2 has a concentration peak, the influence of impurities reaching the drift layer 2 through the inclined side surface of the implantation mask 100. As shown in FIG. 15, it is possible to obtain a distribution in which the second conductivity type impurity high concentration region 29 in the well region 20 reaches the vicinity of the surface at the end of the drift layer 2. That is, the position of the impurity concentration peak in the depth direction of the well region 20 is a deep position in a portion other than the end portion, but the position becomes shallow near the end portion and reaches the upper surface of the well region 20.

  In this case, since the high concentration region 29 extends to a shallow portion of the well region 20 serving as a channel region, an effect of suppressing the extension of the depletion layer from the drift layer 2 into the well region 20 can be obtained when the MOSFET is turned on. In this case, the leakage current is reduced in a MOSFET having a short channel length (for example, less than 1 μm).

  As described above, the shape of the well region 20 varies depending on the shape of the implantation mask 100 and ion implantation conditions. For convenience, the following steps will be mainly described based on the structure of FIG.

  After the formation of the well region 20, as shown in FIG. 16, the implantation mask 100 is thinned by performing a very small amount of isotropic etching on the surface of the implantation mask 100 (first thinning process). . For example, when the implantation mask 100 is made of a photoresist, the first thinning process can be performed by a process in a gas phase with oxygen plasma or a process in a liquid phase with an organic solvent such as acetone. In the case where the implantation mask 100 is made of a silicon oxide film, it can be carried out by processing in a liquid phase with buffered hydrofluoric acid or dilute hydrofluoric acid.

  The etching amount of the surface of the implantation mask 100 in the first thinning process may be 0.1 to 1 μm, more preferably 0.1 to 0.5 μm (since both the left and right surfaces of the implantation mask 100 are etched, the implantation mask 100 is etched). 100 is thinned by twice this etching amount). Hereinafter, the implantation mask 100 subjected to the first thinning process is referred to as an “implantation mask 100a”.

  Here, when the implantation mask 100a is a photoresist, hard baking is performed at 200 ° C. or higher so as not to be dissolved by a developing solution for subsequent photolithography. Note that the photoresist is slightly reduced when hard baking is performed, so that the implantation mask 100a is further thinned. Alternatively, instead of the above-described hard baking, the surface of the photoresist implantation mask 100a is covered with a silicon oxide film 33 having a thickness of about 100 nm as shown in FIG. 17, so that it is not immersed in the developer for subsequent photolithography. It may be.

  Subsequently, an implantation mask 103 made of a photoresist is formed by photolithography as shown in FIG. FIG. 19 shows a case where the silicon oxide film 33 is provided on the surface of the implantation mask 100a as shown in FIG.

  Then, as shown in FIG. 20, the implantation mask 103 is thinned by performing a very small amount of isotropic etching on the surface of the implantation mask 103 (second thinning process). Since the implantation mask 103 is a photoresist, the second thinning process can be performed by a process in a gas phase with oxygen plasma or a process in a liquid phase with an organic solvent such as acetone. FIG. 21 shows a case where the silicon oxide film 33 is provided on the surface of the implantation mask 100a as shown in FIG. Hereinafter, the implantation mask 103 subjected to the second thinning process is referred to as an “implantation mask 103a”.

  The region under the implantation mask 103a becomes a channel region, and the width of the implantation mask 103a defines the channel length, that is, the distance between the source extension region 10 and the JFET extension region 11. In order to position the channel region in the well region 20, the implantation mask 103 a is preferably formed in a region on the well region 20 so as not to straddle the end of the well region 20.

  Here, in the case where the implantation mask 100a is a hard-baked photoresist, as shown in FIG. 20, the implantation mask 100a is slightly reduced by the second thinning process, and the thinning further proceeds, but the implantation is performed as shown in FIG. When the mask 100a is covered with the silicon oxide film 33 or when the implantation mask 100a is a silicon oxide film, the width of the implantation mask 100a is not changed.

  FIG. 22 is an electron micrograph of the implantation mask 103 before the second thinning process (immediately after formation), and FIG. 23 is an electron micrograph of the implantation mask 103a after the second thinning process. The implantation mask 103 shown in FIG. 22 is a photoresist pattern having a width of 1.2 μm. By performing oxygen plasma treatment as the second thinning treatment, an implantation mask 103a having a width of about 0.5 μm shown in FIG. 23 was obtained. It can be seen that there is no deterioration in the shape of the side surface of the implantation mask 103a after the second thinning process.

  FIG. 24 is a diagram showing the relationship between the dimension when the implantation mask 103 is formed (after photolithography) and the dimension of the implantation mask 103a after the second thinning process (after etching). This is an experimental result when oxygen plasma treatment is performed as the second thinning treatment. By performing the second thinning process, an implantation mask 103a having a width of 1 μm or less, which is the resolution limit of photolithography, could be produced.

  It was also confirmed that the dimensional variation of the implantation mask 103a after the thinning was very small. This means that the width of the implantation mask 103a after thinning can be accurately controlled by adjusting the width of the implantation mask 103 and the oxygen plasma treatment time. In order to reduce the sacrifice amount of the resist thickness and increase the dimensional accuracy of the implantation mask 103a, it is desirable to form a fine implantation mask 103 in advance by photolithography and shorten the oxygen plasma treatment time.

  However, if the implantation mask 103 having a sufficiently narrow width can be formed without performing the thinning process, the second thinning process may be omitted. In that case, higher dimensional accuracy can be obtained than when the thinning process is performed.

Next, as shown in FIG. 25, the first conductivity type source extension region 10 and the JFET extension region 11 are simultaneously formed by ion implantation of impurities using the implantation masks 100a and 103a as a mask. The depths of the source extension region 10 and the JFET extension region 11 are set so that their bottom surfaces do not exceed the bottom surface of the well region 20. The impurity concentration of the source extension region 10 and the JFET extension region 11 is, for example, about 5 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ in a range exceeding the impurity concentration of the well region 20. It is not depleted. Further, this ion implantation is performed with an acceleration energy such that the source extension region 10 and the JFET extension region 11 are not connected to each other due to lateral scattering during the implantation.

  The impurity distribution in the substrate depth direction of the source extension region 10 and the JFET extension region 11 may be uniform, or may be a low concentration on the upper side (substrate surface side) and a high concentration on the lower side (back side of the substrate). Good. Particularly in the latter case, in the MOS structure composed of the gate electrode 35, the gate insulating film 30 and the drift layer 2, the quality of the gate insulating film 30 deteriorates due to the influence of crystal defects caused by ion implantation on the surface of the drift layer 2. Can be prevented, and a high-quality MOS structure can be realized.

  As shown in FIG. 25, the source extension region 10 is located inside the well region 20. The JFET extension region 11 is connected to the drift layer 2 while including the end portion of the well region 20 (that is, straddling the end portion of the well region 20).

  L1 and L2 shown in FIG. 25 correspond to those shown in FIG. 6 or FIG. The distance L1 between the source extension region 10 and the JFET extension region 11 is the channel length of the MOSFET, which is substantially determined by the width of the implantation mask 103a. As described with reference to FIGS. 22 to 24, the width of the implantation mask 103a can be accurately controlled.

  The channel length of a conventional MOSFET (a structure without the source extension region 10 and the JFET extension region 11) is the size and alignment accuracy of both the mask for forming the well region and the mask for forming the source region. Depends on. That is, the channel length was determined by photolithography and ion implantation twice.

  On the other hand, the channel length of the MOSFET of this embodiment is determined by one photolithography, thinning process and ion implantation of the implantation mask 103a. Therefore, the uniformity of the channel length in the unit cell and the channel length in the wafer are determined. Uniformity can be remarkably improved as compared with the prior art, and a device with little variation in electrical characteristics can be obtained.

  Further, since the first conductivity type impurity for forming the JFET extension region 11 is not implanted immediately below the implantation mask 100a, the adjacent JFET extension regions 11 are separated from each other with a distance L2. That is, the JFET region includes a portion of the first JFET region 6 surrounded by the JFET extension region 11 and a portion of the second JFET region 7 surrounded by the well region 20. Since the impurity concentration of the entire surface portion of the JFET region is not increased, the electric field applied to the gate insulating film 30 when the MOSFET is turned off is relaxed, and the reliability of the device is improved.

  Further, the end position of the well region 20 adjacent to the second JFET region 7 is determined by the width of the implantation mask 100, and the end position of the JFET extension region 11 adjacent to the first JFET region 6 thins the implantation mask 100. This is determined by the width of the implantation mask 100a formed in a self-aligned manner. As a result, as described above, the distance between the end of the JFET extension region 11 and the end of the well region 20, that is, the absolute value of the difference between the interval L2 of the JFET extension region 11 and the interval L3 of the well region 20 (FIG. 7) ( The value of | L2−L3 | / 2) is constant in each unit cell, and is equal in all unit cells. As a result, an imbalance of the electric field applied to the gate insulating film 30 does not occur when the MOSFET is turned off, and the reliability of the device is improved.

  When the well region 20 having the tapered shape shown in FIG. 15 and the structure in which the high concentration region 29 reaches the surface is formed, the end of the JFET extension region 11 on the channel region side is the surface portion of the well region 20 as shown in FIG. May be connected to the high concentration region 29. According to this configuration, since the extension of the depletion layer extending from the JFET extension region 11 to the channel region is suppressed when the MOSFET is on, the short channel effect is suppressed. Therefore, it becomes possible to set the channel length shorter, and it is also possible to achieve both high threshold voltage and low on-resistance of the MOSFET.

  When the inverted tapered well region 20 shown in FIG. 10 is formed, as shown in FIG. 27, the well region adjacent to the second JFET region 7 rather than the interval L2 between the JFET extension regions 11 adjacent to the first JFET region 6. The interval L3 of 20 may be shortened. According to this configuration, when the MOSFET is turned off, the influence of the JFET extension region 11 having a relatively high impurity concentration on the electric field intensity distribution is mitigated by the shielding effect by the depletion layer extending from the end of the well region 20. As a result, the electric field applied to the gate insulating film 30 immediately above the JFET region is further relaxed, and the effect of improving the reliability of the MOSFET is obtained.

  After that, an implantation mask (photoresist or silicon oxide film) having a predetermined shape is formed on the drift layer 2 by photolithography and a JTE region 50 (FIG. 3) is formed by ion implantation of a second conductivity type impurity. .

Subsequently, an implantation mask having a predetermined shape is formed on the drift layer 2 and ions of a first conductivity type are ion implanted to form the source region 12 (FIG. 28) and the field stop region 13 (FIG. 3). The depth of the source region 12 is set so that the bottom surface thereof does not exceed the bottom surface of the well region 20, and the impurity concentration value is in a range exceeding the impurity concentration value of the well region 20, for example, 1 × 10 ¹⁷ cm. ^-3 to 1 × 10 ²¹ cm ^-3 or so.

  Further, in order to realize good metal contact between the well region 20 and the source pad 41, a well contact region 21 having a second conductivity type impurity concentration higher than the impurity concentration of the well region 20 is formed by ion implantation. This ion implantation is desirably performed by heating the drift layer 2 to a temperature of 150 ° C. or higher. Thereby, the well contact region 21 having a low sheet resistance is formed.

  Simultaneously with the well contact region 21, the terminal conductive low resistance region 28 (FIG. 3) may be formed by ion implantation. By providing the termination low resistance region 28 in the termination well region 27, the parasitic resistance in the termination well region 27 can be reduced, and for example, a termination structure with excellent dV / dt resistance can be obtained. Of course, the terminal low-resistance region 28 may be formed in a separate process from the well contact region 21.

  Here, as shown in FIG. 29, the impurity of the drift layer 2 is formed below the JFET region (the first JFET region 6 and the second JFET region 7) and the well region 20 by ion-implanting the first conductivity type impurity to the entire surface of the substrate. The first conductivity type current control layer 8 having an impurity concentration higher than the concentration may be formed. When the current control layer 8 is provided, the resistance of the JFET region is reduced, so that the on-resistance of the MOSFET is reduced and the avalanche breakdown occurring between the well region 20 and the drift layer 2 is more stable when a reverse bias is applied. The effect which becomes is also acquired.

The impurity concentration of the current control layer 8 is lower than the maximum impurity concentration of the second conductivity type in the well region 20 and higher than the impurity concentration of the first conductivity type in the drift layer 2. The value is set to about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , for example. The impurity concentration distribution in the depth direction of the current control layer 8 may not be uniform.

  The current control layer 8 may be formed at any timing before and after each of the above steps after the drift layer 2 is formed. Alternatively, the current control layer 8 may be formed simultaneously with the epitaxial growth of the drift layer 2. In that case, the impurity of the first conductivity type to be introduced is increased during the epitaxial growth of the drift layer 2, and the upper portion of the drift layer 2 is grown as the current control layer 8 in the epitaxial growth.

  Thereafter, the implanted impurities are electrically treated by performing a heat treatment for about 0.5 minutes to 60 minutes in an inert gas atmosphere such as argon or nitrogen or in a vacuum at a temperature in the range of 1500 ° C. to 2200 ° C. To activate. This heat treatment may be performed in a state where the surface of the drift layer 2 or the surface of the drift layer 2 and the back surface of the semiconductor substrate 1 and their end surfaces are covered with a film made of carbon. By doing so, it is possible to prevent the surface of the drift layer 2 from being roughened by etching due to residual moisture or residual oxygen in the apparatus during the heat treatment.

  Next, a silicon oxide film is formed on the surface of the drift layer 2 by thermal oxidation, and the thermal oxide film is removed with hydrofluoric acid, whereby the altered layer on the surface of the drift layer 2 is removed to obtain a clean surface. Thereafter, a silicon oxide film is deposited on the drift layer 2 by, for example, a CVD (Chemical Vapor Deposition) method and patterned to form a field oxide film 31 covering a portion other than the active region. The film thickness of the field oxide film 31 may be about 0.5 μm to 2 μm.

Further, the gate insulating film 30 is formed by forming a silicon oxide film on the surface of the drift layer 2 by, for example, a thermal oxidation method or a deposition method. If necessary, the gate insulating film 30 may be subjected to a heat treatment in a nitrogen gas atmosphere such as NO or N ₂ O or an ammonia atmosphere, or a heat treatment in an inert gas such as argon.

  Thereafter, polysilicon as a material for the gate electrode 35 is deposited by the CVD method and patterned by photolithography and etching to form the gate electrode 35. The polysilicon constituting the gate electrode 35 preferably contains phosphorus or boron and has a low sheet resistance. Phosphorus and boron may be incorporated during the polysilicon film formation, or may be activated by ion implantation and subsequent heat treatment. Further, the gate electrode may be a multilayer film of polysilicon, metal, and intermetallic compound.

  Note that the gate electrode 35 is not formed in the region on the source region 12. In order to reduce the on-resistance of the MOSFET, it is desirable that the contact resistance between the source region 12 and the ohmic electrode 40 be low. For this purpose, it is necessary to increase the impurity concentration of the first conductivity type in the source region 12. On the other hand, since it is difficult to form a high-quality gate insulating film 30 on the surface of the high impurity concentration source region 12 formed by ion implantation, the gate electrode 35 and the gate insulating film 30 are formed on the high impurity concentration source region 12. When the MOS structure is formed by forming the gate, problems such as an increase in gate leakage current occur. Therefore, it is desirable that the gate electrode 35 is not formed on the source region 12 and the upper surface thereof is connected to the ohmic electrode 40 or the interlayer oxide film 32.

  Next, an interlayer insulating film 32 is deposited by a CVD method or the like. Then, contact holes (source contact holes and well contact holes) reaching the surfaces of the source region 12, the well contact region 21 and the termination well region 27 are formed in the interlayer oxide film 32 by, for example, dry etching. At this time, a contact hole (gate contact hole) reaching the surface of the gate electrode 35 may be simultaneously formed in the interlayer oxide film 32. As a result, the process steps can be simplified and the cost for manufacturing the chip can be reduced.

  Subsequently, an ohmic electrode 40 is formed on the surface of silicon carbide (source region 12, well contact region 21, and termination well region 27) exposed at the bottom of each contact hole of interlayer insulating film 32. The ohmic electrode 40 is a layer for obtaining ohmic contact between the source region 12, the well contact region 21 and the terminal low-resistance region 28 and the source pad 41 to be formed later.

  As a method for forming the ohmic electrode 40, for example, a metal film mainly composed of Ni is formed on the entire surface of the substrate including the inside of the contact hole, and Ni and silicon carbide react by applying heat treatment at 600 to 1100 ° C. There is a method in which silicide is formed, and then the excess metal layer on the interlayer insulating film 32 is removed by wet etching using nitric acid, sulfuric acid, hydrochloric acid, a mixed solution thereof with hydrogen peroxide, or the like. Further, after the excess metal film is removed, the heat treatment may be performed again. By making the temperature at this time higher than the previous heat treatment, it is possible to obtain the ohmic electrode 40 that can realize ohmic contact with lower contact resistance.

  The ohmic electrode 40 may be formed of an intermetallic compound (silicide) using the same metal, or an intermetallic compound using a different metal depending on the conductivity type of silicon carbide to be connected. . In order to reduce the on-resistance of the MOSFET, it is important that the ohmic contact resistance between the ohmic electrode 40 and the source region 12 of the first conductivity type is low. Further, the well region 20 is fixed to the ground potential, This is because the contact resistance between the ohmic electrode 40 and the second conductivity type well contact region 21 is required to be sufficiently low in order to improve the forward characteristic of the built-in body diode. Each of the intermetallic compounds using a plurality of metals can be selectively formed by patterning a metal film for forming each intermetallic compound using a photoengraving technique.

  In the process of forming the ohmic electrode 40, the ohmic electrode 42 may be formed on the back surface of the semiconductor substrate 1 by the same process. By providing the ohmic electrode 42, good ohmic contact can be obtained between the semiconductor substrate 1 and the drain electrode 43 to be formed later.

  If a gate contact hole has already been formed in the previous step and the gate electrode 35 is polysilicon, silicide is also formed in the portion of the gate electrode 35 exposed to the gate contact hole in the step of forming the ohmic electrode 40. Is done. If a gate contact hole has not yet been formed, a gate contact hole is subsequently formed in the interlayer oxide film 32 by photolithography and etching.

  Subsequently, a wiring material made of Al, Ag, Cu, Ti, Ni, Mo, W, Ta and nitrides thereof, or a laminated film thereof or an alloy thereof is formed on the interlayer oxide film 32 including the inside of the contact hole. The gate wiring 44, the gate pad 45, and the source pad 41 are formed by patterning them by sputtering or vapor deposition. Further, a drain electrode 43 is formed by forming a metal film such as Ti, Ni, Ag, or Au on the ohmic electrode 42 on the back surface of the semiconductor substrate 1.

  Through the above steps, the MOSFET having the configuration shown in FIG. 30 is formed, and the silicon carbide MOSFET having the configuration shown in FIGS. 3 and 4 can be obtained.

  FIG. 31 shows a configuration when the well region 20 is tapered as shown in FIG. FIG. 32 shows a configuration in which the well region 20 is tapered as shown in FIG. 15 and the high-concentration region 29 reaches the surface of the well region 20. FIG. 33 shows a configuration in which the end of the JFET extension region 11 on the channel region side is connected to the high concentration region 29 at the surface of the well region 20 as shown in FIG. FIG. 34 shows a configuration in the case where the well region 20 has a reverse taper shape as shown in FIG. Further, FIG. 35 shows a configuration in which the well region 20 is reversely tapered as shown in FIG. 27 and the interval (L3) of the well region 20 is shorter than the interval (L2) of the JFET extension region 11.

  Although not shown, the surface side of the MOSFET may be covered with a protective film such as a silicon nitride film or polyimide. In that case, openings are formed in regions of the protective film on the source pad 41, the gate wiring 44, and the gate pad 45 so that wirings from an external control circuit can be connected to them.

  As described above, according to the present embodiment, adjacent JFET extension regions 11 are spaced apart from each other with a predetermined interval (L2). That is, the JFET region includes a portion of the first JFET region 6 surrounded by the JFET extension region 11 and a portion of the second JFET region 7 surrounded by the well region 20. Since the impurity concentration of the entire surface portion of the JFET region does not increase, the electric field applied to the gate insulating film 30 during the reverse bias of the MOSFET is relaxed, and a highly reliable semiconductor device can be obtained.

  Since the source extension region 10 and the JFET extension region 11 are formed in the same process (FIG. 25), both have the same impurity concentration distribution in the depth direction. Therefore, it is possible to reduce the on-current variation due to the uniform channel length and to reduce the channel resistance by reducing the channel length. Furthermore, since the distance (| L2-L3 | / 2) between the end of the JFET extension region 11 and the end of the well region 20 is uniform within the unit cell, the gate insulating film 30, the first JFET region 6 and the The electric field distribution in the second JFET region 7 is made uniform, and the reliability of the semiconductor device can be increased.

  Further, the gate electrode 35 is not formed on the source region 12 having a high impurity concentration of the first conductivity type, and the MOS structure is not formed there, so that the gate leakage current can be suppressed. The gate electrode 35 may be formed on the source extension region 10. In this case, the first conductivity type impurity concentration of the source extension region 10 is set to be the first conductivity type impurity concentration of the source region 12 at least on the surface. Should be lower. Thereby, the gate leakage current is also suppressed, and the reliability of the gate insulating film 30 is prevented from being lowered.

  The impurity concentration distribution of the first conductivity type in the source extension region 10 and the JFET extension region 11 is low on the surface side and high on the back side of the substrate, so that it is on the source extension region 10 and the JFET extension region 11. The reliability of the gate insulating film 30 in the MOS structure is improved.

  As shown in FIG. 32, the depletion layer extending from the drift layer 2 to the well region 20 during the ON operation is obtained by adopting a configuration in which the high concentration region 29 having a high impurity concentration of the second conductivity type extends to the surface of the drift layer 2. It is possible to realize a MOSFET that suppresses elongation and has little leakage current. In particular, as shown in FIG. 33, when the high-concentration region 29 includes the end portion of the JFET extension region 11, the extension of the depletion layer from the drift layer 2 and the JFET extension region 11 during the ON operation is suppressed, and the leakage current is small. A MOSFET can be realized.

  On the other hand, as shown in FIGS. 34 and 35, the well region 20 may have an inversely tapered shape. In particular, as shown in FIG. 35, the amount of protrusion of the well region 20 to the second JFET region 7 is made larger than the amount of protrusion of the JFET extension region 11 to the first JFET region 6 side. Application of a high electric field to the semiconductor device is suppressed, and the reliability of the semiconductor device can be increased.

<Embodiment 2>
FIG. 36 is a longitudinal sectional view showing the configuration of the silicon carbide MOSFET which is the semiconductor device according to the second embodiment, and FIGS. 37 to 39 are process diagrams for explaining the manufacturing method thereof.

  As shown in FIG. 36, the MOSFET of the present embodiment has a second conductivity type source pocket region 51 surrounding the source extension region 10 and a second conductivity type JFET pocket region 52 surrounding the JFET extension region 11 as compared with the configuration of FIG. , And a current control region 9 of the first conductivity type connecting the JFET extension region 11 and the second JFET region 7 is provided. The source pocket region 51 is entirely formed over the well region 20, and the JFET pocket region 52 is partially formed over the well region 20.

  According to the MOSFET of the present embodiment, the presence of the source pocket region 51 and the JFET pocket region 52 suppresses the depletion layer from extending from the JFET extension region 11 and the source extension region 10 to the channel region. Therefore, even if the channel length is shortened, it is possible to suppress an increase in leakage current and a decrease in threshold voltage, which can contribute to a reduction in on-resistance due to a shorter channel length and a shorter cell pitch. The first conductivity type current control region 9 serves to prevent the JFET extension region 11 and the second JFET region 7 from being completely separated by the JFET pocket region 52.

  The MOSFET of this embodiment can be formed by the following method. That is, after the step of FIG. 20 (or FIG. 21) shown in the first embodiment, the first conductivity type source extension region 10 and the JFET extension region as shown in FIG. 37 by ion implantation using the implantation masks 100a and 103a. 11 is formed. Then, further thinning processing (third thinning processing) is performed on the implantation masks 100a and 103a by etching using oxygen plasma processing. Hereinafter, the implantation mask 100a and the implantation mask 103a subjected to the third thinning process are referred to as “implantation mask 100b” and “implantation mask 103b”, respectively.

  Thereafter, the source pocket region 51 and the JFET pocket region 52 are formed by ion implantation of the second conductivity type impurity using the implantation masks 100b and 103b as masks as shown in FIG. The depths of the source pocket region 51 and JFET pocket region 52 are set so that their bottom surfaces exceed the bottom surfaces of the source extension region 10 and JFET extension region 11. Thus, the source pocket region 51 and the JFET extension region 52 can be formed in a self-aligned manner with respect to the source extension region 10 and the JFET extension region 11.

  Alternatively, after the step of FIG. 37, ion implantation using the implantation masks 100a and 103a as a mask is performed without performing the third thinning process, and the source extension region 10 is included by utilizing the lateral scattering of impurities. A source pocket region 51 and a JFET pocket region 52 including the JFET extension region 11 may be formed. Alternatively, when ion implantation is performed using the implantation masks 100a and 103a as masks, the source pocket region 51 and the JFET pocket region 52 can also be formed by performing oblique implantation of impurities and rotational implantation (or step implantation) of the substrate. Can do. In that case, the source pocket region 51 and the JFET extension region 52 may be formed before the source extension region 10 and the JFET extension region 11.

  After the formation of the source pocket region 51 and the JFET pocket region 52, as shown in FIG. 39, an implantation mask 108 is formed by photolithography, and the current control region 9 is formed by performing ion implantation. The depth of the current control region 9 is set so as to exceed the bottom surface of the JFET pocket region 52. Further, the impurity concentration of the current control region 9 needs to be higher than the concentration of the second conductivity type impurity of the JFET pocket region 52. However, if it is too high, the electric field strength applied to the gate insulating film 30 becomes high. It is desirable for the region 52 to be small in the range exceeding the concentration of the second conductivity type impurity.

  Thereafter, the same procedure as that shown in FIG. 28 and subsequent drawings in the first embodiment is performed, whereby the MOSFET structure of FIG. 36 is obtained. Also in the present embodiment, the structure shown in FIGS. 10, 14, and 15 may be applied as the well region 20.

  According to the second embodiment, the presence of the source pocket region 51 and the JFET pocket region 52 suppresses the depletion layer from extending from the JFET extension region 11 and the source extension region 10 to the channel region. Therefore, even if the channel length is shortened, it is possible to suppress an increase in leakage current and a decrease in threshold voltage, which can contribute to a reduction in on-resistance due to a shorter channel length and a shorter cell pitch.

  Furthermore, since the bottom surface of the JFET extension region 11 is covered with the JFET pocket region 52 of the second conductivity type, the electric field applied to the gate insulating film 30 when a reverse bias is applied to the semiconductor device can be further relaxed, The reliability of the apparatus can be improved.

<Embodiment 3>
FIG. 40 is a longitudinal sectional view showing the configuration of the silicon carbide MOSFET which is the semiconductor device according to the third embodiment, and FIGS. 41 and 42 are process diagrams for explaining the manufacturing method thereof.

  As shown in FIG. 40, the MOSFET of the present embodiment has a second conductivity type source pocket region 51 covering a part of the bottom surface of the source extension region 10 and a part of the bottom surface of the JFET extension region 11 as compared with the configuration of FIG. And a second conductivity type JFET pocket region 52 for covering each.

  Since part of the bottom surface of the JFET extension region 11 is covered with the JFET pocket region 52 of the second conductivity type, the distance at which the JFET extension region 11 is in contact with the second JFET region 7 is shorter than in the case of the first embodiment. . Therefore, the electric field applied to the gate insulating film 30 when a reverse bias is applied to the semiconductor device can be further relaxed, and the reliability of the device can be improved.

  The MOSFET of this embodiment can be formed by the following method. That is, after the step of FIG. 20 (or FIG. 21) shown in the first embodiment, the second conductivity type source pocket region 53 and the JFET pocket region are implanted as shown in FIG. 41 by ion implantation using the implantation masks 100a and 103a. 52 is formed. Then, implantation masks 100b and 100b are formed by performing further thinning processing (third thinning processing) on the implantation masks 100a and 103a by etching using oxygen plasma treatment.

  Subsequently, the source extension region 16 and the JFET extension region 11 are formed by ion implantation of the first conductivity type impurities using the implantation masks 100b and 103b as masks as shown in FIG. The depths of the source extension region 16 and the JFET extension region 11 are set so that their bottom surfaces do not exceed the bottom surfaces of the source pocket region 53 and the JFET pocket region 52. As described above, the source extension region 10 and the JFET extension region 11 can be formed in a self-aligned manner with respect to the source pocket region 51 and the JFET pocket region 52.

  Thereafter, the MOSFET structure shown in FIG. 40 is obtained by performing the same procedure as that shown in FIG. 28 and subsequent drawings in the first embodiment. Also in the present embodiment, the structure shown in FIGS. 10, 14, and 15 may be applied as the well region 20.

  According to the third embodiment, since a part of the bottom surface of the JFET extension region 11 is covered with the second conductivity type JFET pocket region 52, the distance at which the JFET extension region 11 is in contact with the second JFET region 7 is as follows. It becomes shorter than the case of form 1. Therefore, the electric field applied to the gate insulating film 30 when a reverse bias is applied to the semiconductor device can be further relaxed, and the reliability of the device can be improved.

<Embodiment 4>
FIG. 43 is a longitudinal sectional view showing the configuration of the silicon carbide MOSFET which is the semiconductor device according to the fourth embodiment, and FIGS. 44 and 45 are process diagrams for explaining the manufacturing method thereof.

  As shown in FIG. 43, the MOSFET of the present embodiment is formed in the second conductivity type source pocket region 51 formed in the upper portion of the source extension region 10 and in the upper portion of the JFET extension region 11 with respect to the configuration in FIG. A second conductivity type JFET pocket region 52 is provided.

  According to this configuration, since the channel region can be moved away from the MOS interface (the surface of the well region 20), the influence of the interface state of the MOS interface on the channel region can be reduced. Therefore, channel mobility can be increased and channel resistance can be reduced.

  The MOSFET of this embodiment can be formed by the following method. That is, after the step of FIG. 20 (or FIG. 21) shown in the first embodiment, the second conductivity type source pocket region 53 and the JFET pocket region are implanted as shown in FIG. 44 by ion implantation using the implantation masks 100a and 103a. 52 is formed.

  Subsequently, the source extension region 16 and the JFET extension region 11 are formed by ion implantation of the first conductivity type impurities using the implantation masks 100b and 103b as masks as shown in FIG. The depths of the source extension region 10 and the JFET extension region 11 are such that their bottom surfaces do not exceed the well region 20, and the depths of the source pocket region 55 and the JFET pocket region 56 are such that their bottom surfaces are the source extension region 10. And is set in a range not exceeding the bottom surface of the JFET extension region 11. As described above, the source extension region 10 and the JFET extension region 11 can be formed in a self-aligned manner with respect to the source pocket region 51 and the JFET pocket region 52.

  Note that the source extension region 10 and the JFET extension region 11 may be formed before the source pocket region 51 and the JFET pocket region 52.

  Thereafter, the same procedure as that shown in FIG. 28 and subsequent drawings in the first embodiment is performed, whereby the MOSFET structure of FIG. 43 is obtained. Also in the present embodiment, the structure shown in FIGS. 10, 14, and 15 may be applied as the well region 20.

  According to the fourth embodiment, since the channel region can be moved away from the MOS interface (the surface of the well region 20), the influence of the interface state of the MOS interface on the channel region can be reduced. Therefore, channel mobility can be increased and channel resistance can be reduced.

  In each of the above embodiments, a vertical MOSFET is shown as an example of a semiconductor device according to the present invention. However, the application of the present invention is not limited to this and can be widely applied to switching elements having a MOS structure. For example, in the configuration of FIG. 30, if a collector layer made of the second conductivity type is provided between the semiconductor substrate 1 and the ohmic electrode 42, an IGBT configuration is obtained, but the above-described effects of the present invention can also be obtained in the IGBT.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Drift layer, 5 chip | tip, 6 1st JFET area | region, 7 2nd JFET area | region, 8 Current control layer, 9 Current control area | region, 10 Source extension area | region, 11 JFET extension area | region, 12 Source area | region, 20 Well area | region, 21 Well contact region, 29 high concentration region, 30 gate insulating film, 31 field oxide film, 32 interlayer oxide film, 35 gate electrode, 40, 42 ohmic electrode, 41 source pad, 43 drain electrode, 44 gate wiring, 45 gate pad, 50 JTE region, 51 source pocket region, 52 JFET pocket region.

Claims (17)

A semiconductor substrate;
A first conductivity type drift layer formed on the semiconductor substrate;
A well region of a second conductivity type selectively formed on the upper surface of the drift layer;
A JFET region which is a portion adjacent to the well region in the drift layer;
A first conductivity type source region selectively formed on an upper surface of the well region;
A source extension region of a first conductivity type formed on the upper surface of the well region so as to partially overlap the source region;
A JFET extension region of a first conductivity type formed on the upper surface of the well region so as to partially overlap the JFET region;
A semiconductor device including a gate electrode disposed on the drift layer via a gate insulating film and extending over the JFET extension region and the source extension region;
A plurality of well regions including the source region, the source extension region, and the JFET extension region;
The gate electrode extends over the adjacent well regions and the JFET region therebetween,
A semiconductor device, wherein the JFET extension regions in adjacent well regions are separated from each other. 2. The semiconductor device according to claim 1, wherein the source extension region and the JFET extension region are formed simultaneously by ion implantation in the same process. 3. The semiconductor device according to claim 1, wherein a distance between an end portion on the JFET region side in the well region and an end portion on the JFET region side in the JFET extension region is uniform in a plan view. The first conductivity type impurity concentration of the upper surface portion of the source extension region and the JFET extension region is lower than the first conductivity type impurity concentration of the upper surface portion of the source region,
The semiconductor device according to claim 1, wherein the gate electrode is not formed on the source region. 5. The semiconductor device according to claim 1, wherein the source extension region and the JFET extension region have a higher impurity concentration of the first conductivity type at the bottom than at the top. The high concentration region of the second conductivity type impurity in the well region is located in a deep portion other than the end portion of the well region, and extends from the deep portion to the upper surface portion in the vicinity of the end portion of the well region. 6. The semiconductor device according to any one of items 5. The semiconductor device according to claim 6, wherein the position of the end portion on the source extension region side in the JFET extension region is included in the high concentration region extending to the upper surface portion of the well region. The well region has a reverse taper shape with a wider bottom than the top,
8. The semiconductor device according to claim 1, wherein an end of the well region on the JFET region side protrudes beyond an end of the JFET extension region on the JFET region side. 9. A source pocket region of a second conductivity type formed to overlap the well region so as to surround the source extension region;
9. The semiconductor device according to claim 1, further comprising a second conductivity type JFET pocket region formed to partially overlap the well region so as to surround the JFET extension region. 10. The semiconductor device according to claim 9, further comprising a current control region of a first conductivity type that is formed so as to partially overlap the JFET extension region in the JFET region and connects the JFET extension region to the JFET region below the JFET extension region. A second conductivity type source pocket region formed on the well region so as to cover a part of the bottom of the source extension region;
9. The second conductivity type JFET pocket region formed so as to overlap a part of the well region so as to cover a part of the bottom of the JFET extension region. 9. Semiconductor device. A source pocket region of a second conductivity type formed on the source extension region;
9. The semiconductor device according to claim 1, further comprising a JFET pocket region of a second conductivity type formed on an upper portion of the JFET extension region. The semiconductor device according to claim 1, wherein the semiconductor substrate and the drift layer are wide band gap semiconductors. (A) forming a first mask on a first conductivity type drift layer formed on a semiconductor substrate;
(B) forming a second conductivity type well region in the drift layer by ion implantation using the first mask and defining a JFET region adjacent to the well region under the first mask; ,
(C) a step of thinning the first mask after the step (b);
(D) forming a second mask on the well region while leaving the first mask;
(E) After the steps (c) and (d), a first conductivity type JFET extension connected to the JFET region in the well region by ion implantation using the first mask and the second mask. Forming a region, and forming a source extension region of the first conductivity type in a region sandwiching the second mask from the JFET extension region;
(F) removing the first and second masks;
(G) forming a first conductivity type source region connected to the source extension region in the well region;
(H) forming a gate insulating film and a gate electrode straddling the JFET region, the JFET extension region, and the source extension region on the drift layer. After (e),
(I) The first and second masks are thinned, and then ion implantation using the first and second masks is performed to make the source extension region a deeper second conductivity type source pocket region and a JFET extension. 15. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of forming a JFET pocket region of a second conductivity type deeper than the region. After the steps (c) and (d) and before the step (e),
(I) Forming a second conductivity type source pocket region deeper than the source extension region and a second conductivity type JFET pocket region deeper than the JFET extension region by ion implantation using the first and second masks. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of thinning the first and second masks. After the steps (c) and (d),
(I) A second conductivity type source pocket region shallower than the source extension region and a second conductivity type JFET pocket region shallower than the JFET extension region by ion implantation using the first mask and the second mask. The method of manufacturing a semiconductor device according to claim 14, further comprising: