JP5676923B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an insulated gate semiconductor device having a trench gate structure in which a gate electrode is embedded in a trench and a manufacturing method thereof.

  In power electronics equipment, switching elements such as silicon IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are used as means for switching between execution and stop of power supply for driving a load such as an electric motor. It is used. In the high voltage region from about 1 kV to higher than that, application of silicon carbide MOSFET is also being studied. These switching elements are all insulated gate semiconductor devices.

  In silicon carbide MOSFET, a channel is formed at the interface between silicon carbide and the insulating film. The silicon carbide MOSFET changes the conductivity of the channel by controlling the voltage applied to the gate electrode formed immediately above the insulating film, and between the source electrode and the drain electrode connected to both ends of the channel. Performs switching operation of the flowing current.

  Among silicon carbide MOSFETs used as power semiconductors, vertical MOSFETs are particularly important applications. There are different types of vertical MOSFETs, such as a planar type and a trench type, depending on the gate structure. Here, the trench type MOSFET is referred to as a trench gate type MOSFET.

  Prior art trench gate type MOSFETs and their manufacturing methods are disclosed in, for example, Patent Documents 1 and 2. In the technique disclosed in Patent Document 1, after an n− type epitaxial layer is formed on the inner wall of the trench by an epitaxial growth method, a gate insulating film is formed on the surface of the n− type epitaxial layer, and the trench is filled with the gate electrode film Thus, a gate electrode is formed. With such a structure, it is possible to design the impurity concentration of the n − type epitaxial layer forming the channel separately from the impurity concentration of the n − type epitaxial layer and the p type epitaxial layer in which the trench is formed. In addition, the resistance of the channel portion is reduced and the threshold voltage is lowered.

  In the technique disclosed in Patent Document 2, the trench sidewall is formed into a tapered shape, thermally oxidized to form a thermal oxide film, and then an n-type impurity is implanted from the normal direction of the substrate using the thermal oxide film as a mask. To do. As a result, n-type impurities are implanted through the thermal oxide film at the side surface portion of the trench where the thermal oxide film is thin, and a thin film semiconductor layer is formed in the channel portion. Thereafter, the oxide film is removed, and a gate electrode is formed through the same process as in Patent Document 1. With such a configuration, the thin film semiconductor layer corresponding to the n − type epitaxial layer of the channel portion of Patent Document 1 is formed without epitaxial growth, the resistance of the channel portion is reduced, and the threshold voltage is increased. Is low.

Japanese Patent No. 3419163 JP 2002-261280 A

  In the trench gate type MOSFET disclosed in Patent Document 1, the epitaxial layer of the channel portion is formed by an epitaxial growth process, and the epitaxial growth rate, that is, the growth rate is adjusted between the side surface and the bottom surface of the trench. Since control is required, it cannot be easily manufactured.

  In the technique disclosed in Patent Document 2, it is possible to form a thin film semiconductor layer in the channel portion without going through an epitaxial growth process, but the thickness dimension of the thin film semiconductor layer depends on the taper angle of the trench. The channel mobility of the trench gate type MOSFET is determined when the channel is formed parallel to the crystal plane as described in, for example, “Materials science forum 2007, vol. 556-57, p. 807-p. 810”. It is known that the characteristics are the best. In the trench gate type MOSFET disclosed in Patent Document 2, when the thickness dimension of the thin film semiconductor layer to be formed is determined, the taper angle of the trench necessary for realizing the thin film semiconductor layer having the thickness dimension is determined, so that design is possible. The taper angle is limited.

  For example, in the case of a vertical trench whose side surface is parallel to the thickness direction of the substrate, a thin film semiconductor layer cannot be formed on the side surface of the trench even if impurities are implanted from the normal direction. In order to form the thin film semiconductor layer on the side surface of the trench, it is necessary to perform impurity implantation a plurality of times from an oblique direction, so that it cannot be easily manufactured. Therefore, in the technique disclosed in Patent Document 2, it is difficult to form a channel parallel to the crystal plane as described above, and it is difficult to realize the above-described good channel mobility.

  In the technique disclosed in Patent Document 2, usable substrates are limited, for example, it is necessary to use a (0001-) carbon surface in order to form a thin film semiconductor layer.

  An object of the present invention is to provide a semiconductor device that does not require an epitaxial growth process and is not limited by the taper angle of the trench and the substrate used, and can reduce the resistance of the channel portion and lower the threshold voltage. A manufacturing method and a semiconductor device are provided.

The method for manufacturing a semiconductor device of the present invention includes a step of forming a first conductivity type drift layer by laminating on a surface portion on one side in a thickness direction of a first conductivity type semiconductor substrate, and a thickness direction one side of the drift layer. Forming a base region of the second conductivity type on the surface portion on the side, forming a source region of the first conductivity type on a part of the surface portion on one side in the thickness direction of the base region, and the base region And a step of forming a mask that is laminated on a surface portion on one side in the thickness direction of the source region so as to expose a predetermined portion for forming a trench of the source region, and is exposed through the opening of the mask. through the source region, by ion-implanting an impurity of the first conductivity type in the base region, spread radially outward from the opening of the mask, the effective second than the base region A step of concentration of the impurity conductivity type to form a lower channel layer, after forming the channel layer by reactive ion etching said source region and said base region using said mask, said source region, And a step of forming a trench penetrating the channel layer formed in the base region.

According to another aspect of the present invention, there is provided a semiconductor device manufactured by the above-described method for manufacturing a semiconductor device, wherein the first conductivity type semiconductor substrate and the semiconductor substrate are stacked on a surface portion on one side in the thickness direction. A drift layer of the first conductivity type, a base region of the second conductivity type formed on the surface portion on one side in the thickness direction of the drift layer, and a portion of the surface portion on the one side in the thickness direction of the base region. A first conductivity type source region, and a side surface of the trench penetrating the base region and the source region in the thickness direction, and the diameter of the trench increases from the opening on one side in the thickness direction of the trench toward the bottom surface. spreads outwardly, is provided along the the concentration is low channel layer of effective second conductivity type impurity than the base region, the inner wall including a side surface and a bottom surface of the trench gate An insulating film, a gate electrode provided in contact with the gate insulating film on a radially inner side of the trench, and a gate electrode provided so as to cover the gate electrode, on one side in the thickness direction of the source region and the base region An interlayer insulating film opened so that a part of the surface portion is exposed; a source electrode electrically connecting the source region exposed through the opening of the interlayer insulating film and the base region; and a thickness direction of the semiconductor substrate And a drain electrode provided on the surface portion on the other side.
According to another aspect of the present invention, there is provided a semiconductor device manufactured by the above-described method for manufacturing a semiconductor device, wherein the first conductivity type semiconductor substrate and the semiconductor substrate are stacked on a surface portion on one side in the thickness direction. A drift layer of the first conductivity type, a base region of the second conductivity type formed on the surface portion on one side in the thickness direction of the drift layer, and a portion of the surface portion on the one side in the thickness direction of the base region. A first conductivity type source region, and a side surface of the trench penetrating the base region and the source region in the thickness direction, and the diameter of the trench increases from the opening on one side in the thickness direction of the trench toward the bottom surface. A channel layer extending outward in the direction and having an effective second conductivity type impurity concentration lower than that of the base region, and a gate provided along an inner wall including a side surface and a bottom surface of the trench. An insulating film, a gate electrode provided in contact with the gate insulating film on a radially inner side of the trench, and a gate electrode provided so as to cover the gate electrode, on one side in the thickness direction of the source region and the base region An interlayer insulating film opened so that a part of the surface portion is exposed; a source electrode electrically connecting the source region exposed through the opening of the interlayer insulating film and the base region; and a thickness direction of the semiconductor substrate A drain electrode provided on the surface portion on the other side, and a second conductivity type impurity concentration higher than that of the base region in the base region other than the portion where the source region is formed. And further comprising two base regions.
According to another aspect of the present invention, there is provided a semiconductor device manufactured by the above-described method for manufacturing a semiconductor device, wherein the first conductivity type semiconductor substrate and the semiconductor substrate are stacked on a surface portion on one side in the thickness direction. A drift layer of the first conductivity type, a base region of the second conductivity type formed on the surface portion on one side in the thickness direction of the drift layer, and a portion of the surface portion on the one side in the thickness direction of the base region. A first conductivity type source region, and a side surface of the trench penetrating the base region and the source region in the thickness direction, and the diameter of the trench increases from the opening on one side in the thickness direction of the trench toward the bottom surface. A channel layer extending outward in the direction and having an effective second conductivity type impurity concentration lower than that of the base region, and a gate provided along an inner wall including a side surface and a bottom surface of the trench. An insulating film, a gate electrode provided in contact with the gate insulating film on a radially inner side of the trench, and a gate electrode provided so as to cover the gate electrode, on one side in the thickness direction of the source region and the base region An interlayer insulating film opened so that a part of the surface portion is exposed; a source electrode electrically connecting the source region exposed through the opening of the interlayer insulating film and the base region; and a thickness direction of the semiconductor substrate A drain electrode provided on a surface portion on the other side, and further comprising a bottom surface protective layer formed of a second conductivity type semiconductor layer on the bottom surface of the trench and protecting the gate insulating film. .

According to the method for manufacturing a semiconductor device of the present invention, the first conductivity type drift layer is formed by being laminated on the surface portion on one side in the thickness direction of the first conductivity type semiconductor substrate. A base region of the second conductivity type is formed on the surface portion on one side in the thickness direction of the drift layer. A source region of the first conductivity type is formed on a part of the surface portion on one side in the thickness direction of the base region. A mask is formed which is laminated on the surface portion on one side in the thickness direction of the base region and the source region so as to expose a predetermined portion for forming a trench in the source region. Impurities of the first conductivity type are ion-implanted into the base region through the source region exposed through the mask opening, spread radially outward from the mask opening, and effective second conductivity than the base region. A channel layer having a low type impurity concentration is formed. After the channel layer is formed, the source region and the base region using a mask is reactive ion etching, a trench penetrating the channel layer formed on the source region, and the base region is formed.

When the impurities are ion-implanted, the impurities are implanted so as to spread outward in the radial direction of the opening of the mask, so that an impurity implantation layer is formed in the base region so as to extend over a wider range than the opening of the mask. After that, since the trench is formed by reactive ion etching of the source region and the base region using the same mask, the portion where the channel on the side surface of the trench is formed (hereinafter sometimes referred to as “channel portion”) An impurity implantation layer remains as the channel layer. The channel layer, a first conductivity type impurity in the base region of a second conductivity type so formed is ion-implanted, the low concentration of impurities in the effective second conductivity type than the base region. By providing such a channel layer, the resistance of the channel portion of the semiconductor device can be reduced and the threshold voltage can be lowered.

  Since this channel layer is formed by utilizing the spread of impurities during ion implantation, an epitaxial growth process is not required to form the channel layer, and the taper angle of the trench and the semiconductor substrate to be used are limited. There is nothing. Also, since the impurity is implanted before forming the trench, unlike the case where the impurity is implanted after the trench is formed, protection against the impurity implantation on the bottom surface of the trench is performed so that the impurity is implanted only on the side surface of the trench. There is no need to form a layer. Further, since impurity ion implantation for forming the channel layer and etching for forming the trench are performed with one mask, mask alignment is not necessary, and the number of steps can be reduced. Therefore, an excellent semiconductor device can be easily manufactured as described above.

According to the semiconductor device of the present invention, the side surface of the trench that penetrates the base region and the source region in the thickness direction is constituted by the channel layer. Channel layer toward the bottom from the opening of one side in the thickness direction of the trench, which extends radially outward of the trench, the concentration of impurities in the effective second conductivity type is lower than the base region . Thus the channel section is a portion where a channel is formed in the side surface of the trench, the concentration is low channel layer in the effective impurity of the second conductivity type is provided than the base region, than in the case where the channel layer is not Thus, a semiconductor device having a low resistance in the channel portion and a low threshold voltage can be realized. This semiconductor device is manufactured by the above-described method for manufacturing a semiconductor device according to the present invention, and the channel layer is formed by utilizing the spread when the impurity is implanted. Therefore, an epitaxial growth process is performed to form the channel layer. Is not necessary. Therefore, the semiconductor device of the present invention can be easily manufactured.
According to the semiconductor device of the present invention, the base region further includes a second base region having a concentration of the second conductivity type impurity higher than that of the base region in a portion other than the portion where the source region is formed. This semiconductor device of the present invention can be easily manufactured in the same manner as the semiconductor device of the present invention described above.
In addition, according to the semiconductor device of the present invention, the bottom surface of the trench is further provided with the bottom surface protection layer that is configured by the second conductivity type semiconductor layer and protects the gate insulating film. This semiconductor device of the present invention can be easily manufactured in the same manner as the semiconductor device of the present invention described above.

It is sectional drawing which shows the structure of the trench gate type MOSFET1 which is a semiconductor device in the 1st Embodiment of this invention. FIG. 6 is a cross-sectional view showing a configuration at a stage where the formation of the source region 14 is completed. 6 is a cross-sectional view showing a configuration at a stage where the formation of the etching mask 26 is completed. FIG. It is sectional drawing which shows the structure in the stage which the etching of the silicon oxide layer 25 was complete | finished. 3 is a cross-sectional view showing a configuration at a stage where the formation of a channel layer 16 is completed. FIG. FIG. 6 is a cross-sectional view showing a configuration at a stage where formation of trenches 15 is completed. 6 is a cross-sectional view showing a configuration at a stage where the formation of the interlayer insulating film 19 is completed. FIG. It is sectional drawing which shows the structure of the trench gate type MOSFET2 which is a semiconductor device in the 2nd Embodiment of this invention. 4 is a cross-sectional view showing a configuration at a stage where the formation of the second base region 30 is completed. FIG. It is sectional drawing which shows the structure of the trench gate type MOSFET3 which is a semiconductor device in the 3rd Embodiment of this invention. It is sectional drawing which shows the structure in the stage where formation of the bottom face protective layer 35 was complete | finished. It is sectional drawing which shows the structure of the trench gate type MOSFET50 which is a semiconductor device of the 1st premise technique. It is sectional drawing which shows the structure of 50 A of trench gate type MOSFETs which are the semiconductor devices of the 2nd premise technique. It is sectional drawing which shows the structure in the middle of the manufacturing process of 50 A of trench gate type MOSFETs shown in FIG.

<Prerequisite technology>
Before describing the semiconductor device and the manufacturing method thereof according to the present invention, a semiconductor device and a manufacturing method thereof as a prerequisite technology of the present invention will be described. FIG. 12 is a cross-sectional view showing a configuration of a trench gate type MOSFET 50 which is a semiconductor device of the first prerequisite technology. The trench gate type MOSFET (hereinafter sometimes simply referred to as “MOSFET”) 50 of the first prerequisite technology is a silicon carbide semiconductor device. MOSFET 50 is fabricated on an n + type silicon carbide semiconductor substrate 51 having a (0001−) carbon surface on the surface on one side in the thickness direction, specifically, the upper surface that is the upper surface of FIG. The MOSFET 50 is manufactured as follows.

  First, n − type epitaxial layer 52 and p type epitaxial layer 53 are sequentially grown on the upper surface of silicon carbide semiconductor substrate 51, and then n + type source region 54 is formed in a predetermined region of p type epitaxial layer 53. A trench 55 is formed in a predetermined region of the n + type source region 54 so as to penetrate the n + type source region 54 and the p type epitaxial layer 53 and reach the n − type epitaxial layer 52. Thereafter, a second n − is formed on the inner wall surface of the trench 55, specifically, on the surface of the n + -type source region 54, the p-type epitaxial layer 53 and the n − -type epitaxial layer 2 constituting the inner wall of the trench 55 by an epitaxial growth method. A type epitaxial layer (hereinafter referred to as “second n-type epitaxial layer”) 56 is formed. At this time, the thickness dimension of the second n− type epitaxial layer 56 formed on the bottom surface of the inner wall surface of the trench 55 is about one tenth of the thickness dimension of the second n− type epitaxial layer 56 formed on the side surface. It becomes.

  Next, thermal oxidation is performed by an anisotropic thermal oxidation method, and a gate insulating film 57 is formed on the surface of the second n− type epitaxial layer 56. At this time, the second n− type epitaxial layer 56 formed on the bottom surface of the trench 55 is entirely oxidized to be changed into an oxide film, and becomes a gate insulating film 57. The surface of the second n− type epitaxial layer 56 formed on the side surface of the trench 55 is oxidized to form the gate insulating film 57. Next, the trench 55 is filled with a polysilicon layer as the gate electrode film 58. Thereafter, an interlayer insulating film 59, a source electrode film 60, and a drain electrode film 61 are formed, and a trench gate type MOSFET 50 is manufactured.

  In the first prerequisite technology, by adopting such a structure, the impurity concentration of the second n− type epitaxial layer 56 forming the channel is changed to the n− type epitaxial layer 52 and the p type epitaxial layer 53 in which the trench 55 is formed. It is possible to design them separately from each other, reducing the resistance of the channel portion and lowering the threshold voltage.

  FIG. 13 is a cross-sectional view showing a configuration of a trench gate type MOSFET 50A which is a semiconductor device of the second prerequisite technology. 14 is a cross-sectional view showing a configuration in the middle of the manufacturing process of trench gate type MOSFET 50A shown in FIG. Since the MOSFET 50A of the second base technology is similar in configuration to the MOSFET 50 of the first base technology shown in FIG. 12, the MOSFET 50A of the second base technology is the same as the MOSFET 50 of the first base technology. About the structure, the same referential mark is attached | subjected and common description is abbreviate | omitted.

  Similarly to the MOSFET 50 of the first base technology, the MOSFET 50A of the second base technology includes a silicon carbide semiconductor substrate 51 using a (0001-) carbon surface as an upper surface, an n − type epitaxial layer 52, and a p type epitaxial layer 53. And an n + type source region 54. Hereinafter, silicon carbide semiconductor substrate 51, n − type epitaxial layer 52, p type epitaxial layer 53, and n + type source region 54 may be collectively referred to as “substrate”.

  In the MOSFET 50A of the second premise technology, as shown in FIG. 14, the sidewall of the trench 55A is formed to have a tapered shape by adjusting the etching gas conditions, and then thermally oxidized to perform thermal oxidation. 62 is formed. At this time, by using the (0001−) carbon surface, the thickness of the thermal oxide film 62 formed on the bottom surface of the trench 55A and the surfaces of the n + -type source region 54 and the p-type epitaxial layer 53 as the substrate surface. The dimension is about five times larger than the thickness dimension of the thermal oxide film 62 formed on the side surface of the trench 55A.

  Thereafter, using the thermal oxide film 62 as a mask, n-type impurities are implanted from the normal direction of the substrate, that is, upward from the paper surface in FIG. As a result, n-type impurities are implanted through the thermal oxide film 62 in the side surface portion of the trench 55A where the thermal oxide film 62 is thin, and the thin film semiconductor layer 63 is formed in the channel portion. At this time, the bottom surface of the trench 55A is protected from the n-type impurity implantation by the oxide film 62 formed on the bottom surface. That is, the n-type impurity is not implanted into the bottom portion of the trench 55A, and the thin film semiconductor layer 63 is not formed. Thereafter, the oxide film 62 is removed, and a trench gate type MOSFET 50A is manufactured through a process similar to that of the MOSFET 50 of the first prerequisite technology.

  In the second premise technology, such a configuration makes it possible to form the thin film semiconductor layer 63 in the channel portion corresponding to the second n− type epitaxial layer 56 in the MOSFET 50 of the first premise technology without using epitaxial growth. Thus, the resistance of the channel portion is reduced and the threshold voltage is lowered.

  In the first prerequisite technique shown in FIG. 12, it is necessary to form the second n− type epitaxial layer 56 constituting the channel portion of the trench gate type MOSFET 50 by an epitaxial growth process. In addition, in order to form the second n− type epitaxial layer 56 only on the side surface of the trench 55, it is necessary to perform advanced control such as adjusting the epitaxial growth rate, that is, the growth rate, on the side surface and the bottom surface of the trench 55. It is. Therefore, there is a problem that the trench gate type MOSFET 50 of the first prerequisite technology cannot be easily manufactured.

  In the second prerequisite technique shown in FIGS. 13 and 14, the thin film semiconductor layer 63 can be formed in the channel portion without going through an epitaxial growth step. The thickness dimension of the thin film semiconductor layer 63 is the same as that of the trench 55A. Depends on taper angle. The channel mobility of the trench gate type MOSFET is determined when the channel is formed parallel to the crystal plane as described in, for example, “Materials science forum 2007, vol. 556-57, p. 807-p. 810”. It is known that the characteristics are the best.

  In the trench gate type MOSFET 50A of the second prerequisite technology, when the thickness dimension of the thin film semiconductor layer 63 to be formed is determined, the taper angle of the trench 55A necessary for realizing the thin film semiconductor layer 63 having the thickness dimension is determined. There is a problem that the taper angle that can be designed is limited.

  For example, in the case of a vertical trench whose side surface is parallel to the thickness direction of the substrate, even if impurities are implanted from the normal direction of the substrate as shown in FIG. 14, the thin film semiconductor layer 63 is formed on the side surface of the trench. Can not. In order to form the thin film semiconductor layer 63 on the side surface of the trench, it is necessary to inject impurities several times from an oblique direction, so that it cannot be easily manufactured. Therefore, in the second prerequisite technique, it is difficult to form a channel parallel to the crystal plane as described above, and it is difficult to realize the above-described good channel mobility.

  Further, the second premise technique has a problem that usable substrates are limited, for example, it is necessary to use a (0001-) carbon surface in order to form the thin film semiconductor layer 63.

  As described above, the first and second base technologies have various problems. Therefore, the semiconductor device of the present invention employs the configurations of the following embodiments. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type.

<First Embodiment>
FIG. 1 is a cross-sectional view showing a configuration of a trench gate type MOSFET 1 which is a semiconductor device according to a first embodiment of the present invention. A trench gate type MOSFET (hereinafter sometimes simply referred to as “MOSFET”) 1 of the present embodiment is a silicon carbide semiconductor device using silicon carbide.

  MOSFET 1 includes a silicon carbide semiconductor substrate (hereinafter also referred to as a “silicon carbide substrate”) 11, an n-type silicon carbide drift layer 12, a p-type base region 13, an n-type source region 14, and a channel layer. 16, a gate insulating film 17, a gate electrode 18, an interlayer insulating film 19, a source electrode 20 and a drain electrode 21.

  Silicon carbide substrate 11 is an n-type low-resistance silicon carbide substrate, and is realized, for example, as a silicon carbide substrate having a 4H polytype. Silicon carbide drift layer 12 is formed by being laminated on the surface portion on one side in the thickness direction of silicon carbide substrate 11. Base region 13 is formed on the surface portion on one side in the thickness direction of silicon carbide drift layer 12. Base region 13 contains a p-type impurity which is a second conductivity type impurity, for example, aluminum (Al). The source region 14 is formed shallower than the base region 13 in a part of the surface portion on one side in the thickness direction of the base region 13. Source region 14 contains an n-type impurity, for example, nitrogen (N), which is an impurity of the first conductivity type.

  A trench 15 is formed in the base region 13 and the source region 14 so as to penetrate the base region 13 and the source region 14 in the thickness direction. In the present embodiment, trench 15 is formed so as to penetrate through source region 14 and base region 13 and reach the inside of silicon carbide drift layer 12.

  The gate insulating film 17 is formed along the inner wall including the side surface and the bottom surface of the trench 15. In the present embodiment, gate insulating film 17 is made of silicon oxide.

  The gate electrode 18 is formed so as to fill the inside of the trench 15 including the gate insulating film 17. In other words, the gate electrode 18 is provided in contact with the gate insulating film 17 on the radially inner side of the trench 15.

  The interlayer insulating film 19 is formed so as to cover the gate electrode 18. More specifically, the interlayer insulating film 19 is provided so as to cover the gate electrode 18 and the portion of the source region 14 near the gate electrode 18. The interlayer insulating film 19 is opened so as to expose the source region 14 and the portion of the base region 13 near the source region 14, that is, the remaining portion excluding the portion near the gate electrode 18. The interlayer insulating film 19 is not formed.

  The source electrode 20 is formed on the surface portion on one side in the thickness direction of the source region 14 and the base region 13 where the interlayer insulating film 9 is not formed. The source electrode 20 electrically connects the source region 14 exposed through the opening of the interlayer insulating film 19 and the base region 13. Drain electrode 21 is formed on the surface portion on the opposite side to the surface portion on one side in the thickness direction of silicon carbide substrate 11, that is, on the surface portion on the other side in the thickness direction of silicon carbide substrate 11.

  In the MOSFET 1, a region of the base region 13 that forms the side surface of the trench 15 that faces the gate electrode 18 through the gate insulating film 17 and in which an inversion layer is formed during the ON operation is referred to as a channel portion. Of the portion sandwiched between silicon carbide drift layer 12 and source region 14 in base region 13, the distance between silicon carbide drift layer 12 and source region 14 in the portion including the channel portion is referred to as the channel length.

  In the present embodiment, a channel layer 16 is formed in the channel portion. More specifically, channel layer 16 is formed across the channel portion of base region 13 and the portion connected to the channel portion of the surface portion on one side in the thickness direction of silicon carbide drift layer 12. The channel layer 16 is formed so as to spread outward in the radial direction of the trench 15 from the opening on one side in the thickness direction of the trench 15 toward the bottom surface. The channel layer 16 has a second conductivity type impurity concentration, that is, a p-type impurity concentration lower than that of the base region 13. The channel layer 16 is formed by ion-implanting an n-type impurity such as nitrogen (N) into the p-type base region 13.

  Next, the operation of the trench gate type MOSFET 1 of the present embodiment will be briefly described. When a positive voltage equal to or higher than the threshold voltage is applied to gate electrode 18 of trench gate type MOSFET 1, an inverted channel is formed in the channel portion, and n-type source region 14 and n-type silicon carbide drift layer 12 are In the meantime, a path through which electrons as carriers flow is formed. Electrons flowing from source region 14 into silicon carbide drift layer 12 reach drain electrode 21 via silicon carbide drift layer 12 and silicon carbide substrate 11 in accordance with an electric field formed by a positive voltage applied to drain electrode 21. . Therefore, a current flows from the drain electrode 21 to the source electrode 20 by applying a positive voltage to the gate electrode 18. This state is called an on state.

  The on-resistance of the trench gate type MOSFET 1 can be reduced by reducing the resistance of the channel portion in the on state, but the resistance of the channel portion can be lowered as the channel length is shorter and the electron mobility in the channel portion is higher. Here, if the effective acceptor concentration in the channel portion is low, the influence of impurity scattering is reduced. Therefore, the mobility of electrons in the channel portion can be increased as the effective acceptor concentration in the channel portion is decreased. it can. The threshold voltage also decreases as the effective acceptor concentration in the channel portion decreases.

  Unlike the ON state, when a voltage lower than the threshold voltage is applied to the gate electrode 18, no inversion channel is formed in the channel portion, so that no current flows from the drain electrode 21 to the source electrode 20. This state is called an off state.

  In the off state, a depletion layer extends from the pn junction between silicon carbide drift layer 12 and base region 13 due to the positive voltage applied to drain electrode 21. When the depletion layer extending from the pn junction toward the base region 13 reaches the source region 14, punch-through breakdown occurs.

In this embodiment, the lower limit of the p-type impurity concentration in the base region 13 (hereinafter sometimes simply referred to as “impurity concentration”) is set to 1 × 10 ¹⁷ cm ⁻³ or more so that punch-through breakdown does not occur. ing. The upper limit of the impurity concentration of the base region 13 can reduce the effective acceptor concentration of the channel portion of the base region 13 by performing ion implantation of an n-type impurity such as nitrogen (N), whereby the channel layer 16 can be formed. Thus, it is 5 × 10 ¹⁷ cm ⁻³ or less. That is, in this embodiment, the impurity concentration of the base region 13 is set to 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less.

  Subsequently, a method for manufacturing the trench gate type MOSFET 1 which is the semiconductor device of the present embodiment will be described in order with reference to FIGS. 2-7 is sectional drawing which shows the structure in each manufacturing process of trench gate type | mold MOSFET1.

FIG. 2 is a cross-sectional view showing the configuration at the stage where the formation of the source region 14 is completed. First, as shown in FIG. 2, an n-type silicon carbide drift layer 12 is epitaxially grown on the surface portion on one side in the thickness direction of the silicon carbide substrate 11 by a chemical vapor deposition (abbreviation: CVD) method. . As silicon carbide substrate 11, an n-type low-resistance silicon carbide substrate having a 4H polytype is used. The concentration of n-type impurities in silicon carbide drift layer 12 (hereinafter sometimes referred to as “n-type impurity concentration”) is selected in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The thickness dimension of silicon carbide drift layer 12 is selected in the range of 5 μm to 50 μm.

Next, a p-type base region 13 is formed by ion-implanting a p-type impurity, for example, Al, into the surface portion on one side in the thickness direction of silicon carbide drift layer 12. At this time, the depth of the ion implantation of the p-type impurity is set to a depth not exceeding the thickness dimension of the silicon carbide drift layer 12, specifically, about 0.5 μm to 3 μm. Further, the concentration of ion-implanted p-type impurities (hereinafter sometimes referred to as “p-type impurity concentration”), that is, the p-type impurity concentration of the base region 13 is 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁷ cm ^{−. In} the range of ³ , the n-type impurity concentration of the silicon carbide drift layer 12 is higher. Of the silicon carbide drift layer 12, the region that becomes p-type in the region where the p-type impurity is ion-implanted becomes the base region 13. The base region 13 may be formed by epitaxial growth. Also in this case, the p-type impurity concentration and the thickness dimension of the base region 13 are the same as those formed by ion implantation.

Next, an n-type impurity, for example, N is ion-implanted into a surface portion on one side in the thickness direction of silicon carbide drift layer 12 through an implantation mask (not shown) to form n-type source region 14. Specifically, n-type impurities are ion-implanted into a portion of silicon carbide drift layer 12 that becomes base region 13, that is, a portion of the surface portion on one side in the thickness direction of base region 13, thereby producing an n-type source. Region 14 is formed. The n-type impurity ion implantation depth is shallower than the thickness dimension of the base region 13. Further, the concentration of the ion-implanted n-type impurity, that is, the n-type impurity concentration of the source region 14 is in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the p-type impurity concentration of the base region 13 is set. Exceed. Of the regions into which the n-type impurity is implanted in the base region 13 of the silicon carbide drift layer 12, the region showing the n-type becomes the source region 14.

  FIG. 3 is a cross-sectional view showing the configuration at the stage where the formation of the etching mask 26 is completed. Next, as shown in FIG. 3, a silicon oxide layer 25 is deposited on the surface portion on one side in the thickness direction of silicon carbide drift layer 12 by about 1 μm to 2 μm. Specifically, the silicon oxide layer 25 is formed on the surface portion on one side in the thickness direction of the base region 13 where the source region 14 is not formed and on the surface portion on one side in the thickness direction of the source region 14. . Thereafter, the silicon oxide layer 25 is laminated on the surface portion on one side in the thickness direction to form an etching mask 26 made of a resist material, and an opening is formed at a portion where the trench 15 is formed.

  FIG. 4 is a cross-sectional view showing the configuration at the stage where the etching of the silicon oxide layer 25 has been completed. After forming the etching mask 26 as described above, as shown in FIG. 4, the silicon oxide layer 25 having the etching mask 26 formed on the surface portion is subjected to reactive ion etching (abbreviation: RIE) treatment. The silicon oxide layer 25 is opened by etching. As a result, the silicon oxide layer 25 is opened so that a predetermined portion for forming the trench 15 of the source region 14 is exposed. The silicon oxide layer 25 etched here serves as an implantation mask and an etching mask used in a process described later.

  FIG. 5 is a cross-sectional view showing the configuration at the stage where the formation of the channel layer 16 is completed. Next, as shown in FIG. 5, an n-type impurity, for example, N is ion-implanted using the etching mask 26 and the remaining silicon oxide layer 25 as an implantation mask to form a channel layer 16. Specifically, an n-type impurity is ion-implanted into the base region 13 through the etching mask 26 and the source region 14 exposed through the opening of the silicon oxide layer 25 to form the channel layer 16. In the present embodiment, not only base region 13 but also a portion of silicon carbide drift layer 12 is implanted with n-type impurities to form channel layer 16.

The depth of ion implantation of n-type impurities for forming the channel layer 16 is deeper than the thickness dimension of the base region 13. Further, the concentration of the ion-implanted n-type impurity, that is, the n-type impurity concentration of the channel layer 16 is set to the same level as the p-type impurity concentration of the base region 13, specifically, 1 × 10 ¹⁷ cm ^{−3 to} 6 × 10. ^{It is} about ¹⁷ cm ⁻³ . When performing the ion implantation, it is known that there is injected spreads in the lateral direction, the channel layer 16 extends about 0.1μm~0.3μm to by apertures Rimo径outward implantation mask is formed Is done. The implantation spread becomes larger as the impurity concentration is larger and the implantation energy is larger.

  FIG. 6 is a cross-sectional view showing the configuration at the stage where the formation of the trench 15 is completed. Subsequently, silicon carbide is etched by RIE as shown in FIG. 6 using silicon oxide layer 25 which is the same mask used for ion implantation of n-type impurities for forming channel layer 16. A trench 15 penetrating the source region 14 and the base region 13 is formed. The depth of the trench 15 is about 0.5 μm to 3 μm so as to be equal to or greater than the depth of the base region 13. In the present embodiment, trench 15 penetrates source region 14 and base region 13 to reach the inside of silicon carbide drift layer 12. More specifically, trench 15 penetrates channel layer 16 and drifts silicon carbide. It is formed so as to reach the inside of the layer 12.

  Next, after removing the silicon oxide layer 25 used as a mask, annealing is performed at 1300 ° C. to 1900 ° C. for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas by a heat treatment apparatus. By this annealing, ion-implanted n-type impurities and p-type impurities such as N and Al are activated.

  FIG. 7 is a cross-sectional view showing a configuration at a stage where the formation of the interlayer insulating film 19 is completed. Subsequently, as shown in FIG. 7, the surface portion of the silicon carbide drift layer 12 including the source region 14 and the base region 13 is thermally oxidized, so that the gate insulating film 17 having a desired thickness is formed inside the trench 15, specifically It is formed on the inner wall. The gate insulating film 17 is not limited to thermal oxidation, and may be formed, for example, by depositing a silicon oxide layer.

  Next, a gate electrode film, for example, a polycrystalline silicon film having conductivity, is formed by a low pressure CVD method so as to be in contact with the gate insulating film 17 inside the trench 15. The gate electrode 18 is formed by patterning the formed gate electrode film. Next, an interlayer insulating film 19 is formed so as to cover the surface portions on one side in the thickness direction of the gate electrode 18, the gate insulating film 17, the source region 14, and the base region 13. After that, as shown in FIG. 7, the interlayer insulating film 19 is opened so that the base region 13 and the portion of the source region 14 near the base region 13 are exposed.

  Finally, source electrode 10 electrically connected to exposed portions of source region 14 and base region 13 is formed, and drain electrode 11 is laminated on the surface portion on the other side in the thickness direction of silicon carbide substrate 11. Form. Thereby, the vertical MOSFET 1 shown in FIG. 1 is completed. Here, examples of the material to be the source electrode 10 and the drain electrode 11 include an Al alloy.

  As described above, according to the present embodiment, as shown in FIG. 5, n-type impurities are ionized in base region 13 through source region 14 exposed through the opening of silicon oxide layer 25 used as an implantation mask. The channel layer 16 is formed by implantation. When an impurity is ion-implanted through the implantation mask, the impurity is implanted by spreading outward in the radial direction of the opening of the implantation mask. This phenomenon is called “infusion spreading”. In the base region 13, an impurity implantation layer is formed so as to extend over a wider range than the opening of the silicon oxide layer 25, which is an implantation mask, due to the implantation spread when the n-type impurity is ion-implanted. This impurity implantation layer becomes the channel layer 14. Since the silicon oxide layer 25 is also used as an etching mask for forming the trench 15, the channel layer 16 is formed to extend over a wider range than the opening of the etching mask.

  Next, using the same mask as that used for ion implantation, that is, the silicon oxide layer 25, the source region 14 and the base region 13 are etched to form the trench 15, so that the channel on the side surface of the trench 15 is formed. An n-type impurity implantation layer remains as the channel layer 16 in the channel portion which is a portion.

  Since the channel layer 16 is formed by ion-implanting n-type impurities into the p-type base region 13, the effective p-type impurity concentration, that is, the effective acceptor concentration is lower than that of the base region 13. Since such a channel layer 16 is formed, the resistance of the channel portion can be reduced and the threshold voltage can be lowered.

  In the present embodiment, since the channel layer 16 having a low acceptor concentration is effectively formed by utilizing the implantation spread, which is the spread of impurities during ion implantation, an epitaxial growth process is performed to form the channel layer 16. unnecessary. Further, the taper angle of the trench and the semiconductor substrate to be used are not limited. In addition, since the n-type impurity is implanted before the trench 15 is formed, unlike the case where the n-type impurity is implanted after the trench is formed, the trench 15 is implanted so that the n-type impurity is implanted only into the side surface of the trench. It is not necessary to form a protective layer against the implantation of n-type impurities, that is, a protective layer for protecting the n-type impurities from being implanted into the bottom surface. Therefore, in order to function as a protective layer, a treatment such as increasing the thickness of the oxide film that is the gate insulating film on the bottom surface of the trench 15 is not necessary.

  In the present embodiment, the n-type impurity is implanted using the silicon oxide layer 25 which is an etching mask for forming the trench 15. The n-type impurity is implanted to form the channel layer 16 and the trench. Etching to form 15 is realized with one mask. As described above, since the implantation of impurity ions for forming the channel layer 16 and the etching for forming the trench 15 are performed with one mask, mask alignment is not necessary, and the number of processes can be reduced. From the above, in the present embodiment, the excellent MOSFET 1 can be easily manufactured as described above.

<Second Embodiment>
FIG. 8 is a cross-sectional view showing a configuration of a trench gate type MOSFET 2 which is a semiconductor device according to the second embodiment of the present invention. MOSFET 2 of the present embodiment is a silicon carbide semiconductor device, similarly to MOSFET 1 of the first embodiment. The MOSFET 2 of the present embodiment is similar in configuration to the MOSFET 1 of the first embodiment. Therefore, in the MOSFET 2 of the present embodiment, the same configuration as the MOSFET 1 of the first embodiment is the same. A common description is omitted with reference numerals.

  The MOSFET 2 of the present embodiment has a p-type impurity concentration higher than that of the base region 13 in a part of the p-type base region 13, specifically, in a portion other than the portion where the n-type source region 14 is formed. Two base regions 30 are provided.

  Next, a method for manufacturing MOSFET 2 of the present embodiment will be described with reference to FIG. FIG. 9 is a cross-sectional view showing a configuration at a stage where the formation of the second base region 30 is completed. Since the manufacturing method of MOSFET 2 of the present embodiment is similar to the manufacturing method of MOSFET 1 of the first embodiment, description of the same steps will be omitted, and different steps will be described.

  In the present embodiment, after the step of forming source region 14 shown in FIG. 2 described above in the first embodiment, as shown in FIG. 9, on the surface portion on one side in the thickness direction of silicon carbide drift layer 12. The implantation mask 31 is formed by laminating. The implantation mask 31 is formed so as to be opened so that a predetermined portion of the base region 13 is exposed to form the second base region 30. In the present embodiment, implantation mask 31 is laminated on the surface portion on one side in the thickness direction of source region 14 in silicon carbide drift layer 12 to form the surface portion on the one side in the thickness direction of silicon carbide drift layer 12. An opening is formed so that the base region 13 to be exposed is exposed.

Next, a p-type impurity such as Al is ion-implanted into the silicon carbide drift layer 12 having the implantation mask 31 formed on the surface portion. At this time, the ion implantation depth of the p-type impurity is about the same as that of the base region 13, specifically about 0.5 μm to 3 μm. Further, the concentration of the ion-implanted p-type impurity, that is, the p-type impurity concentration of the second base region 30 is higher than that of the base region 13, specifically, 5 × 10 ¹⁷ cm ⁻³ to 1 × 10 ^19. It is assumed that it is in the range of cm ⁻³ and is higher than the n-type impurity concentration of silicon carbide drift layer 12. Here, the region that becomes p-type in the region where the p-type impurity is ion-implanted in the silicon carbide drift layer 12 becomes the second base region 30.

  As described above, according to the present embodiment, the second base region 30 having a higher p-type impurity concentration than the base region 13 is formed in the base region 13 other than the portion where the source region 14 is formed. It is formed. As a result, even when the p-type impurity concentration of the base region 13 is lowered, the depletion layer extending from the p-type base region 13 toward the n-type source region 14 by the depletion layer extending from the second base region 39. The layer can be suppressed. Accordingly, since punch-through is less likely to occur, the p-type impurity concentration in the base region 13 can be further reduced, and the depth of the base region 13 can be reduced.

<Third Embodiment>
FIG. 10 is a sectional view showing a configuration of a trench gate type MOSFET 3 which is a semiconductor device according to the third embodiment of the present invention. MOSFET 3 of the present embodiment is a silicon carbide semiconductor device, similarly to MOSFET 1 of the first embodiment. Since the MOSFET 3 of the present embodiment is similar in configuration to the MOSFET 1 of the first embodiment, the same configuration as the MOSFET 1 of the first embodiment is the same in the MOSFET 3 of the present embodiment. A common description is omitted with reference numerals.

  The MOSFET 3 according to the present embodiment includes a bottom protective layer 35 formed of a p-type semiconductor layer on the bottom of the trench 15. The bottom protective layer 35 protects the gate insulating film 17.

  Next, a method for manufacturing MOSFET 3 of the present embodiment will be described with reference to FIG. FIG. 11 is a cross-sectional view showing the configuration at the stage where the formation of the bottom protective layer 35 is completed. Since the manufacturing method of MOSFET 3 of the present embodiment is similar to the manufacturing method of MOSFET 1 of the first embodiment, description of the same steps will be omitted, and different steps will be described.

In this embodiment, after the step of forming the trench 15 shown in FIG. 6 in the first embodiment, an etching mask made of the silicon oxide layer 25 used when forming the trench 15 is left. Then, using this silicon oxide layer 25 as an etching mask, as shown in FIG. 11, p-type impurities such as Al are ion-implanted into the bottom surface of the trench 15 to form the bottom surface protective layer 35. At this time, the concentration of the ion-implanted p-type impurity, that is, the p-type impurity concentration of the bottom surface protective layer 35 is about the same as that of the p-type base region 13, specifically, 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10. ^It is assumed that it is higher than the n-type impurity concentration of silicon carbide drift layer 12 in the range of ¹⁷ cm ⁻³ . Here, the region that becomes p-type in the region where the p-type impurity is ion-implanted in the silicon carbide drift layer 12 becomes the bottom surface protective layer 35.

  As described above, according to the present embodiment, the bottom surface protective layer 35 composed of the p-type semiconductor layer is formed on the bottom surface of the trench 15. As a result, the electric field strength of the portion of gate insulating film 17 formed on the bottom surface of trench 15 is relaxed by the depletion layer extending from p-type bottom surface protective layer 35 toward silicon carbide drift layer 12. Concentration can be prevented. Therefore, the reliability of the gate insulating film 17 can be improved.

  In the present embodiment, since the bottom protective layer 35 is formed using the mask used when forming the trench 15, mask alignment is not necessary, and the number of processes can be reduced.

  The configuration other than the bottom surface protection layer 35 of the MOSFET 3 of the present embodiment is configured similarly to the MOSFET 1 of the first embodiment, but may be configured similarly to the MOSFET 2 of the second embodiment.

  In each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, in other embodiments of the present invention, the first conductivity type is p-type and the second conductivity type is the second conductivity type. The type may be n-type.

  1, 2, 3, 50, 50A trench gate type MOSFET, 11, 51 silicon carbide semiconductor substrate, 12 silicon carbide drift layer, 13 base region, 14 source region, 15, 55, 55A trench, 16 channel layer, 17, 57 , 57A gate insulating film, 18 gate electrode, 19, 59, 59A interlayer insulating film, 20 source electrode, 21 drain electrode, 25 silicon oxide layer, 26 etching mask, 30 second base region, 31 implantation mask, 35 bottom surface protection Layer, 52 n− type epitaxial layer, 53 p type epitaxial layer, 54 n + type source region, 56 second n− type epitaxial layer, 58, 58A gate electrode film (polysilicon layer), 60 source electrode film, 61 drain electrode film 62 Thermal oxide film, 63 Thin film semiconductor layer.

Claims (8)

Laminating on a surface portion on one side in the thickness direction of the first conductivity type semiconductor substrate to form a drift layer of the first conductivity type;
Forming a second conductivity type base region on a surface portion on one side in the thickness direction of the drift layer;
Forming a first conductivity type source region on a portion of the surface portion on one side in the thickness direction of the base region;
Forming a mask that is laminated on a surface portion on one side in the thickness direction of the base region and the source region, so that a predetermined portion is exposed to form a trench of the source region; and
By implanting ions of the first conductivity type into the base region through the source region exposed through the opening of the mask, the base region is spread radially outward from the opening of the mask and is more effective than the base region. Forming a channel layer having a low concentration of typical second conductivity type impurities ;
After forming the channel layer by reactive ion etching said source region and said base region using said mask, a trench penetrating the channel layer formed on the source region, and said base region And a step of forming the semiconductor device. In the step of forming the channel layer, the semiconductor device according to claim 1, characterized that you form the channel layer spread 0.1μm~0.3μm radially outward from the opening of the mask Production method. In the step of forming the channel layer, the claims the concentration of impurities of the first conductivity type, characterized that you form the channel layer is ^{1 × 10 17 cm -3 ~6 ×} 10 17 cm -3 A method for manufacturing a semiconductor device according to 1 or 2. After the step of forming the source region and before the step of forming the mask,
The method further comprises forming a second base region having a second conductivity type impurity concentration higher than that of the base region in a portion of the base region other than the portion where the source region is formed. the method of manufacturing a semiconductor device according to any one of claims 1 to 3. After the step of forming the trench,
A bottom protective layer that protects the gate insulating film formed on the inner wall of the trench by ion-implanting a second conductivity type impurity into the bottom of the trench using the mask used when forming the trench. the method of manufacturing a semiconductor device according to any one of claims 1-4, characterized by further comprising the step of forming. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1,
A first conductivity type semiconductor substrate;
A drift layer of a first conductivity type provided by being laminated on a surface portion on one side in the thickness direction of the semiconductor substrate;
A base region of a second conductivity type formed on a surface portion on one side in the thickness direction of the drift layer;
A source region of a first conductivity type formed on a portion of the surface portion on one side in the thickness direction of the base region;
The side surface of the trench that penetrates the base region and the source region in the thickness direction is configured, and spreads outward in the radial direction of the trench from the opening on one side in the thickness direction of the trench toward the bottom surface. A channel layer having a low concentration of effective second conductivity type impurities,
A gate insulating film provided along an inner wall including a side surface and a bottom surface of the trench;
A gate electrode provided in contact with the gate insulating film on the radially inner side of the trench;
An interlayer insulating film provided so as to cover the gate electrode and opened so as to expose part of the surface portion on one side in the thickness direction of the source region and the base region;
A source electrode that electrically connects the source region exposed through the opening of the interlayer insulating film and the base region;
Semi conductor arrangement characterized by obtaining Bei and drain electrodes provided on a surface portion of the thickness direction other side of the semiconductor substrate. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 4,
A first conductivity type semiconductor substrate;
A drift layer of a first conductivity type provided by being laminated on a surface portion on one side in the thickness direction of the semiconductor substrate;
A base region of a second conductivity type formed on a surface portion on one side in the thickness direction of the drift layer;
A source region of a first conductivity type formed on a portion of the surface portion on one side in the thickness direction of the base region;
The side surface of the trench that penetrates the base region and the source region in the thickness direction is configured, and spreads outward in the radial direction of the trench from the opening on one side in the thickness direction of the trench toward the bottom surface. A channel layer having a low concentration of effective second conductivity type impurities,
A gate insulating film provided along an inner wall including a side surface and a bottom surface of the trench;
A gate electrode provided in contact with the gate insulating film on the radially inner side of the trench;
An interlayer insulating film provided so as to cover the gate electrode and opened so as to expose part of the surface portion on one side in the thickness direction of the source region and the base region;
A source electrode that electrically connects the source region exposed through the opening of the interlayer insulating film and the base region;
A drain electrode provided on the surface portion on the other side in the thickness direction of the semiconductor substrate,
A semiconductor device, further comprising a second base region having a concentration of a second conductivity type impurity higher than that of the base region in a portion of the base region other than the portion where the source region is formed. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 5,
A first conductivity type semiconductor substrate;
A drift layer of a first conductivity type provided by being laminated on a surface portion on one side in the thickness direction of the semiconductor substrate;
A base region of a second conductivity type formed on a surface portion on one side in the thickness direction of the drift layer;
A source region of a first conductivity type formed on a portion of the surface portion on one side in the thickness direction of the base region;
A side surface of the trench that penetrates the base region and the source region in the thickness direction is configured, and spreads outward in the radial direction of the trench from the opening on one side in the thickness direction of the trench toward the bottom surface. A channel layer having a low concentration of effective second conductivity type impurities,
A gate insulating film provided along an inner wall including a side surface and a bottom surface of the trench;
A gate electrode provided in contact with the gate insulating film on the radially inner side of the trench;
An interlayer insulating film provided so as to cover the gate electrode and opened so as to expose part of the surface portion on one side in the thickness direction of the source region and the base region;
A source electrode that electrically connects the source region exposed through the opening of the interlayer insulating film and the base region;
A drain electrode provided on the surface portion on the other side in the thickness direction of the semiconductor substrate,
A semiconductor device, further comprising a bottom surface protection layer that is formed of a second conductivity type semiconductor layer on the bottom surface of the trench and protects the gate insulating film.

Images