JP3170966B2 - Insulated gate control semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate control semiconductor device such as a field effect transistor or an insulated gate bipolar transistor having a buried gate structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art The above-described insulated gate control semiconductor device has an advantage that its on / off can be controlled by an insulated gate having a high input impedance, and that a field effect transistor is particularly suitable for a high frequency and an insulated gate bipolar transistor is particularly suitable for a large current. In addition to being widely used as individual semiconductor elements, recently, the number of cases in which the semiconductor device is used together with related circuits in a form of integrated circuit device chip has been increasing.

In this insulated gate control semiconductor device, in order to improve the high frequency characteristics and increase the current capacity not only in the case of being incorporated in an integrated circuit device but also in the case of an individual element, a fine unit cell pattern is planarized by utilizing semiconductor integrated circuit technology. However, recently the performance improvement due to such fine patterning is approaching its limit, so the gate is housed in a trench dug in a semiconductor and the miniaturization is performed. A buried insulated gate structure has been adopted. Hereinafter, the structure of the conventional insulated gate control semiconductor device having the buried gate structure will be described with reference to FIG.

[0006] The insulated gate control semiconductor device shown in FIG. 6 is a vertical field effect transistor, and FIG. 6 shows an enlarged cross section of an end portion including two buried insulated gates. A semiconductor substrate 10, which is a wafer or chip for a semiconductor device, has an n-type epitaxial layer having a relatively high resistivity of several tens μm as a semiconductor region 12 on which a fine structure is to be formed on an n-type semiconductor substrate 11. That has grown,
The p-type well 20 extends from the surface of the semiconductor region 12 within a range surrounded by the field oxide film 13 covering the surface on the right side of the figure.
First, a trench 30 is dug into a lower semiconductor region 12 as shown in the figure from a point on the surface of the well 20, and a gate oxide film 41 and a gate 42 of polycrystalline silicon are formed therein. , The p-type contact layer 23 for the well 20 is diffused between the trenches 30 with a high impurity concentration, and the n-type source layer 50 partially overlaps the contact layer 23. At the same time, it diffuses very shallowly with a high impurity concentration so as to be in contact with the groove 30.

Further, a metal electrode film 61 is provided on the surface side of the semiconductor substrate 10 so that the contact layer 23 of the p-type well 20 and n
The source layer 50 is formed as a source terminal S for short-circuiting on the front surface, an electrode film 62 is provided on the back surface in contact with the n-type semiconductor substrate 11 to form a drain terminal D, and the insulating gate 40 has a section other than the illustrated cross section. The control terminal G is derived from the location. In the field effect transistor having such a structure, when the control terminal G receives a positive control voltage from the source terminal S, the n-type source layers 50 and n of the p-type well 20 contacting the gate oxide film 41 on the side surface of the groove 30
An n-type channel is formed in a portion sandwiched between the semiconductor regions 12 and the source terminal S and the drain terminal D are turned on. As described above, by embedding the insulating gate 40 in the groove 30 and forming the channel in the vertical direction, the interval between the insulating gates 40 can be shortened, and the structure can be miniaturized. , The current capacity can be increased.

Since the depletion layer mainly spreads in the semiconductor region 12 below the trench 30 when the device is off, the breakdown voltage of this field effect transistor is set by the thickness of the semiconductor region 12. Since dielectric breakdown easily occurs along the lower surface of the field oxide film 13 in the semiconductor region 12, a metal so-called field plate 63 is placed on the field oxide film 13 and near the periphery of the well 20 at the same time that the electrode film 61 is provided. And the same potential as that of the well 20 is applied thereto to prevent dielectric breakdown. FIG. 6 shows the structure of the field-effect transistor.
By inserting a buffer layer of the shape between the semiconductor region 12 and the semiconductor region 12, an insulated gate bipolar transistor can be obtained with the upper part of the semiconductor region 12 having the same structure as that shown in the figure.

[0007]

By embedding the insulated gate as described above, the structure of the insulated gate control semiconductor device can be finely patterned to enhance its high-frequency characteristics or increase its current capacity. In the off state, the avalanche breakdown is likely to occur in the semiconductor region below the insulated gate groove, which has the adverse effect of being rather disadvantageous in terms of withstand voltage. There is a problem that the forward voltage or the on-voltage tends to increase because the flow path of the current flowing into the region is not so good. Hereinafter, the causes of these problems will be described with reference to FIGS. 7A and 7B, respectively.

FIG. 7A is an enlarged sectional view of a main part of an insulated gate control semiconductor device in an off state.
The manner in which the depletion layer extends from the pn junction between the semiconductor region 20 and the n-type semiconductor region 12 into the latter is shown by the equipotential surface EP. When the interval between the equipotential surfaces EP is compared with the line just below the groove 30, the line b in the bulge, the line c along the Si surface, and the line d near the curvature of the junction, as can be seen from the figure, the insulating gate 40 Embedded groove 30
In the direction of the lower vertical line a, the interval between the equipotential surfaces EP is the narrowest, and the electric field intensity is very strong at a portion immediately below the groove 30 in the semiconductor region 12, and avalanche breakdown is likely to occur. The distance between the equipotential surfaces EP in the direction of the line c beside the surface of the semiconductor region 12 in contact with the field oxide film 13 is widened by the above-mentioned field plate 63, and the electric field intensity is reduced. As described above, the weak point where avalanche breakdown is most likely to occur is directly below the groove 30 in the semiconductor region 12, and the reduction in breakdown voltage due to this weak point is slightly alleviated by reducing the depth of the groove 30 projecting from the bottom surface of the well 20. However, in practice, when the groove 30 slightly protrudes from the bottom surface, the device withstand voltage suddenly drops by about 150 V, and then the depth decreases further as the depth of the groove 30 increases. Was confirmed.

FIG. 7B is an enlarged cross-sectional view of the same main portion as above in an ON state. FIG. 7B shows a flow path of an electron current flowing into the semiconductor region 12 from a channel Ch formed on the side surface of the groove 30.
CP is shown. When a current flows into the semiconductor region 12 from the channel Ch in the vertical direction, a depletion region DZ where there is almost no charge due to the so-called J-FET effect is formed between the well 20 and the semiconductor region 12 from the current inflow point as shown in the figure. It is known that it spreads along the pn junction surface, which limits the spread angle indicated by θ in the figure in the semiconductor region 12 of the current flow path CP, so that the current density within this narrow angle θ increases,
It is considered that the ON voltage, which is a voltage drop in the flow path CP, increases. According to the results of the experiment, the increase in ON voltage
There is room for improvement by shortening the mutual spacing of the 30's, but there is a limit to this means, and it has been found that significant improvement cannot be expected even if the depth of the groove 30 projecting from the bottom of the well 20 is reduced. .

[0010] The above-mentioned reduction in withstand voltage and increase in on-voltage are both counter-effects that occur when the buried insulated gate is used to improve high-frequency characteristics and increase current capacity. In fact, this has been the biggest bottleneck in further improving the performance of semiconductor devices. In view of this situation, an object of the present invention is to reduce as much as possible the degree to which the withstand voltage of the insulated gate control semiconductor device is reduced or the degree to which the on-voltage is increased even when a buried insulated gate is employed. .

[0011]

According to the insulated gate control semiconductor device of the present invention, the purpose of preventing an increase in on-voltage is to:
A semiconductor region of one conductivity type formed on the surface side of the semiconductor substrate, a well of another conductivity type formed in a predetermined range of the semiconductor region, and a trench dug from the surface of the well to reach the semiconductor region; An insulating gate embedded in the trench, a source layer of one conductivity type diffused from the surface of the well in contact with the trench, and a first main terminal derived from the surface of the well and the source layer An insulated gate control semiconductor device comprising: a second main terminal derived from the back side of the semiconductor substrate; and a control terminal derived from the insulated gate , wherein the groove is formed near the groove of the well.
Shallow diffusion diffused shallower than well depth
This is achieved by providing a part . The well shallow
0.5μ deeper than the diffusion depth of the trench
m or more, preferably 1 μm or more.
Also in this case, the groove projects downward from the bottom of the well.
Making the depth smaller is advantageous in suppressing an increase in the on-state voltage .

The purpose of preventing the decrease in the withstand voltage described above is as follows.
According to the insulated gate control semiconductor device of the present invention, the well
In the peripheral portion, a deep diffusion portion is provided, which is deeper than the groove.
It is achieved by that. In addition, the deep diffusion part of the well
Minutes at least 50% deeper than other parts
It is good to diffuse. Also, the groove is below the bottom of the well.
The projecting depth is as small as possible, for example, 3 μm or less.
More desirably, the thickness is 0.5 to 2 μm, which is advantageous in increasing the withstand voltage .

The above-described configuration in which the peripheral portion of the well has a deep diffusion portion and the configuration in which a portion of the well has a shallow diffusion portion are implemented in combination with each other to prevent a reduction in breakdown voltage and an increase in on-voltage. The object can be achieved at the same time, and it is suitable for any structure, particularly, an insulated gate control semiconductor device having a vertical structure. In order to lead one main terminal from the well, it is preferable to form a contact layer of the same conductivity type diffused with a high impurity concentration on the surface portion of the well of the lead portion as in the conventional case.

In the method of manufacturing an insulated gate control semiconductor device according to the present invention using the well having the deep diffusion portion and the shallow diffusion portion, the peripheral portion of the surface of the one conductivity type semiconductor region on the front surface side of the semiconductor substrate has a predetermined range. At the same time, the well of the other conductivity type is diffused deeper than the groove in which the insulating gate is
The groove is formed near the groove on the surface of the predetermined area.
Other conductivity type impurities, the well territory to diffuse the deeper for partial shallow spreading by well region than the depth of the wells of that
Ion implantation at a lower dose than when forming the region , ion implantation of impurities of another conductivity type into the surface of the region where the groove is formed , and thermal diffusion of these ion-implanted impurities to form a deep diffusion portion at the periphery. A well including a region diffused shallower than the groove is formed inside the trench, the trench is dug from the surface of the well to a semiconductor region below, and an insulating gate is buried in the trench, and a surface of the well is formed. The source layer of one conductivity type is shallowly diffused into a portion in contact with the groove. When the above-mentioned contact layer is provided on the surface of the well, it is advantageous in terms of the process that the impurity of the other conductivity type is thermally diffused simultaneously with the impurity of one conductivity type of the source layer.

[0015]

According to the present invention, the contact between the bottom of the well and the semiconductor region is improved.
Focusing on the fact that the potential distribution at the time of off and the current distribution at the time of on in the semiconductor region can be controlled by providing irregularities on the pn junction surface, the insulated gate control semiconductor The present invention has succeeded in solving a conventional problem in which the adverse effect of reducing the breakdown voltage of the device or increasing the on-voltage occurs.

That is, by forming the deep diffusion portion referred to in the configuration of the preceding paragraph at the periphery of the well, the equipotential surface in the semiconductor region below the insulating gate is pushed downward from the surroundings so as to reduce the depletion layer when off. Thus, the electric field strength in the semiconductor region immediately below the insulated gate is reduced, and the withstand voltage of the insulated gate control semiconductor device is improved as compared with the related art. Further, by forming a shallow diffused portion in the structure described in the preceding paragraph and providing a trench for an insulating gate in a well portion near the shallow diffused portion, the above-mentioned structure is accompanied by a current flowing from the channel on the side surface of the trench into the semiconductor region at the time of ON. The depletion region created by the J-FET effect can be almost completely contained in the so-called recess at the bottom of the well corresponding to the shallow diffusion, thereby increasing the spread angle of the current flow path in the semiconductor region. This is to reduce the current density in the flow path by enlarging, thereby reducing the on-voltage of the insulated gate control semiconductor device, which is the voltage drop.

Further, the method of manufacturing an insulated gate control semiconductor device according to the present invention is suitable for forming a well having the above-mentioned deep diffusion portion and shallow diffusion portion. After the portion is first diffused to a predetermined depth, the impurity for the shallow diffusion portion is ion-implanted into the surface of this area at a low dose, and the impurity is ion-implanted at a predetermined dose into a part of the inner surface of the peripheral portion. By thermally diffusing them, a deep diffusion portion, a shallow diffusion portion, and a portion for an insulated gate of a well can be accurately formed to desired depths in a small number of steps.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a partially enlarged cross-sectional view of an insulated gate control semiconductor device according to the present invention, and FIG. 2 is an enlarged view of the distribution of equipotential surfaces when turned off and the distribution of current flow paths when turned on. FIG. 3 is a diagram showing a breakdown voltage characteristic, FIG. 4 is a diagram showing an on-voltage characteristic, and FIG. 5 is a diagram showing a state of a main process in a manufacturing method of the present invention corresponding to the insulated gate control semiconductor device of FIG. FIG. 3 is an enlarged sectional view of a main part of the wafer indicated by. In these embodiments, the well has a deep diffusion portion and a shallow diffusion portion. However, the present invention can be practiced by providing only one of these in the well. Although the insulated gate control semiconductor device is a field effect transistor, the present invention can be applied to a semiconductor device such as an insulated gate bipolar transistor or a thyristor having an insulated gate and having a similar structure.

FIG. 1 shows an insulated gate control semiconductor device of the present invention in the same manner as in the conventional example of FIG. 6 and is denoted by the same reference numerals, and the following mainly describes the differences. The difference from the conventional structure is that the p-type well 20 formed from the surface of the n-type semiconductor region 12 of the semiconductor substrate 10 has a deep diffusion portion 21 on the peripheral edge thereof and is embedded in the groove 30 inside the same. The point that the shallow diffusion portion 22 is provided near the insulated gate 40 is that the n-type source layer 50 and the well contact the trench 30.
A p-type contact layer 23 for 20 is provided, one main terminal S as a source terminal is derived from the well 20 and the source layer 50 via the electrode film 61, and from the back side of the semiconductor substrate 10 via the electrode film 62. The point that the other main terminal D that is the drain terminal is derived and the control terminal G is derived from the insulated gate 40 are all the same as the conventional example of FIG. Well on field oxide film 13
This is the same in that a field plate 63 placed at the same potential as 20 is provided.

Next, the effect of the deep diffusion portion 21 and the shallow diffusion portion 22 of the well 20, which is a feature of the present invention, will be described with reference to FIG. 2 corresponding to FIG. FIG. 2 (a) shows how the depletion layer spreads in the semiconductor region 12 in the off state.
As can be seen from comparison with FIG. 7 (a), the equipotential surface EP is pushed down entirely in the inner region on the left side in FIG. Therefore, the depletion layer easily spreads in the semiconductor region 12 immediately below the groove 30, which is a conventional weak point. 2.5 to 4 × 10 when the impurity concentration of the semiconductor region 12 is 10 ¹⁴ to 10 ¹⁶ atoms / cm ³
Avalanche breakdown occurs at an electric field strength of ⁵ V / cm.
In the present invention, the electric field intensity immediately below the groove
This can relax and improve the withstand voltage. In addition,
Even when the trench 30 is provided near the shallow diffusion portion 22 as in this example, the spread of the depletion layer in the semiconductor region 12 is not significantly affected.

FIG. 2B shows a flow path CP of the electron current in this example, which flows into the semiconductor region 12 from the channel Ch on the side surface of the groove 30 in the ON state. As can be seen from a comparison with FIG. 7B, since the trench 30 is provided near the shallow diffusion portion 22, the depletion region DZ generated by the J-FET effect described above is reduced to the shallow diffusion portion.
As shown in the figure, the current flow path CP in the semiconductor region 12 almost fits in the recess on the bottom surface of the well 20 corresponding to 22.
Is wider than before. Thus, in the present invention, the current density in the flow path CP can be reduced to reduce the voltage drop, and the ON voltage of the insulated gate control semiconductor device can be reduced. Note that, as can be easily understood from the drawing, even when the deep diffusion portion 21 is provided, the distribution of the current flow path CP at the time of ON is hardly affected by the provision.

Next, referring to FIGS. 3 and 4, the results of experiments relating to the withstand voltage and the on-voltage of the insulated gate control semiconductor device having the structure shown in FIG. 1 will be introduced. FIG. 3 shows the characteristics of the breakdown voltage BV or the avalanche breakdown voltage on the vertical axis with respect to the depth d of the groove 30 on the horizontal axis. The characteristic A is the case of the present invention, and the characteristic B is FIG. This is the case of the conventional structure of FIG. In this experiment, the diffusion depth of the well 20 was set to 4.5 μm in the conventional structure corresponding to the characteristic B, whereas the diffusion depth of the deep diffusion portion 21 in the well 20 was adjusted in the structure shown in FIG. The depth was 4.5 μm, the diffusion depth of the shallow diffusion portion 22 was 2 μm, and the diffusion depth of the trench 30 was 2.5 μm. The semiconductor region 12 has a thickness of 50 μm and a specific resistance of 42 Ωcm.

According to the characteristic B of the conventional structure, while the depth d of the groove 30 is smaller than the diffusion depth d1 of the well 20, the breakdown voltage BV is constant at 700 V, but the depth d of the groove 30 is equal to the depth of the well 20. If the voltage exceeds d1 even slightly, the breakdown voltage BV rapidly decreases to 550V or less. This is probably because the electric field concentrates on the semiconductor region 12 immediately below the groove 30 in the conventional structure. On the other hand, in the characteristic A of the present invention, when the depth d of the groove 30 exceeds the depth d2 of the well 20 in that portion, the withstand voltage BV decreases from the previous 700 V, but the degree of decrease is much smaller than in the conventional case. Thus, the withstand voltage BV is about 650 V when the depth d is 4 μm, and a withstand voltage of about 600 V can be obtained even when the depth d is 6 μm. This is presumably because the deep diffusion portion 21 at the peripheral edge of the well 20 easily spreads the depletion layer in the semiconductor region 12 immediately below the groove 30, and the electric field intensity is reduced.

FIG. 4 shows the dependence of the ON voltage FV on the vertical axis on the arrangement pitch p of the grooves 30 or the insulating gates 40 on the horizontal axis when the well 20 has the same structure as in FIG. As before, when the characteristic B is the conventional structure, the characteristics A1 and A2 are the case of the structure of FIG. 1 according to the present invention. In the conventional structure, the depth of the groove 30 is 6 μm, and in the structure of the present invention, the depth of the groove 30 is Is 4 for characteristic A1.
μm, and 3 μm for the characteristic A2. When the arrangement pitch p of the grooves 30 is reduced for a certain current rating, the on-voltage FV is generally reduced as shown in the figure. However, in the characteristic B of the conventional structure, when the arrangement pitch p is further reduced from 15 to 20 μm, the on-voltage FV becomes On the contrary, it rises. This is presumably because if the arrangement pitch p is too narrow, the influence of the depletion region DZ in FIG. 7B becomes stronger and the spread angle θ of the current flow path CP becomes smaller. On the contrary,
In the characteristics A1 and A2 in the case of the present invention, the on-voltage FV is lower than in the prior art, and almost no adverse effect due to the reduction of the arrangement pitch p appears. This is because the shallow diffusion region 22 in FIG.
It is thought to confine DZ. Also, when the groove 30 is shallow, the characteristic A2 has a slightly lower on-voltage FV.
The smaller the protruding depth of the well 20 from the bottom is the above J-
It is considered that the FET effect becomes slight.

As can be seen from the characteristics shown in FIGS. 3 and 4 described above, in the insulated gate control semiconductor device of the present invention, the groove 30 is used.
Is less than about 3μm protruding from the bottom of the well 20,
More preferably, the thickness is set to 0.5 to 2 μm, which is advantageous for improving the breakdown voltage BV and reducing the on-voltage FV. In addition, well 20
The diffusion portion 21 deeper than the depth of the dug portion of the groove 30 is 50
%, It is advantageous that the diffusion portions 22 are each diffused so as to be shallower than 0.5 μm, preferably 1 μm or more.

Finally, a method of manufacturing the insulated gate control semiconductor device of the present invention corresponding to the structure of FIG. 1 will be described with reference to FIG. The figure is a cross-sectional view of a portion corresponding to FIG. 1, but the semiconductor substrate 10 or its n-type semiconductor region 12 as a wafer is shown.
It is shown. The semiconductor region 12 or the epitaxial layer has a thickness of, for example, 50 μm and a specific resistance of about 40 Ωcm. FIG. 5 (a) shows the diffusion step of the deep diffusion portion 21 for the well 20. The field oxide film 13 on the right side of the figure is formed by photoetching from an oxide film having a thickness of about 1 μm obtained by thermally oxidizing the semiconductor region 12, and the left portion surrounded by the field oxide film 13 is a range in which the well 20 is formed.
In the step of FIG. 5A, boron is used as a p-type impurity in the periphery of this range, for example, at an accelerating voltage of 50 keV and 4 × 10 ¹³ atoms / cm 3.
After ion implantation at a dose of about ² , a deep diffusion portion 21 for a well is formed at a predetermined depth by thermal diffusion at a high temperature of about 1150 ° C. for 2 to 3 hours. During this thermal diffusion, the surface of the semiconductor region 12 is covered with an oxide film 14 of 0.15 to 0.3 μm.

FIG. 5B shows a shallow diffusion portion 22 for wells.
And a step of introducing boron through the oxide film 14 to the entire surface of the semiconductor region 12 using the field oxide film 13 as a mask.
At a keV accelerating voltage, ions are implanted at a low dose of about 4 × 10 ¹³ atoms / cm ² or slightly lower. FIG. 5 (c) shows a p-type impurity 20a for a portion where a well groove 30 is to be provided.
Before that, a low-temperature oxide film 15 is formed to a thickness of, for example, 1 μm by a CVD method or the like, and a window is opened by photoetching. The low-temperature oxide film 15 is formed at a low temperature of 400 to 450 ° C. so that the depth of the deep diffusion portion 21 does not change. Boron as the impurity 20a is ion-implanted at a dose of ² × 10 ³ atoms / cm ² at an acceleration voltage of 80 keV, for example, using the low-temperature oxide film 15 as a mask.

FIG. 5 (d) shows a thermal diffusion step for forming the well 20. For example, the above-described introduced impurities 22a and 20a are simultaneously thermally diffused by heat treatment at a high temperature of 1150 ° C. for 1 to 2 hours to deeply diffuse the impurities. The well 20 has a portion 21 and a shallow diffusion portion 22. As a result, the depth of each portion of the well 20 is, for example, 4.5 μm for the deep diffusion portion 21, 2 μm for the shallow diffusion portion 22, and 2.5 μm for the other portions. As described above, according to the method of the present invention, the depth of each part of the well 20 can be accurately determined with a small number of steps by first forming the deep diffusion portion 21 and then introducing the impurity in two steps and simultaneously performing thermal diffusion. Can be controlled.

FIG. 5E shows a process of digging the groove 30.
A dry etching method using the low-temperature oxide film 15 formed as shown in FIG. 1C as a mask, preferably a reactive ion etching method, is used to form a 1 to 2 .mu.
And digging it to a depth of, for example, 3 to 4 μm so as to reach the semiconductor region 12 thereunder. Then, the low-temperature oxide film 15 is removed using an etching solution such as a hydrofluoric acid, and the field oxide film is removed. The state shown in FIG. FIG. 5 (f) shows a process of arranging the insulating gate 40. First, a very thin gate oxide film 41 is formed by oxidizing the whole surface, and then polycrystalline silicon for the gate 42 is shown by a dashed line in the figure by the CVD method. As shown in the drawing, the insulating gate 40 is buried in the groove 30 by growing the entire surface and performing photoetching. Note that the actual planar pattern of the groove 30 and the insulating gate 40 is preferably a comb-like shape connected to each other at locations other than the illustrated cross section.

FIG. 5 (g) shows a step of diffusing the source layer 50. In this embodiment, the p-type contact layer 23 is provided in the well 20, so that boron is not in contact with the groove 30 and the n-type is used. For example, arsenic is ion-implanted at a high impurity concentration so as to be in contact with the groove 30 for the source layer 50, and then a shallow n-type source layer 50 and an n-type contact layer 23 deeper than that are formed by simultaneous thermal diffusion. Put in. Finally, FIG. 5 (h) shows an electrode film disposing step, in which the surface of the contact layer 23 and the surface of the source layer 50 are short-circuited by the usual aluminum electrode film 61 to form one main terminal S of FIG. A field plate 63 connected to the well 20 is formed on the field oxide film 13 from an aluminum film. Note that the control terminal G of the insulated gate 40 in FIG. 1 is led out from the connection portion of the comb-like pattern, and the other terminal D is led out from the back side of the semiconductor substrate 10.

According to the above-described manufacturing method, each portion of the well 20 having the unevenness on the bottom surface is formed with an accurate diffusion depth, so that the insulated gate control semiconductor device has a withstand voltage of, for example, 600 V and is stable with good reproducibility. Voltage can also be reduced. In addition, by reducing the arrangement pitch of the grooves 30 to about 10 μm or less and miniaturizing the pattern, the high-frequency characteristics of the field-effect transistor are improved as compared with the conventional case, and the insulated gate bipolar transistor has a chip area of several mm square. One hundred insulated gates 40 can be arranged to provide a current capacity of several tens of amps. The insulated gate control semiconductor device of the present invention can operate at high speed by applying a control voltage of several to 15 V to the control terminal.

In the above-described embodiment, the deep diffusion portion 21 of the well 20 is provided on the periphery thereof. However, if necessary, the deep diffusion portion 21 is formed inside the well 20 to improve the breakdown voltage. Can be further enhanced. In this case, the trench 30 and the insulating gate 40 are sandwiched by the deep diffusion portion 21, and the insulated gate control semiconductor device has a so-called composite structure of unit structures. As can be seen from the embodiment, the area required for forming the deep diffusion portion 21 inside the well 20 may be substantially the same as the above-described arrangement pitch p of the grooves 30. As described above, the present invention is not limited to the embodiments and can be carried out in various modes as necessary or necessary.

[0033]

As described above, in the insulated gate control semiconductor device of the present invention, the well is formed so as to form a diffusion part deeper than the inner part from the surface of the semiconductor region to the peripheral part, or to form a shallow diffusion part in part. A trench is dug from the surface of the well to reach the semiconductor region underneath, an insulating gate is buried therein, and a source layer is diffused from the surface of the well so as to contact the groove. Thus, the following effects can be obtained.

(A) By forming a deep diffusion portion in the peripheral portion of the well and digging a groove in a shallower inner portion to bury the insulating gate, a depletion layer is formed in the semiconductor region below the groove when off. It is easy to spread, the electric field intensity immediately below the groove is reduced, and the breakdown voltage of the insulated gate control semiconductor device can be improved. (b) A depletion region generated near the point where current flows into the semiconductor region from the channel on the side surface of the groove when the shallow diffusion is formed in the well and an insulated gate buried in the groove is provided near the well. To reduce the on-voltage of the insulated gate control semiconductor device by increasing the spread angle of the current flow path in the semiconductor region and reducing the current density in the flow path it can.

(C) The effect of improving the breakdown voltage of the deep diffusion part and the effect of reducing the on-voltage of the shallow diffusion part do not interfere with each other or are mutually reduced as described in the embodiment. Therefore, by forming both a deep diffusion portion and a shallow diffusion portion in the well, it is possible to simultaneously improve the withstand voltage and reduce the on-voltage of the insulated gate control semiconductor device.

(D) Since not only the current capacity can be increased but also the on-voltage can be reduced by reducing the pitch at which the grooves or the insulating gates are arranged, the fine patterning of the insulated gate control semiconductor device can be further promoted and its high frequency characteristics can be improved. And the on-time current characteristics can be improved. Further, in the method of manufacturing an insulated gate control semiconductor device according to the present invention, a deep diffusion portion is first diffused to a predetermined depth in a peripheral portion of a region where a well is to be formed, and then an impurity for a shallow diffusion portion is doped on a surface in this range. Impurities are ion-implanted into a part of the inner surface of the peripheral portion at a low dose at a predetermined dose, and are simultaneously thermally diffused, thereby providing a deep diffusion portion, a shallow diffusion portion, and an insulating gate portion. Wells can be formed with a small number of steps and while precisely controlling the depth of each of these portions to desired values.

[Brief description of the drawings]

FIG. 1 is a partially enlarged cross-sectional view of an insulated gate control semiconductor device according to the present invention.

FIGS. 2A and 2B show the state of the insulated gate control semiconductor device shown in FIG. 1 when it is turned off and when it is turned on. FIG. 2A shows the distribution of equipotential surfaces when it is off, and FIG. It is a principal part expanded sectional view of FIG. 1 which respectively shows the distribution of a road.

FIG. 3 is a characteristic diagram showing a breakdown voltage characteristic of the insulated gate control semiconductor device of FIG. 1;

FIG. 4 is a characteristic diagram showing on-voltage characteristics of the insulated gate control semiconductor device of FIG. 1;

FIGS. 5A and 5B show the manufacturing method of the present invention for the insulated gate control semiconductor device of FIG. 1 in the state of each of main steps, wherein FIG. 5A shows a deep diffusion part diffusion step, and FIG. (C) is a process for introducing impurities for wells, (d) is a thermal diffusion process, (e) is a trench excavation process, and (f) is an insulating gate. FIG. 7 (g) is an enlarged cross-sectional view of a principal part of the wafer showing the state of the source layer diffusion step, and FIG. 7 (h) shows the state of the electrode film arrangement step.

FIG. 6 is a partially enlarged sectional view of a conventional insulated gate control semiconductor device.

7A and 7B show states of the insulated gate control semiconductor device shown in FIG. 6 when it is turned off and when it is turned on. FIG. 7A shows the distribution of equipotential surfaces when it is off, and FIG. It is a principal part enlarged sectional view of FIG. 6 which shows the distribution of a road, respectively.

[Explanation of symbols]

Reference Signs List 10 semiconductor substrate or wafer 12 semiconductor region or epitaxial layer 20 well 21 well deep diffusion portion 22 well shallow diffusion portion 30 groove 40 insulating gate 50 source layer A Withstand voltage characteristic of insulated gate control semiconductor device of the present invention A1 Insulation of the present invention On-voltage characteristics of gate control semiconductor device A2 On-voltage characteristics of insulated gate control semiconductor device of the present invention B Withstand voltage and on-voltage characteristics of conventional insulated gate control semiconductor device BV Withstand voltage of insulated gate control semiconductor device CP Current path when on D Other main terminal or drain terminal d Depth of groove DZ Depletion region EP Equipotential surface when off FV ON voltage of insulated gate control semiconductor device G Control terminal p Arrangement pitch of groove S One main terminal or source terminal

Claims (3)

(57) [Claims] 1. A semiconductor region of one conductivity type formed on a surface side of a semiconductor substrate, a well of another conductivity type formed in a predetermined range of the semiconductor region, and a well from the surface of the well to the semiconductor region. A trench, an insulated gate embedded in the trench, a source layer of one conductivity type diffused from the surface of the well in contact with the trench, and a source layer derived from the surface of the well and the source layer. An insulated gate control semiconductor device including a first main terminal, a second main terminal derived from the back side of the semiconductor substrate, and a control terminal derived from the insulated gate. An insulated gate control semiconductor device having a shallow diffusion portion that is diffused shallower than a depth of a well where the groove is formed. 2. The insulated gate control semiconductor device according to claim 1 , wherein the well has a deeply diffused portion deeper than the groove at a peripheral portion of the well. 3. A step of diffusing a well of another conductivity type deeper than a groove in which an insulating gate is buried in a peripheral portion of a predetermined range on a surface of a semiconductor region of one conductivity type on a surface side of a semiconductor substrate; The groove is formed near the groove on the surface
A well region which diffuses impurities of another conductivity type to the well region which is diffused shallower than the depth of the well of the portion;
A step of ion-implanting at a lower dose than forming a step, a step of ion-implanting impurities of another conductivity type into the surface of the region where the groove is formed, and a step of thermally diffusing these ion-implanted impurities to form a peripheral portion. Forming a well including a region diffused shallower than the groove inside the deep diffusion portion, digging the groove from the surface of the well to a lower semiconductor region, insulating in the groove; A step of embedding a gate and a step of shallowly diffusing a source layer of one conductivity type in a portion in contact with the groove on the surface of the well, and forming a first main terminal from the well and the source layer in a second direction from the back side of the semiconductor substrate. A method for manufacturing an insulated gate control semiconductor device, wherein a main terminal is derived from a control terminal from an insulated gate.