JP3915180B2 - Trench type MOS semiconductor device and manufacturing method thereof - Google Patents

Trench type MOS semiconductor device and manufacturing method thereof Download PDF

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JP3915180B2
JP3915180B2 JP17788597A JP17788597A JP3915180B2 JP 3915180 B2 JP3915180 B2 JP 3915180B2 JP 17788597 A JP17788597 A JP 17788597A JP 17788597 A JP17788597 A JP 17788597A JP 3915180 B2 JP3915180 B2 JP 3915180B2
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trench
layer
channel region
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JPH1126758A (en
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武義 西村
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、トレンチ内に絶縁膜を介して埋め込まれた制御用のゲート電極層を有する、ＭＯＳＦＥＴ（金属−酸化膜−半導体構造のゲート電極を有する電界効果トランジスタ）、ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）、絶縁ゲートサイリスタ、およびそれらの集合体であるインテリジェントパワーモジュール（ＩＰＭ）などのトレンチ型ＭＯＳ半導体装置とその製造方法に関する。
【０００２】
【従来の技術】
図６は、従来のトレンチ構造を有するＭＯＳ半導体装置の一例であるＭＯＳＦＥＴの主要部の部分断面図である。
半導体基板であるｎドレイン層１の表面層にｐチャネル領域２が形成され、そのｐチャネル領域２の表面層にｎソース領域３が形成されている。ｎソース領域３の表面からｐチャネル領域２を貫通してｎドレイン層１に達するトレンチ８が形成され、そのトレンチ８の内部には、ゲート酸化膜４を挟んで多結晶シリコンからなるゲート電極層５が充填されている。ｎソース領域３の表面上には、ｐチャネル領域２の表面に共通に接触するソース電極７が、またｎドレイン層１の他面にはドレイン電極９が設けられている。６はゲート電極層５を覆う絶縁膜である。ｎドレイン層１を不純物濃度の異なる二層とすることもある。
【０００３】
ゲート電極層５に接触して設けられた図示されないゲート電極に適当な電圧を印加することにより、トレンチ８の内壁に沿ったｐチャネル領域２の表面層に反転層（チャネル）を生じ、ドレイン電極９とソース電極７間が導通して電流が流れる。
【０００４】
【発明が解決しようとする課題】
図６において、トレンチ構造を有するＭＯＳ型半導体装置を製造するには、ｎソース領域３と、ｐチャネル領域２を貫通してｎドレイン層１に達するトレンチ８を掘り、そのトレンチ８にゲート酸化膜４を介してゲート電極層５を充填しなければならない。もし、トレンチ８の深さが、ｐチャネル領域２より浅い場合にはｐチャネル領域２中に反転層が形成されない部分ができ、電流通路が形成されないので、動作しない。従って、トレンチ８の深さとｐチャネル領域２の深さとの間の関係を所望の特性に合わせて設定することが重要である。
【０００５】
図７は、耐圧におけるトレンチ８の深さとｐチャネル領域２の深さとの間の差ｘの依存性を示す特性図である。横軸は、トレンチ８の深さとｐチャネル領域２の深さとの差ｘ、縦軸は耐圧である。差ｘを大きくすると、耐圧が低下していることがわかる。高耐圧を達成するには、差ｘを小さい値に抑えなければならない。
一方でこの差ｘを小さくすると、オン抵抗が増大するという不具合が生じた。これは、差ｘが小さいと、ゲート電極に電圧を印加した際に、トレンチ１０の底部に十分な反転層が形成されず、チャネル抵抗が増すためと考えられる。
【０００６】
従って、耐圧が高く、オン抵抗の小さいＭＯＳＦＥＴとするためには、トレンチ深さとチャネル領域の差ｘを、非常に狭い範囲で制御しなければならないことになり、製造が困難である。またもし、この差ｘにばらつきがあると、耐圧や、オン抵抗がばらつくことになる。実際に、オン抵抗のバラツキが同一ロット内で２０〜３０％になることがあった。そしてこの問題は、トレンチ型ＭＯＳＦＥＴに限らず、ＭＯＳ構造のゲートをもつトレンチ型半導体装置に共通の問題である。
【０００７】
以上の問題に鑑み本発明の目的は、耐圧が高く、オン抵抗が小さく、しかも製造が容易なトレンチ構造を有するトレンチ型ＭＯＳ半導体装置の製造方法を提供することにある。
【０００８】
【課題を解決するための手段】
前記の課題を解決するため本発明は、トレンチの第一導電型ドレイン層への突出を0.1〜0.5μｍとし、トレンチの底部に第一導電型ドレイン層より高濃度の第一導電型ウェル領域を有するものとすれば、耐圧が高く、トレンチ深さとチャネル領域深さとの差ｘが小さくても、低抵抗の第一導電型ウェル領域が反転層の働きをするため、オン抵抗の増大が抑えられることになる。また、トレンチ深さとチャネル領域深さとの差ｘの許容範囲が広くなる。
このようなトレンチ型ＭＯＳ半導体装置の製造方法として、第一導電型の不純物のイオン注入および熱処理により、トレンチの底部に第一導電型ウェル領域を形成するものとする。注入角の浅いイオン注入とすれば、トレンチの側面には殆どイオンが注入されない。そして、仮にトレンチの側面に注入されたとしても、深さが浅いので、表面層の僅かな量のエッチングで除去できる。トレンチの底部には、ほぼ垂直に注入されるので、深く注入できる。
そして、トレンチ形成用の絶縁膜マスクを、トレンチ形成後に後退エッチングさせ、第一導電型不純物のイオン注入および熱処理により、第一導電型ソース領域とトレンチ底部の第一導電型ウェル領域とを同時に形成するものとする。そのようにすれば、第一導電型ソース領域と第一導電型ウェル領域とを同時に形成できるので、フォトリソグラフィ工程を別々に行う必要が無く、工程が短縮できる。
【０００９】
【００１０】
【００１１】
【００１２】
【００１３】
【発明の実施の形態】
以下、実施例にもとづき、図を参照しながら本発明の実施の形態を説明する。なお、ｎ、ｐを冠した領域、層等はそれぞれ電子、正孔を多数キャリアとする領域、層を意味するものとし、第一導電型をｎ型、第二導電型をｐ型とした例を示すが、これを逆にすることもできる。
【００１４】
［実施例１］
図１は、本発明第一の実施例のＭＯＳＦＥＴの主要部の上層部分の部分断面図である。図に示した主要部以外に、主に周縁領域に耐圧を分担する部分があるが、本発明の本質に係る部分でないので、省略している。
エピタキシャルウェハの成長層であるｎドレイン層１の表面層にｐチャネル領域２が形成され、そのｐチャネル領域２の表面層にｎソース領域３が形成されている。ｎソース領域３の表面からｐチャネル領域２を貫通してｎドレイン層１に達するトレンチ８が形成され、そのトレンチ８の内部には、ゲート酸化膜４を挟んで多結晶シリコンからなるゲート電極層５が充填されている。ｎソース領域３の表面上には、ｐチャネル領域２の表面と共通に接触するソース電極７が設けられている。この例では、絶縁膜６の上にソース電極７が延長されているが、必ずこのようにしなければならないわけではない。この実施例１のＭＯＳＦＥＴが、従来のトレンチ型ＭＯＳＦＥＴと異なっている点は、トレンチ８の底面部分にｎドレイン層１より不純物濃度の高いｎ+ ウェル領域１０が設けられている点である。ｎドレイン層１の裏面には、図示されていない低抵抗のサブストレートとその裏面に設けられたドレイン電極がある。また、ゲート電極層５に接触する金属のゲート電極も図示されていない。
【００１５】
図３（ａ）〜（ｅ）は、図１のＭＯＳＦＥＴの製造方法を示す主な製造工程ごとの断面図である。エピタキシャルウェハの成長層であるｎドレイン層１の表面層にほう素イオン、次いでひ素イオンの注入、熱処理によりｐチャネル領域２、およびｎソース領域３を形成し、更に表面にトレンチ形成のため酸化膜１１を形成し、フォトリソグラフィにより、パターニングする［図３（ａ）］。例えば、エピタキシャルウェハのサブストレートは、４ｍΩ・ｃｍで、厚さ３５０μｍ、ｎドレイン層は０．５５Ω・ｃｍで、厚さ１０μｍである。ｐチャネル領域２、ｎソース領域３の深さは、それぞれ２．５μｍ、０．６μｍである。
【００１６】
酸化膜１１のパターンをマスクとして、ＨＢｒガスを用いたドライエッチングによりトレンチ８を形成する［同図（ｂ）］。このときトレンチ８の深さは、ｐチャネル領域２の拡散深さより少し深くする。トレンチの寸法は、例えば、幅１μｍ、深さ２．７μｍ、間隔３．５μｍである。すなわち、トレンチ８の深さとｐチャネル領域２の拡散深さとの差ｘは約０．２μｍとなる。
【００１７】
トレンチ形成用の酸化膜１１をそのまま使用し、燐イオン１２を注入する［同図（ｃ）］。イオン注入の条件は、加速電圧１５０ｋＶ、ドーズ量を１×１０13／ｃｍ2 とし、注入角は０°とする。注入角の浅いイオン注入とすれば、トレンチの側面には殆どイオンが注入されない。仮にトレンチの側面に注入されたとしても、深さが浅いので、表面層の僅かな量のエッチングで除去できる。トレンチの底部には、ほぼ垂直に注入されるので、深く注入できる。１３はイオン注入領域である。
【００１８】
酸化膜１１を除去した後、熱酸化により、トレンチ内面に厚さ１００ｎｍのゲート酸化膜４を形成する。（１０５０℃、６０分）この熱処理により、トレンチ８底部に注入された燐イオンが活性化され、拡散深さ０．５μｍのｎ+ ウェル領域１０が形成される［同図（ｄ）］。
減圧ＣＶＤにより、トレンチ８内にゲート電極層５となる多結晶シリコンを埋め込み、余分な多結晶シリコンをエッチングした後、ＣＶＤによりほうけい酸ガラス（ＢＰＳＧ）の絶縁膜６を堆積し、フォトリソグラフィにより、パターニングし、更にスパッタリングによりソース電極７となるアルミニウム合金層を堆積し、パターニングする［同図（ｅ）］。図示していないが、ｎドレイン層１の裏面側にＴｉ、Ｎｉ、Ａｕの金属層を蒸着してドレイン電極とする。
【００１９】
このように、トレンチ８の底部にｎドレイン層１より抵抗率の低いｎ+ ウェル領域１０を設けることにより、ウェハ内でのオン抵抗のバラツキは大幅に改善され、５％以内となり、特性が安定した。また、オン抵抗の増大の問題が解決されるため、トレンチの深さは浅めの０．１〜０．５μｍの間に制御すればよいことになり、耐圧を高くできる。そして、トレンチ深さの許容範囲が広くなって、製造が容易になった。
【００２０】
[実施例２]
図４（ａ）〜（ｅ）は、図１のＭＯＳＦＥＴの別の製造方法を示す主な製造工程ごとの断面図である。半導体基板であるｎドレイン層１の表面層にほう素イオンの注入、熱処理によりｐチャネル領域２を形成し、更に表面にトレンチ形成のため酸化膜１１を形成し、フォトリソグラフィにより、パターニングする［図４（ａ）］。
【００２１】
酸化膜１１のパターンをマスクとして、ドライエッチングによりトレンチ８を形成する［同図（ｂ）］。
ウェットエッチングでトレンチ形成マスクとして使用した酸化膜１１のパターンを後退エッチングし、トレンチ８の開口付近のｐチャネル領域２の表面を露出させた後、ひ素イオンを注入する［同図（ｃ）］。１３はひ素イオン注入領域である。トレンチ８の底部だけでなく、開口部の近傍にもイオン注入され、ソース領域３形成のためのイオン注入となる。従ってこのイオン注入のドーズ量は、実施例１より多く、５×１０13／ｃｍ2 程度とするのがよい。
【００２２】
酸化膜１１を除去した後、熱酸化により、トレンチ内部にゲート酸化膜４を形成する。このとき、熱処理により、ｐチャネル領域２の表面層およびトレンチ８底部に注入されたひ素イオンが活性化され、ｎソース領域３、ｎ+ ウェル領域１０が形成される［同図（ｄ）］。
この後、実施例１と同様にして、トレンチ８内にゲート電極層５となる多結晶シリコンを埋め込み、余分な多結晶シリコンをエッチングした後、ＣＶＤにより絶縁膜６を堆積し、フォトリソグラフィにより、パターニングし、更にスパッタリングによりソース電極７となるアルミニウム合金層を堆積し、パターニングする［同図（ｅ）］。
【００２３】
このような方法をとれば、ｎ+ ウェル領域１０を形成するためのイオン注入を特別に行う必要がなく、実施例１の製造方法より工程が短縮できる。
［参考例］
図２は、本発明参考例のＭＯＳＦＥＴのセル断面図である。
この例は、ｎソース領域３の表面からトレンチ８が形成され、そのトレンチ８の底部にｎ+ ウェル領域１０が形成されているのは、図１の実施例１と同様であるが、トレンチ８の深さがｐチャネル領域２の拡散深さより浅い点が異なっている。ただし、トレンチ８の底部に形成されたｎ+ ウェル領域１０が、ｎドレイン層１に達している。
【００２４】
図５（ａ）〜（ｅ）は、図２のＭＯＳＦＥＴの製造方法を示す主な製造工程ごとの断面図である。半導体基板であるｎドレイン層１の表面層にほう素イオン、次いでひ素イオンの注入、熱処理によりｐチャネル領域２、およびｎソース領域３を形成し、更に表面にトレンチ形成のため酸化膜１１を形成し、フォトリソグラフィにより、パターニングする［図５（ａ）］。
【００２５】
酸化膜１１のパターンをマスクとして、ドライエッチングによりトレンチ８を形成する［同図（ｂ）］。このときトレンチ８の深さは、ｐチャネル領域２の拡散深さより少し浅くする。
トレンチ形成用の酸化膜１１をそのままマスクとして使用し、燐イオンを注入する［同図（ｃ）］。この時注入角は０°とする。１３はイオン注入領域である。
【００２６】
酸化膜１１を除去した後、熱酸化により、トレンチ内部にゲート酸化膜４を形成する。このとき、熱処理により、トレンチ８底部に注入された燐イオンが活性化され、ｎドレイン層１に接するｎ+ ウェル領域１０が形成される［同図（ｄ）］。
減圧ＣＶＤにより、トレンチ８内にゲート電極層５となる多結晶シリコンを埋め込み、余分な多結晶シリコンをエッチングした後、ＣＶＤにより絶縁膜６を堆積し、フォトリソグラフィにより、パターニングし、更にスパッタリングによりソース電極７となるアルミニウム合金層を堆積し、パターニングする［同図（ｅ）］。
【００２７】
この場合、従来なら、反転層が形成されないためＭＯＳ半導体装置は動作しないが、本参考例のようにトレンチ８の底部にｎドレイン層１より抵抗率の低いｎ+ ウェル領域１０を設けることにより、トレンチ８の深さがｐチャネル領域の拡散深さより浅い場合でも、反転層がｎソース領域３からｎドレイン層１までつながり、動作可能となる。
【００２８】
このようにすることにより、ウェハ内でのオン抵抗のバラツキ等が大幅に改善され、また、トレンチ深さの許容範囲が広くなり、製造が容易になった。
【００２９】
【発明の効果】
以上説明したように本発明によれば、トレンチ内にゲート絶縁膜を介してゲート電極層が設けられたトレンチ型ＭＯＳ半導体装置において、トレンチの底部に高濃度の第一導電型ウェル領域を設けることによって、オン抵抗が安定し、トレンチの深さと第二導電型チャネル領域の深さとの差ｘを0.1 〜 0.5 μｍと小さい値としても従来のようなオン抵抗の増大が無いため、耐圧を高く保てるようになる。また差ｘの許容範囲が広くなり、製造が容易になる。
【００３０】
そして本発明の様なトレンチ型ＭＯＳ半導体装置の製造方法として、トレンチ形成後、その形成に用いた絶縁膜パターンを後退エッチングさせ、第一導電型不純物のイオン注入および熱処理をおこない、ソース領域と第一導電型ウェル領域を同時に形成することで、工程を短縮できることを示した。
【図面の簡単な説明】
【図１】 本発明実施例１のＭＯＳＦＥＴの部分断面図
【図２】 本発明参考例のＭＯＳＦＥＴの部分断面図
【図３】 （ａ）〜（ｅ）は図１の実施例１のＭＯＳＦＥＴの製造工程順の断面図
【図４】 （ａ）〜（ｅ）は図３の製造方法と異なる実施例２の製造方法の製造工程順の断面図
【図５】 （ａ）〜（ｅ）は図２の参考例のＭＯＳＦＥＴの製造工程順の断面図
【図６】 従来のＭＯＳＦＥＴの部分断面図
【図７】 トレンチ深さとｐチャネル領域の拡散深さとの差ｘによる耐圧の変化を示す特性図
【符号の説明】
１ ｎドレイン層
２ ｐチャネル領域
３ ｎソース領域
４ ゲート酸化膜
５ ゲート電極層
６ 絶縁膜（ＢＰＳＧ）
７ ソース電極
８ トレンチ
９ ドレイン電極
１０ ｎ+ ウェル領域
１１ 酸化膜
１２ 燐イオン
１３ イオン注入領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOSFET (field effect transistor having a gate electrode of a metal-oxide film-semiconductor structure) and an IGBT (insulated gate bipolar transistor) having a control gate electrode layer embedded in the trench through an insulating film. The present invention relates to a trench type MOS semiconductor device such as an insulated gate thyristor and an intelligent power module (IPM) which is an assembly thereof, and a manufacturing method thereof.
[0002]
[Prior art]
FIG. 6 is a partial cross-sectional view of the main part of a MOSFET which is an example of a MOS semiconductor device having a conventional trench structure.
A p channel region 2 is formed on the surface layer of the n drain layer 1 which is a semiconductor substrate, and an n source region 3 is formed on the surface layer of the p channel region 2. A trench 8 is formed from the surface of n source region 3 through p channel region 2 to reach n drain layer 1. Inside trench 8, a gate electrode layer made of polycrystalline silicon with gate oxide film 4 interposed therebetween 5 is filled. On the surface of the n source region 3, a source electrode 7 in common contact with the surface of the p channel region 2 is provided, and on the other surface of the n drain layer 1, a drain electrode 9 is provided. An insulating film 6 covers the gate electrode layer 5. The n drain layer 1 may be two layers having different impurity concentrations.
[0003]
By applying an appropriate voltage to a gate electrode (not shown) provided in contact with the gate electrode layer 5, an inversion layer (channel) is generated in the surface layer of the p channel region 2 along the inner wall of the trench 8, and the drain electrode 9 and the source electrode 7 are conducted, and a current flows.
[0004]
[Problems to be solved by the invention]
In FIG. 6, in order to manufacture a MOS semiconductor device having a trench structure, a trench 8 that penetrates the n source region 3 and the p channel region 2 and reaches the n drain layer 1 is dug, and a gate oxide film is formed in the trench 8. The gate electrode layer 5 must be filled via 4. If the depth of the trench 8 is shallower than that of the p-channel region 2, a portion where the inversion layer is not formed is formed in the p-channel region 2, and a current path is not formed, so that the operation is not performed. Therefore, it is important to set the relationship between the depth of the trench 8 and the depth of the p-channel region 2 in accordance with desired characteristics.
[0005]
FIG. 7 is a characteristic diagram showing the dependency of the difference x between the depth of the trench 8 and the depth of the p-channel region 2 in breakdown voltage. The horizontal axis represents the difference x between the depth of the trench 8 and the depth of the p-channel region 2, and the vertical axis represents the breakdown voltage. It can be seen that when the difference x is increased, the breakdown voltage is lowered. In order to achieve a high breakdown voltage, the difference x must be kept small.
On the other hand, when this difference x is reduced, there is a problem that the on-resistance increases. This is presumably because if the difference x is small, a sufficient inversion layer is not formed at the bottom of the trench 10 when a voltage is applied to the gate electrode, and the channel resistance increases.
[0006]
Therefore, in order to obtain a MOSFET having a high withstand voltage and a low on-resistance, the difference x between the trench depth and the channel region must be controlled within a very narrow range, which is difficult to manufacture. If the difference x varies, the withstand voltage and the on-resistance vary. Actually, the ON resistance variation may be 20 to 30% in the same lot. This problem is not limited to trench MOSFETs but is common to trench semiconductor devices having MOS structure gates.
[0007]
In view of the above problems, an object of the present invention is to provide a method for manufacturing a trench type MOS semiconductor device having a trench structure that has a high breakdown voltage, a low on-resistance, and is easy to manufacture.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention sets the protrusion of the trench to the first conductivity type drain layer to be 0.1 to 0.5 μm, and a first conductivity type well region having a higher concentration than the first conductivity type drain layer at the bottom of the trench. In this case, even if the withstand voltage is high and the difference x between the trench depth and the channel region depth is small, the low-resistance first conductivity type well region functions as an inversion layer, so that an increase in on-resistance can be suppressed. It will be. Further, the allowable range of the difference x between the trench depth and the channel region depth is widened.
As a method for manufacturing such a trench type MOS semiconductor device, a first conductivity type well region is formed at the bottom of the trench by ion implantation of a first conductivity type impurity and heat treatment. If ion implantation is performed at a shallow implantation angle, almost no ions are implanted into the side surface of the trench. Even if it is implanted into the side surface of the trench, the depth is shallow, so that it can be removed by a slight amount of etching of the surface layer. Since the bottom of the trench is implanted substantially vertically, it can be implanted deeply.
Then, the trench formation insulating film mask is etched backward after the trench formation, and the first conductivity type source region and the first conductivity type well region at the bottom of the trench are simultaneously formed by ion implantation of the first conductivity type impurity and heat treatment. It shall be. By doing so, since the first conductivity type source region and the first conductivity type well region can be formed at the same time, it is not necessary to perform the photolithography process separately, and the process can be shortened.
[0009]
[0010]
[0011]
[0012]
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below based on examples with reference to the drawings. In addition, the area | region and layer which crowned n and p shall mean the area | region and layer which respectively have an electron and a hole as a majority carrier, The example which made the 1st conductivity type n type and the 2nd conductivity type p type This can be reversed.
[0014]
[Example 1]
FIG. 1 is a partial cross-sectional view of the upper layer portion of the main part of the MOSFET according to the first embodiment of the present invention. In addition to the main portion shown in the figure, there is a portion that mainly shares the breakdown voltage in the peripheral region, but it is omitted because it is not a portion related to the essence of the present invention.
A p channel region 2 is formed in the surface layer of the n drain layer 1 which is a growth layer of the epitaxial wafer, and an n source region 3 is formed in the surface layer of the p channel region 2. A trench 8 is formed from the surface of n source region 3 through p channel region 2 to reach n drain layer 1. Inside trench 8, a gate electrode layer made of polycrystalline silicon with gate oxide film 4 interposed therebetween 5 is filled. On the surface of the n source region 3, a source electrode 7 that is in contact with the surface of the p channel region 2 is provided. In this example, the source electrode 7 is extended on the insulating film 6, but this is not always necessary. The MOSFET of the first embodiment is different from the conventional trench MOSFET in that an n + well region 10 having an impurity concentration higher than that of the n drain layer 1 is provided on the bottom surface portion of the trench 8. On the back surface of the n drain layer 1, there is a low-resistance substrate (not shown) and a drain electrode provided on the back surface. Also, a metal gate electrode that contacts the gate electrode layer 5 is not shown.
[0015]
3A to 3E are cross-sectional views for each main manufacturing process showing the method for manufacturing the MOSFET of FIG. Boron ions and then arsenic ions are implanted into the surface layer of the n drain layer 1 which is a growth layer of the epitaxial wafer, and the p channel region 2 and the n source region 3 are formed by heat treatment, and an oxide film is formed on the surface for trench formation. 11 is formed and patterned by photolithography [FIG. 3A]. For example, the substrate of the epitaxial wafer is 4 mΩ · cm and the thickness is 350 μm, and the n drain layer is 0.55 Ω · cm and the thickness is 10 μm. The depths of the p channel region 2 and the n source region 3 are 2.5 μm and 0.6 μm, respectively.
[0016]
Using the pattern of oxide film 11 as a mask, trench 8 is formed by dry etching using HBr gas [FIG. At this time, the depth of the trench 8 is made slightly deeper than the diffusion depth of the p channel region 2. The dimensions of the trench are, for example, a width of 1 μm, a depth of 2.7 μm, and an interval of 3.5 μm. That is, the difference x between the depth of the trench 8 and the diffusion depth of the p-channel region 2 is about 0.2 μm.
[0017]
The oxide film 11 for forming the trench is used as it is, and phosphorus ions 12 are implanted [FIG. The ion implantation conditions are an acceleration voltage of 150 kV, a dose of 1 × 10 13 / cm 2 , and an implantation angle of 0 °. If ion implantation is performed at a shallow implantation angle, almost no ions are implanted into the side surface of the trench. Even if it is implanted into the side surface of the trench, the depth is so shallow that it can be removed by a slight amount of etching of the surface layer. Since the bottom of the trench is implanted substantially vertically, it can be implanted deeply. Reference numeral 13 denotes an ion implantation region.
[0018]
After removing the oxide film 11, a gate oxide film 4 having a thickness of 100 nm is formed on the inner surface of the trench by thermal oxidation. (1050 ° C., 60 minutes) By this heat treatment, phosphorus ions implanted into the bottom of the trench 8 are activated, and an n + well region 10 having a diffusion depth of 0.5 μm is formed [(d)].
Polycrystalline silicon to be the gate electrode layer 5 is buried in the trench 8 by low-pressure CVD, and excess polycrystalline silicon is etched, and then an insulating film 6 of borosilicate glass (BPSG) is deposited by CVD, and photolithography is performed. Then, patterning is performed, and an aluminum alloy layer to be the source electrode 7 is deposited by sputtering, followed by patterning [FIG. Although not shown, a metal layer of Ti, Ni, and Au is deposited on the back side of the n drain layer 1 to form a drain electrode.
[0019]
Thus, by providing the n + well region 10 having a resistivity lower than that of the n drain layer 1 at the bottom of the trench 8, the variation in on-resistance within the wafer is greatly improved, and the characteristics are stable within 5%. did. In addition, since the problem of increasing the on-resistance is solved, the trench depth may be controlled between 0.1 and 0.5 μm, which is shallower, and the breakdown voltage can be increased. And the tolerance | permissible_range of trench depth became wide and manufacture became easy.
[0020]
[Example 2]
4A to 4E are cross-sectional views for each main manufacturing process showing another method for manufacturing the MOSFET of FIG. A p-channel region 2 is formed on the surface layer of the n-drain layer 1 which is a semiconductor substrate by implantation of boron ions and heat treatment, and an oxide film 11 is formed on the surface for trench formation, and is patterned by photolithography [FIG. 4 (a)].
[0021]
Using the pattern of the oxide film 11 as a mask, a trench 8 is formed by dry etching [FIG.
The pattern of the oxide film 11 used as a trench formation mask is wet etched to expose the surface of the p-channel region 2 near the opening of the trench 8, and then arsenic ions are implanted [(c) in FIG. Reference numeral 13 denotes an arsenic ion implantation region. Ions are implanted not only in the bottom of the trench 8 but also in the vicinity of the opening, and become ion implantation for forming the source region 3. Therefore, the dose amount of this ion implantation is larger than that of the first embodiment and is preferably about 5 × 10 13 / cm 2 .
[0022]
After removing the oxide film 11, a gate oxide film 4 is formed inside the trench by thermal oxidation. At this time, the heat treatment activates the arsenic ions implanted in the surface layer of the p-channel region 2 and the bottom of the trench 8 to form the n source region 3 and the n + well region 10 (FIG. 4D).
Thereafter, in the same manner as in Example 1, polycrystalline silicon to be the gate electrode layer 5 is buried in the trench 8 and excess polycrystalline silicon is etched. Then, an insulating film 6 is deposited by CVD, and by photolithography, Patterning is performed, and an aluminum alloy layer to be the source electrode 7 is deposited by sputtering, followed by patterning [FIG.
[0023]
By adopting such a method, it is not necessary to perform ion implantation for forming the n + well region 10, and the process can be shortened compared with the manufacturing method of the first embodiment.
[ Reference example ]
FIG. 2 is a cell cross-sectional view of a MOSFET according to a reference example of the present invention.
In this example, the trench 8 is formed from the surface of the n source region 3 and the n + well region 10 is formed at the bottom of the trench 8 as in the first embodiment shown in FIG. 1 is different in that the depth of is shallower than the diffusion depth of the p-channel region 2. However, the n + well region 10 formed at the bottom of the trench 8 reaches the n drain layer 1.
[0024]
FIGS. 5A to 5E are cross-sectional views for each main manufacturing process showing a method for manufacturing the MOSFET of FIG. Boron ions and then arsenic ions are implanted in the surface layer of n drain layer 1 which is a semiconductor substrate, p channel region 2 and n source region 3 are formed by heat treatment, and oxide film 11 is formed on the surface for trench formation. Then, patterning is performed by photolithography [FIG. 5A].
[0025]
Using the pattern of the oxide film 11 as a mask, a trench 8 is formed by dry etching [FIG. At this time, the depth of the trench 8 is slightly shallower than the diffusion depth of the p-channel region 2.
Using the oxide film 11 for forming the trench as a mask as it is, phosphorus ions are implanted [FIG. At this time, the injection angle is 0 °. Reference numeral 13 denotes an ion implantation region.
[0026]
After removing the oxide film 11, a gate oxide film 4 is formed inside the trench by thermal oxidation. At this time, phosphorus ions implanted into the bottom of the trench 8 are activated by the heat treatment, and an n + well region 10 in contact with the n drain layer 1 is formed [(d)].
Polycrystalline silicon to be the gate electrode layer 5 is buried in the trench 8 by low-pressure CVD, and after the excess polycrystalline silicon is etched, an insulating film 6 is deposited by CVD, patterned by photolithography, and further sourced by sputtering. An aluminum alloy layer to be the electrode 7 is deposited and patterned [FIG.
[0027]
In this case, the MOS semiconductor device does not operate conventionally because the inversion layer is not formed. However, by providing the n + well region 10 having a lower resistivity than the n drain layer 1 at the bottom of the trench 8 as in this reference example, Even when the depth of the trench 8 is shallower than the diffusion depth of the p-channel region, the inversion layer is connected from the n source region 3 to the n drain layer 1 and can operate.
[0028]
By doing so, the variation in on-resistance in the wafer was greatly improved, and the allowable range of the trench depth was widened, thereby facilitating manufacture.
[0029]
【The invention's effect】
As described above, according to the present invention, in the trench type MOS semiconductor device in which the gate electrode layer is provided in the trench via the gate insulating film, the high-concentration first conductivity type well region is provided at the bottom of the trench. As a result, the on-resistance is stabilized, and even if the difference x between the trench depth and the depth of the second conductivity type channel region is as small as 0.1 to 0.5 μm, there is no increase in the on-resistance as in the conventional case, so the withstand voltage can be kept high. It becomes like this. In addition, the allowable range of the difference x is widened, and manufacturing is facilitated.
[0030]
Then, as a method of manufacturing a trench type MOS semiconductor device as in the present invention, after forming a trench, the insulating film pattern used for the formation is etched back, ion implantation of a first conductivity type impurity and heat treatment are performed, and the source region and the first It was shown that the process can be shortened by simultaneously forming one conductivity type well region.
[Brief description of the drawings]
Figure 1 is a partial cross-sectional view of MOSFET according to the invention Example partial cross-sectional view of one of the MOSFET 2 shows the present invention in Reference Example 3] (a) ~ (e) are of the MOSFET embodiment 1 of FIG. 1 Cross-sectional views in the order of the manufacturing steps [FIG. 4] (a) to (e) are cross-sectional views in the order of the manufacturing steps of the manufacturing method of Example 2 different from the manufacturing method in FIG. 3 [FIG. 5] (a) to (e) cross-sectional views of the fabrication process sequence of the MOSFET reference example of FIG. 2 and FIG. 6 is a partial cross-sectional view of a conventional MOSFET 7 characteristic diagram showing a change in breakdown voltage due to the difference x between the diffusion depth of the trench depth and the p-channel region [Explanation of symbols]
1 n drain layer 2 p channel region 3 n source region 4 gate oxide film 5 gate electrode layer 6 insulating film (BPSG)
7 Source electrode 8 Trench 9 Drain electrode 10 n + well region 11 Oxide film 12 Phosphorus ion 13 Ion implantation region

Claims (2)

第一導電型ドレイン層と、その第一導電型ドレイン層上に設けられた第二導電型チャネル領域と、第二導電型チャネル領域の表面層に形成された第一導電型ソース領域と、その第一導電型ソース領域の表面から第二導電型チャネル領域を貫通し第一導電型ドレイン層に達するトレンチと、トレンチ内にゲート絶縁膜を介して設けられたゲート電極層と、第一導電型ソース領域と第二導電型チャネル領域との表面に共通に接触して設けられたソース電極と、第一導電型ドレイン層に接触して設けられたドレイン電極とからなるトレンチ型ＭＯＳ半導体装置において、前記トレンチの第一導電型ドレイン層への突出が0.1〜0.5μｍであり、該トレンチの底部に第一導電型ドレイン層より高濃度の第一導電型ウェル領域を有することを特徴とするトレンチ型ＭＯＳ半導体装置。A first conductivity type drain layer; a second conductivity type channel region provided on the first conductivity type drain layer; a first conductivity type source region formed on a surface layer of the second conductivity type channel region; A trench extending from the surface of the first conductivity type source region to the first conductivity type drain layer through the second conductivity type channel region, a gate electrode layer provided in the trench via a gate insulating film, and a first conductivity type In a trench type MOS semiconductor device comprising a source electrode provided in common contact with the surfaces of a source region and a second conductivity type channel region, and a drain electrode provided in contact with a first conductivity type drain layer, The trench has a protrusion of 0.1 to 0.5 μm to the first conductivity type drain layer, and has a first conductivity type well region having a higher concentration than the first conductivity type drain layer at the bottom of the trench. Chi-type MOS semiconductor device. 第一導電型ドレイン層と、その第一導電型ドレイン層上に設けられた第二導電型チャネル領域と、第二導電型チャネル領域の表面層に形成された第一導電型ソース領域と、その第一導電型ソース領域の表面から第二導電型チャネル領域を貫通し第一導電型ドレイン層に0.1 〜 0.5 μｍ突出するトレンチと、トレンチ内にゲート絶縁膜を介して設けられたゲート電極層と、第一導電型ソース領域と第二導電型チャネル領域との表面に共通に接触して設けられたソース電極と、第一導電型ドレイン層に接触して設けられたドレイン電極とからなるトレンチ型ＭＯＳ半導体装置の製造方法において、トレンチ形成用の絶縁膜マスクを、トレンチ形成後に後退エッチングさせた後、第一導電型不純物のイオン注入および熱処理により、第一導電型ソース領域とトレンチの底部の第一導電型ウェル領域とを同時に形成することを特徴とするトレンチ型ＭＯＳ半導体装置の製造方法。A first conductivity type drain layer; a second conductivity type channel region provided on the first conductivity type drain layer; a first conductivity type source region formed on a surface layer of the second conductivity type channel region; A trench penetrating the second conductivity type channel region from the surface of the first conductivity type source region and protruding to the first conductivity type drain layer by 0.1 to 0.5 μm; and a gate electrode layer provided in the trench via a gate insulating film; A trench type comprising a source electrode provided in common contact with the surfaces of the first conductivity type source region and the second conductivity type channel region, and a drain electrode provided in contact with the first conductivity type drain layer In a method of manufacturing a MOS semiconductor device, a first conductive type source is formed by performing ion etching of a first conductive type impurity and heat treatment after an insulating film mask for forming a trench is subjected to receding etching after forming the trench. Method of manufacturing a trench type MOS semiconductor device, and forming a band and a first conductivity type well region of the bottom of the trench at the same time.
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