CN108766965B - Groove type double MOS tube device shared by drain electrodes and manufacturing method - Google Patents
Groove type double MOS tube device shared by drain electrodes and manufacturing method Download PDFInfo
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- CN108766965B CN108766965B CN201810877372.0A CN201810877372A CN108766965B CN 108766965 B CN108766965 B CN 108766965B CN 201810877372 A CN201810877372 A CN 201810877372A CN 108766965 B CN108766965 B CN 108766965B
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A trench type double MOS tube device shared by drain electrodes and a manufacturing method belong to the technical field of semiconductors. Comprising a substrate (19), a drift region (18) and a trench (13), characterized in that: the polysilicon in the middle of the groove (13) is divided into a first polysilicon (12) and a second polysilicon (14), a bottom layer contact hole (6) is formed in the MOS structure between the two grooves (13), and a connecting layer is arranged on the surface of the MOS structure. The method also comprises the following steps: step 1, first oxidation and photoetching; step 2, first oxide deposition; step 3, second oxidation; step 4, performing second photoetching; step 5, depositing oxide for the second time; step 6, forming a MOS structure above the drift region (18); and 7, forming a connecting layer. In the trench type double-MOS transistor device shared by the drain electrodes and the manufacturing method, current flows through the conductive channel formed around the trench between the two MOS structures, and the on-resistance is reduced.
Description
Technical Field
A trench type double MOS tube device shared by drain electrodes and a manufacturing method belong to the technical field of semiconductors.
Background
The lithium ion battery has excellent performance, the lithium cobaltate battery becomes the first choice of consumer electronic equipment, but the material of the lithium battery itself determines that the lithium battery cannot be overcharged, overdischarged, overcurrent, short-circuited and ultra-high-temperature charge and discharge, so that a protection circuit is required to be arranged for being matched with the lithium battery, the voltage of a battery cell and the current of the charge and discharge circuit can be accurately monitored at the moment of the lithium battery through the protection circuit, the on-off of the current circuit can be timely controlled, and the battery can be prevented from being damaged badly under a high-temperature environment.
The basic protection circuit diagram of the lithium battery is shown in fig. 24, in the diagram, a driving chip U1 (MOS driving chip) is used for controlling the on and off of MOS tubes M1-M2, a cell B1 is conducted with an external circuit through the driving chip U1, the voltage and the current of the cell B1 are monitored, and when the voltage and the current in a loop exceed specified values, the MOS tubes M1-M2 are turned off, so that the safety of the cell is protected. The MOS transistor M1 includes a MOS structure Q1 and a parasitic diode D1 between the base region and the drain electrode in the MOS structure Q1, and the MOS transistor M2 includes a MOS structure Q2 and a parasitic diode D2 between the base region and the drain electrode in the MOS structure Q2.
The specific working process and working principle of the protection circuit are as follows: in a charging state, an external charging circuit is connected through ports P1-P2, at the moment, the driving chip U1 controls the two MOS tubes to be conducted to form a current loop to charge the battery core, when the voltage of the battery rises above an overcharge voltage, the driving chip U1 controls the MOS structure Q2 to be turned off, at the moment, the parasitic diode D2 is reversely cut off, and the charging current loop is blocked to realize the overcharge protection of the battery. When the voltage of the battery core B1 is reduced below the overdischarge voltage, the driving chip U1 controls the MOS structure Q1 to be turned off, the parasitic diode D1 is reversely cut off, a discharging loop is blocked, and the overdischarge protection of the battery is realized.
According to the above, when the traditional protection circuit works, in the existing protection circuit, the two MOS tubes are connected with the drain electrodes of the two MOS tubes through external connection and welding processes, so that the switch control function of the protection circuit is realized. Taking a charging state as an example, current flows into the battery cell B1 from the port P1, flows in from the source electrode in the MOS tube M1, flows out from the drain electrode of the MOS tube M1 through the MOS structure Q1, the drift region and the substrate in the MOS tube M1, then flows into the drain electrode of the MOS tube M2, and flows out from the source electrode of the MOS tube M2 through the substrate, the drift region and the MOS structure Q2 of the MOS tube M2, so that a charging current loop is formed, the discharging process is basically the same, and therefore, the current can be conducted through the internal and external connecting lines of the two MOS tubes, and therefore, the current path is overlong, the on resistance is overlarge, and the reliability of equipment is greatly affected.
An important practical index of the protection circuit is on-resistance, and because the working frequency of the communication equipment is high, the data transmission requirement bit error rate is low, and the rising and falling edges of the pulse train are steep, the current output capability and the voltage stability requirement of the battery core B1 are high, so that the resistance of the MOS tube in the protection circuit is small when the switch is conducted, and the phenomenon that the communication equipment works abnormally, such as abrupt disconnection, telephone connection failure, noise and the like, is caused when the mobile phone is in communication.
Disclosure of Invention
The invention aims to solve the technical problems that: the trench type double MOS tube device and the manufacturing method thereof, which are used for integrating and sharing the drain electrodes of the two MOS tubes, realize current circulation through the conducting channel formed by the cross structure design of the source electrodes and the grid electrodes of the two MOS tubes, replace a circuit structure which is connected with the two MOS tubes in series, greatly reduce the on-resistance, reduce the power consumption and improve the efficiency and the reliability of equipment.
The technical scheme adopted for solving the technical problems is as follows: the trench type double MOS tube device shared by the drain electrodes comprises a substrate and a drift region above the substrate, wherein a plurality of trenches are formed in the surface of the drift region, a trench sidewall insulating layer and a trench bottom insulating layer are respectively arranged on the sidewall and the bottom of each trench, and polysilicon is filled in each trench, and the trench type double MOS tube device is characterized in that: the middle part in the groove is also vertically provided with a groove middle insulating layer, the polysilicon comprises a first polysilicon and a second polysilicon which are respectively positioned at two sides of the groove middle insulating layer, and two grid electrodes of the double MOS tube are respectively led out from the first polysilicon and the second polysilicon;
and a source region and a base region are sequentially formed between two adjacent grooves from top to bottom, a bottom layer contact hole is further formed between the two grooves, the bottom layer contact hole is filled with conductive materials and penetrates through the source region from top to bottom to enter the base region to form a MOS structure, a connecting layer is arranged on the surface of the MOS structure, and the connecting layer is connected with the MOS structure to respectively lead out two sources of the double MOS tube.
Preferably, in the two adjacent trenches, the first polysilicon and the second polysilicon are disposed at opposite positions.
Preferably, in the two adjacent trenches, the first polysilicon or the second polysilicon which are oppositely arranged are connected.
Preferably, the connecting layer comprises a bottom insulating layer positioned on the surface of the MOS structure and a bottom metal layer positioned on the surface of the bottom insulating layer, the bottom contact holes penetrate through the bottom insulating layer at the same time, the bottom metal layer is connected into the corresponding MOS structure through the bottom contact holes, and the sources of the double MOS tubes are respectively led out.
Preferably, the bottom metal layer comprises a plurality of sections of first bottom metal and a plurality of sections of second bottom metal which are in one-to-one correspondence with the bottom contact holes, the first bottom metal and the second bottom metal are arranged at intervals, and the two sources of the double MOS tube are respectively led out from the plurality of sections of first bottom metal and the plurality of sections of second bottom metal.
Preferably, the connecting layer further comprises a top metal layer, a top insulating layer is filled between the first bottom metal and the second bottom metal and on the upper portion of the connecting layer, the top metal layer is located on the surface of the top insulating layer, the top metal layer comprises a first top metal and a second top metal, and the first top metal and the second top metal are respectively connected with the first bottom metal and the second bottom metal through top contact holes penetrating through the top insulating layer.
A manufacturing method for manufacturing a trench type double MOS tube device shared by drain electrodes is characterized by comprising the following steps: the method comprises the following steps:
and 7, forming a connection layer through a connection layer manufacturing process.
Preferably, the manufacturing process of the connecting layer comprises the following steps:
step 7-1, performing first insulation deposition and third photoetching, depositing a bottom insulation layer on the surfaces of the groove, the base region and the source region, and performing third photoetching downwards from the surface of the bottom insulation layer to form a bottom contact hole;
step 7-2, performing first metal deposition and fourth photoetching, filling conductive materials in the bottom insulating layer, performing metal deposition on the surface of the bottom insulating layer, and performing fourth photoetching to form a first bottom metal and a second bottom metal which are arranged at intervals;
step 7-3, second insulating deposition and fifth photoetching, wherein a top insulating layer is formed between and above the first bottom metal and the second bottom metal, and fifth photoetching is carried out to form top contact holes respectively contacted with the first bottom metal and the second bottom metal;
and 7-4, performing second metal deposition and sixth photoetching, filling conductive materials in the top layer contact holes, performing second metal deposition to form a top layer metal layer, and performing sixth photoetching on the top layer metal layer to respectively form a first top layer metal and a second top layer metal.
Compared with the prior art, the invention has the following beneficial effects:
1. in the trench type double-MOS tube device shared by the drain electrode, an integrated drain electrode sharing design is adopted, and two MOS tube series circuits are integrated on one chip through source electrode and grid electrode crossing structure designs of the two MOS structures, so that when the trench type double-MOS tube device shared by the drain electrode is conducted, a conductive channel is formed around a trench between two adjacent MOS structures, current horizontally flows through a drift region, and no welding copper plate or connecting wire passing through a substrate, back metal and the outside is needed, thereby greatly reducing on resistance, reducing power consumption and improving efficiency and reliability of equipment.
2. The integrated drain electrode groove type double MOS tube device has the advantages that when in conduction, current horizontally flows through the drift region and does not pass through the substrate and the back metal, so that the substrate thinning and the back metal process in the traditional MOS tube are canceled, the flow sheet production process is simplified, and the production cost is saved.
3. The trench type double MOS tube device shared by the drain electrode has the same serial connection function as two MOS tubes in the existing power protection plate circuit, so that the region distribution of the device is greatly facilitated, the cost of the product is reduced, and the connection with the driving chip is the same as the conventional connection mode in actual use, so that the universality is better.
Drawings
Fig. 1 is a cross-sectional view of a trench type dual MOS transistor device shared by the drain of embodiment 1.
Fig. 2 is a perspective view (without metal layer) of a trench type dual MOS transistor device shared by the drains of example 1.
Fig. 3 is a front metal view of a trench dual MOS transistor device shared by the drains of example 1.
Fig. 4 to 12 are flowcharts of a method for manufacturing a trench type dual MOS transistor device shared by the drain electrode of embodiment 1.
Fig. 13 to 16 are flowcharts of a method for manufacturing a trench type dual MOS transistor device shared by the drains in embodiment 2.
Fig. 17 to 20 are flowcharts of a method for manufacturing a trench type dual MOS transistor device shared by the drains in embodiment 3.
Fig. 21 is a cross-sectional view of a trench type dual MOS transistor device shared by the drains of embodiment 4.
Fig. 22 is a perspective view (without metal layer) of a trench type dual MOS transistor device shared by the drains of example 4.
Fig. 23 is a front metal view of a trench dual MOS transistor device for drain sharing in embodiment 5.
Fig. 24 is a schematic diagram of a prior art lithium battery protection circuit.
Wherein: 1. the first top metal layer 2, the top contact hole 3, the top insulating layer 4, the bottom insulating layer 5, the first bottom metal layer 6, the bottom contact hole 7, the second bottom metal layer 8, the insulating trench 9, the second top metal layer 10, the trench middle insulating layer 11, the trench bottom insulating layer 12, the first polysilicon 13, the trench 14, the second polysilicon 15, the trench sidewall insulating layer 16, the source region 17, the base region 18, the drift region 19, the substrate 20, the circuit board backboard 21, the first gate 22, the second gate 23, the first oxide layer 24, the trench oxide layer 25, the oxide column 26, and the source metal layer.
Detailed Description
Fig. 1 to 12 are preferred embodiments of the present invention, and the present invention is further described with reference to fig. 1 to 23.
Example 1:
a trench type double MOS tube device (MOS device for short) shared by drain electrodes comprises a trench type double MOS tube structure shared by drain electrodes and a connecting layer connected with the trench type double MOS tube structure, wherein a source electrode and a grid electrode of the double MOS tube device are led out through the connecting layer, so that a lead wire can be conveniently realized in a circuit in the later stage.
As shown in fig. 2, the MOS transistor device includes a substrate 19 made of an n+ type semiconductor material, a drift region 18 made of an N type semiconductor material above the substrate 19, a plurality of trenches 13 formed on an upper surface of the drift region 18 side by side, a trench sidewall insulating layer 15 formed on a sidewall of the trench 13, and a trench bottom insulating layer 11 formed at a bottom of the trench 13, wherein a thickness of the trench bottom insulating layer 11 is set according to a withstand voltage degree of the MOS chip. The middle part of the trench 13 is further provided with a trench middle insulating layer 10, the trench side wall insulating layer 15 and the trench bottom insulating layer 11 are combined into a whole and vertically spaced in each trench 13 to form two independent filling areas, the two independent filling areas of each trench 13 are respectively filled with first polysilicon 12 and second polysilicon 14, and the arrangement positions of the first polysilicon 12 and the second polysilicon 14 in the two adjacent trenches 13 are opposite. The first polysilicon 12 and the second polysilicon 14 are led out and then serve as two gates of the MOS device, respectively.
A source region 16 of n+ type semiconductor material and a base region 17 of P type semiconductor material are sequentially arranged between two adjacent trenches 13 from the upper surface of the drift region 18 downwards, and bottom contact holes 6 are respectively arranged between the two adjacent trenches 13. The bottom layer contact hole 6 is located in the middle of two adjacent trenches 13, and the bottom layer contact hole 6 penetrates through the source region 16 from the upper surface of the drift region 18 downwards to the base region 17.
Referring to fig. 1 again, the connection layer matched with the MOS die includes a first top metal 1, a second top metal 9, a top insulating layer 3, a bottom insulating layer 4, a first bottom metal 5, and a second bottom metal 7, where the bottom insulating layer 4 is disposed above the drift region 18, and the bottom contact hole 6 passes through the bottom insulating layer 4 upwards at the same time. The upper surface of the bottom insulating layer 4 is provided with a first bottom metal 5 and a second bottom metal 7 at intervals, and the bottom contact hole 6 is filled with a conductive material and is correspondingly connected with the first bottom metal 5 and the second bottom metal 7 respectively.
The MOS device comprises a first bottom layer metal 5, a second bottom layer metal 7, a top layer insulating layer 3, a top layer metal layer, an insulating groove 8, a first top layer metal 1 and a second top layer metal 9, wherein the top layer insulating layer 3 is filled between the first bottom layer metal 5 and the second bottom layer metal 7 and above the first bottom layer metal 5 and the second bottom layer metal 7, the top layer metal layer is further covered on the surface of the top layer insulating layer 3, the insulating groove 8 is formed in the middle of the top layer metal layer, the top layer metal layer is divided into the first top layer metal 1 and the second top layer metal 9 through the insulating groove 8, and the first top layer metal 1 and the second top layer metal 9 correspond to two sources of the MOS device respectively. A plurality of top layer contact holes 2 are further formed in the top layer insulating layer 3, conductive materials are filled in the top layer contact holes 2, and all first bottom layer metals 5 and second top layer metals 9 and all second bottom layer metals 7 and first top layer metals 1 are connected through the top layer contact holes 2.
The specific working process and working principle are as follows: in a charging or discharging state, driving voltage is applied to two gates of the MOS device through the driving chip U1, so that corresponding conductive channels are formed in the MOS device, external charging current enters from the first top metal 1, then enters into MOS structures of the corresponding MOS device through the top contact hole 2 and the second bottom metal 7, enters into another MOS structure through the conductive channels around the grooves 13 between the two adjacent MOS structures, and finally sequentially passes through the base region 17 and passes through the second bottom metal 7 again and then flows out from the second top metal 9 to form a current loop.
When the charging loop or the discharging loop needs to be cut off, one of the MOS structures is closed through the driving chip, the conducting channel around the groove disappears, and the PN junction (parasitic diode) formed by the base region 17 and the source region 16 in the MOS device is reversely cut off, so that the effect of blocking current is achieved.
As can be seen from the above, when the MOS device is turned on, a conductive channel is formed around the trench between two adjacent MOS structures, and current flows horizontally through the drift layer, so that no substrate, back metal, and external solder copper plate or wire are required, thereby greatly reducing on-resistance, reducing power consumption, and improving efficiency and reliability of the device.
In the MOS device, the serial connection function of the MOS device and the two MOS tubes in the existing power protection plate circuit is consistent, so that the area distribution of the device is greatly facilitated, the cost of a product is reduced, and the connection with a driving chip in actual use is the same as the conventional connection mode, so that the universality is better. As shown in fig. 3, in the front metal diagram of the present MOS device, the first top metal 1 and the second top metal 9 are respectively led out as two sources of the MOS device, and the first gate 21 and the second gate 22 are respectively led out as two gates of the MOS device, where the first gate 21 and the second gate 22 are respectively connected to the first polysilicon 12 and the second polysilicon 14.
Meanwhile, as can be seen from fig. 2, in the present MOS die, since the first polysilicon 12 and the second polysilicon 14 are disposed in opposite positions in the adjacent two trenches 13. Therefore, the connection between the first polysilicon 12 (the second polysilicon 14) in the two adjacent trenches 13 can be realized through the narrow trenches filled with polysilicon (the first polysilicon 12 or the second polysilicon 14), so that the conducting area of the gate is increased, and the current density of the gate of the MOS transistor is increased.
As shown in fig. 4 to 12, the method for manufacturing the trench type double MOS transistor device shared by the drain electrodes shown in fig. 1 includes the following steps:
in step a1, a drift region 18 is formed over a substrate 19, and then a first oxidation treatment is performed on the surface of the drift region 18 to form a first oxide layer 23, and then a first photolithography is performed to form a trench 13, as shown in fig. 4.
In step a2, a first oxide deposition is performed on the upper surface of the drift region 18, and a trench bottom insulating layer 11 is formed at the bottom of the trench 13, and the thickness of the trench bottom insulating layer 11 is set according to the withstand voltage required for the chip and the doping concentration of the drift region 18, as shown in fig. 5.
In step a3, a second oxidation treatment is performed on the drift region 18 to form a trench sidewall insulating layer 15, as shown in fig. 6.
In step a4, polysilicon is filled in the trench 13, and a second photolithography is performed, and a groove is formed in the middle of the trench 13 to divide the filled polysilicon into a left portion and a right portion, so as to form a first polysilicon 12 and a second polysilicon 14, respectively, as shown in fig. 7.
In step a5, oxide filling is performed in the grooves in the trenches 13 for the second time to form the insulating layer 10 in the middle of the trenches, and then the first oxide layer 23 on the surface of the drift region 18 is removed to expose the surface of the drift region 18, as shown in fig. 8.
In step a6, a base region 17 and a source region 16 are conventionally formed over the drift region 18, forming a MOS structure, as shown in fig. 9.
In step a7, a bottom insulating layer 4 is deposited on the surface of the chip, and then a third photolithography is performed downwards from the surface of the bottom insulating layer 4 to form a bottom contact hole 6, wherein the bottom contact hole 6 is opened between two adjacent grooves 13 and passes through the bottom insulating layer 4, the source region 16 and the base region 17 downwards in sequence, as shown in fig. 10.
In step a8, the bottom insulating layer 4 is filled by a tungsten plug process, then metal deposition is performed on the surface of the bottom insulating layer 4, and fourth photolithography is performed to form a first bottom metal 5 and a second bottom metal 7 which are arranged at intervals, as shown in fig. 11.
In step a9, a top insulating layer 3 is deposited between and above the first bottom metal 5 and the second bottom metal 7, and a fifth photolithography is performed to form top contact holes 2 respectively contacting the first bottom metal 5 and the second bottom metal 7, as shown in fig. 12.
And a step a10, filling the top layer contact hole 2 by using a tungsten plug process, then carrying out second metal deposition, then carrying out sixth photoetching to form an insulation groove 8, and respectively forming a first top layer metal 1 and a second top layer metal 9 at two sides of the insulation groove 8 to form the trench type double MOS tube device shared by the drain electrodes as shown in fig. 1.
Example 2:
example 2 differs from example 1 in that: the manufacturing steps are different, and the specific steps are as follows:
step b1, step b1 is identical to step a 1.
In step b2, oxide filling is performed on the surface of the drift region 18, and a first oxide layer 23 is formed on the surface of the drift region 18, and a trench oxide layer 24 is formed in the trench 13, as shown in fig. 13.
In step b3, a second photolithography is performed in the trench 13, and after the photolithography is completed, a trench bottom insulating layer 11 and a trench middle insulating layer 10 are formed in the trench 13 at the bottom of the trench 13, respectively, as shown in fig. 14.
In step b4, a second oxidation treatment is performed on the trench 13 sidewall to form a trench sidewall insulating layer 15, as shown in fig. 15.
In step b5, polysilicon filling is performed in the trench 13 to form the first polysilicon 12 and the second polysilicon 14, respectively, and then the first oxide layer 23 is removed, as shown in fig. 16.
Step b6 to step b10 are the same as step a6 and step a10 in embodiment 1, and are not described here again.
Example 3:
example 3 differs from example 2 in that: the manufacturing steps are different, and the specific steps are as follows:
in step c1, a drift region 18 is formed over the substrate 19, and then a first oxidation treatment is performed on the surface of the drift region 18 to form a first oxide layer 23, and then a first photolithography is performed, as shown in fig. 17.
In step c2, a first photolithography is performed on the first oxide layer 23 to form a plurality of oxide pillars 25, as shown in fig. 18.
In step c3, the same material as the drift region 18 is filled between the oxide pillars 25 using an epitaxial process, as shown in fig. 19.
In step c4, a second photolithography is performed on the oxide pillars 25 to form the trench bottom insulating layer 11 and the trench middle insulating layer 10, and simultaneously form the trenches 13, as shown in fig. 20.
Step c5, performing a second oxidation treatment to form an oxide layer on the surface of the drift layer 18 and the sidewall of the trench 13, and then removing the surface oxide layer on the drift region 18, wherein the oxide layer remaining on the sidewall of the trench 13 is the trench sidewall insulating layer 15, as shown in fig. 15.
Step c6 to step c11 are the same as step b5 and step b10 in embodiment 2, and are not described here again.
Example 4:
example 4 differs from example 1 in that: and only one metal layer is arranged above the groove type double-MOS tube chip shared by the drain electrodes. As shown in fig. 20 to 21, a source metal layer 26 is disposed above the trench-type dual MOS transistor chip shared by the drains in this embodiment, and the source metal layer 26 replaces the first top metal 1 and the second top metal 9 in fig. 3 in embodiment 1 to lead out the sources of the two MOS transistors.
In this embodiment, the source metal layer 26 is also connected to the drain electrode through a trench-type dual MOS structure shared by the bottom contact hole 6 filled with a conductive material, and is different from embodiment 1 in that: the bottom layer contact holes 6 are not completely arranged between every two adjacent grooves 13 in a penetrating way, but are staggered on two sides of the groove type double-MOS structure shared by the drain electrodes, and the bottom layer contact holes 6 on the same side are led out from the source electrode metal layers 26 on the corresponding side to serve as source electrodes of the corresponding MOS structure.
In this embodiment, since the bottom contact holes 6 are formed on two sides of the trench dual MOS structure in a staggered manner, the bottom contact holes 6 on the same side are led out from the source metal layer 26 on the corresponding side to serve as the sources of the corresponding MOS structure, so when the two MOS structures are driven to be turned on by the driving chip, the current of the MOS structure without the contact holes cannot be led out through the metal layer, but can only flow through the source region 16 of the MOS structure, resulting in an increase in the on internal resistance of the MOS transistor device.
In this embodiment, the on-resistance is greater than that in embodiment 1, but the trench dual MOS transistor device shared by the drain electrode has a reduced number of metal layers and corresponding insulating layers, so the process is simpler.
Example 5:
this embodiment differs from embodiment 1 in that: in this embodiment, only one metal layer is disposed above the trench-type dual MOS transistor device shared by the drain electrode, instead of the first bottom metal layer 5 or the second bottom metal layer 7, the first top metal layer 1, the second top metal layer 9, and the top insulating layer 3 are omitted. The device conduction performance of this embodiment 1 is the same as that of embodiment 1, except that: because only one metal layer is arranged, partial areas are reserved on the surface of the groove type double-MOS tube device shared by the drain electrodes and are respectively used for leading out two source electrodes of the MOS tube device, as shown in fig. 22, so that the area of the groove type double-MOS tube device shared by the drain electrodes finally formed in the embodiment is larger than that of the scheme in the embodiment 1, but the process is simpler because the groove type double-MOS tube device shared by the drain electrodes is reduced by one metal layer and a corresponding insulating layer.
Example 6:
this embodiment differs from embodiment 1 in that: in this embodiment, the drift region 18 of the N-type semiconductor material in embodiment 1 is omitted, an N-type semiconductor with a very low doping concentration is selected as the substrate 19, then phosphorus ions (or other N-type ions) are implanted by ion implantation, the drift region 18 of the N-type semiconductor is formed by high-temperature diffusion, and the concentration and thickness of the drift region 18 are adjusted according to the required withstand voltage. In this embodiment, the drift region 18 is formed directly above the substrate 19 by doping, so that the flow sheet production process is simplified, the production cost is reduced, and the production period is shortened.
In the above embodiment, the P-type and N-type material layers are exchanged, and the same beneficial effects of the P-channel trench type double MOS transistor can be achieved based on the same structure manufacturing sequence.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way, and any person skilled in the art may make modifications or alterations to the disclosed technical content to the equivalent embodiments. However, any simple modification, equivalent variation and variation of the above embodiments according to the technical substance of the present invention still fall within the protection scope of the technical solution of the present invention.
Claims (4)
1. The utility model provides a two MOS pipe devices of slot type that drain electrode shared, includes drift region (18) of substrate (19) and substrate (19) top, has seted up a plurality of slots (13) at the surface of drift region (18), is provided with slot lateral wall insulating layer (15) and slot bottom insulating layer (11) respectively in the lateral wall and the bottom of slot (13), still fills polycrystalline silicon in slot (13), its characterized in that: a groove middle insulating layer (10) is further vertically arranged in the middle of the groove (13), the polysilicon comprises a first polysilicon (12) and a second polysilicon (14) which are respectively positioned at two sides of the groove middle insulating layer (10), and two grid electrodes of the double MOS tube are respectively led out from the first polysilicon (12) and the second polysilicon (14);
a source region (16) and a base region (17) are sequentially formed between two adjacent grooves (13) from top to bottom, a bottom layer contact hole (6) is further formed between the two grooves (13), the bottom layer contact hole (6) is filled with conductive materials and penetrates through the source region (16) from top to bottom and enters the base region (17) to form a MOS structure, a connecting layer is arranged on the surface of the MOS structure, and the connecting layer is connected with the MOS structure to respectively lead out two sources of the double MOS tube;
in the two adjacent grooves (13), the arrangement positions of the first polysilicon (12) and the second polysilicon (14) are opposite;
in two adjacent grooves (13), the first polysilicon (12) or the second polysilicon (14) which are oppositely arranged are connected;
the connecting layer comprises a bottom insulating layer (4) positioned on the surface of the MOS structure and a bottom metal layer positioned on the surface of the bottom insulating layer (4), wherein the bottom contact holes (6) penetrate through the bottom insulating layer (4) at the same time, the bottom metal layer is connected into the corresponding MOS structure through the bottom contact holes (6), and the sources of the double MOS tubes are respectively led out;
the bottom metal layer comprises a plurality of sections of first bottom metal (5) and a plurality of sections of second bottom metal (7) which are in one-to-one correspondence with the bottom contact holes (6), the first bottom metal (5) and the second bottom metal (7) are arranged at intervals, and the plurality of sections of first bottom metal (5) and the plurality of sections of second bottom metal (7) respectively lead out two source electrodes of the double MOS tube;
in a charging or discharging state, driving voltage is applied to two grid electrodes of the double MOS tube through the driving chip, so that corresponding conductive channels are formed in the double MOS tube, and the conductive channels in the double MOS tube and the conductive channels around the grooves (13) between the double MOS tubes are communicated with two source electrodes led out from the first bottom metal layer (5) and the second bottom metal layer (7) respectively.
2. The drain-shared trench dual MOS transistor device of claim 1, wherein: the connecting layer also comprises a top metal layer, a top insulating layer (3) is filled between the first bottom metal layer (5) and the second bottom metal layer (7) and on the upper portion of the connecting layer, the top metal layer is located on the surface of the top insulating layer (3), the top metal layer comprises a first top metal layer (1) and a second top metal layer (9), and the first top metal layer (1) and the second top metal layer (9) are respectively connected with the first bottom metal layer (5) and the second bottom metal layer (7) through top contact holes (2) penetrating through the top insulating layer (3).
3. A method for manufacturing the drain-shared trench dual MOS transistor device of claim 1 or 2, characterized by: the method comprises the following steps:
step 1, performing first oxidation and photoetching, forming a drift region (18) above a substrate (19), performing first oxidation treatment on the surface of the drift region (18) to form a first oxide layer (23), and performing first photoetching to form a groove (13);
step 2, performing first oxide deposition on the upper surface of the drift region (18), and forming a trench bottom insulating layer (11) at the bottom of the trench (13);
step 3, performing a second oxidation treatment on the drift region (18) to form a trench sidewall insulating layer (15);
step 4, performing second photoetching, namely filling polycrystalline silicon in the groove (13) and performing second photoetching, forming a groove in the middle of the groove (13) to form first polycrystalline silicon (12) and second polycrystalline silicon (14) at intervals;
step 5, depositing oxide for the second time, filling oxide in the groove (13) for the second time to form an insulating layer (10) in the middle of the groove, and then removing the first oxide layer (23) on the surface of the drift region (18);
step 6, forming a base region (17) and a source region (16) above the drift region (18);
and 7, forming a connection layer through a connection layer manufacturing process.
4. A method of manufacturing according to claim 3, wherein: the manufacturing process of the connecting layer comprises the following steps:
step 7-1, performing first insulation deposition and third photoetching, depositing a bottom insulation layer (4) on the surfaces of the groove (13), the base region (17) and the source region (16), and performing third photoetching downwards from the surface of the bottom insulation layer (4) to form a bottom contact hole (6);
step 7-2, performing first metal deposition and fourth photoetching, filling conductive materials in the bottom insulating layer (4), performing metal deposition on the surface of the bottom insulating layer (4), and performing fourth photoetching to form a first bottom metal (5) and a second bottom metal (7) which are arranged at intervals;
step 7-3, second insulating deposition and fifth photoetching, wherein a top insulating layer (3) is formed between and above the first bottom metal (5) and the second bottom metal (7), and fifth photoetching is carried out to form top contact holes (2) respectively contacted with the first bottom metal (5) and the second bottom metal (7);
and 7-4, performing second metal deposition and sixth photoetching, filling conductive materials in the top layer contact hole (2), performing second metal deposition to form a top layer metal layer, and performing sixth photoetching on the top layer metal layer to respectively form a first top layer metal (1) and a second top layer metal (9).
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