CN115424932A - LDMOS device and technological method - Google Patents
LDMOS device and technological method Download PDFInfo
- Publication number
- CN115424932A CN115424932A CN202210998915.0A CN202210998915A CN115424932A CN 115424932 A CN115424932 A CN 115424932A CN 202210998915 A CN202210998915 A CN 202210998915A CN 115424932 A CN115424932 A CN 115424932A
- Authority
- CN
- China
- Prior art keywords
- ldmos device
- region
- sti2
- layer
- field plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 101000658644 Homo sapiens Tetratricopeptide repeat protein 21A Proteins 0.000 claims abstract description 43
- 102100034913 Tetratricopeptide repeat protein 21A Human genes 0.000 claims abstract description 43
- 210000000746 body region Anatomy 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 230000015556 catabolic process Effects 0.000 claims abstract description 15
- 230000005684 electric field Effects 0.000 claims abstract description 15
- 238000000605 extraction Methods 0.000 claims abstract description 8
- 238000009826 distribution Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 30
- 238000005468 ion implantation Methods 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 230000002349 favourable effect Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 230000006872 improvement Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses an LDMOS device and a process method. The surface of the epitaxial layer is provided with STI and STI2; the epitaxial layer is also provided with a buried layer; the edge position above the buried layer is provided with a first deep well, and the buried layer and the first deep well at the edge form an isolation space; a third well is arranged at the outer side of the first deep well at an interval of STI, and a heavily doped extraction region is arranged in the third well to form extraction; the third well forms an isolation ring; a body region of the LDMOS device is arranged in the central region of the isolation space; drain regions of the LDMOS device are arranged on two sides of the body region, and STI2 is arranged on the surface of an epitaxial layer between the drain regions and the body region at intervals; and the top of one side of the grid electrode of the LDMOS device and the surface of the STI2 are covered with metal silicide to form a field plate. The structure of the invention raises the electric field of the drift region, effectively improves the electric field distribution of the drift region of the device, is beneficial to the depletion and expansion of the electric field of the drift region, can improve the breakdown voltage BV of the device, and can improve the offBV of the device by controlling the depth of STI2.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to an LDMOS device.
The invention also relates to a process method of the LDMOS device.
Background
The LDMOS has the characteristics of high voltage and high current of discrete devices, also absorbs the advantage of high-density intelligent logic control of a low-voltage integrated circuit, and the single chip realizes the functions which can be completed by a plurality of chips originally, thereby greatly reducing the area, lowering the cost, improving the energy efficiency and being in line with the development direction of miniaturization, intellectualization and low energy consumption of modern power electronic devices. Breakdown voltage and on-resistance are key parameters for measuring the high-voltage LDMOS device. Therefore, R should be reduced as much as possible to obtain the same breakdown voltage SP To improve the competitiveness of the product.
In a conventional LDMOS structure, as shown in fig. 1, an isolation region is formed by a buried layer and an N-type deep well. The LDMOS structure adopts a double STI structure, a body region is formed in a self-alignment mode, and a channel is formed through self-alignment injection after polycrystalline silicon is etched. The manufacturing process comprises the following steps: forming an epitaxial layer on a substrate, and then forming a double STI structure; forming an active region, including the formation of an N well or a P well and the injection of a drift region, depositing a gate dielectric layer and a polysilicon layer, completing the injection activation of a body region, and then etching to form a polysilicon gate structure; and forming a grid side wall, completing the ion implantation of the source region and the drain region, and completing the back-end process comprising a contact hole and metal.
The current switch type LDMOS device mainly encounters the following problems:
1. the breakdown voltage BV is limited by the length of the drift region and cannot be further increased to meet high voltage applications.
2. The square resistor Rsp is limited by the polysilicon length and cannot be scaled down to a large scale, so that it is difficult to reduce the overall chip area.
The main reasons why the analysis leads to the above problems are:
1. the inability to continue increasing the length of the drift region results in an increase in Rsp, limiting the improvement in ofbv (off-breakdown voltage, i.e., the breakdown voltage of the device in the off state without a channel).
2. The shortening of the length of the polysilicon results in an effective channel length that is too short for punch-through to occur.
Disclosure of Invention
The invention aims to provide an LDMOS device and a process method thereof, which have higher breakdown voltage performance.
In order to solve the above problems, the process method of the LDMOS device according to the present invention includes the following process steps:
the method comprises the steps of firstly, providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate; forming a buried layer of a second conductivity type in the epitaxial layer by ion implantation; etching and filling the surface of the epitaxial layer to form STI2;
forming an active region; forming a first deep well of a second conductive type by ion implantation, and forming a second well of the second conductive type by ion implantation in the first deep well;
performing ion implantation on the outer side of the first trap to form a third trap of the first conductivity type;
secondly, etching the epitaxial surface to form STI;
thirdly, performing ion implantation on the local area between the first deep wells above the buried layer to form a drift region;
fourthly, depositing a gate dielectric layer and a polysilicon layer on the surface of the epitaxial layer;
fifthly, etching the polysilicon layer, opening a body region injection window by utilizing the polysilicon layer etching, and performing ion injection to form a body region;
sixthly, etching the polycrystalline silicon layer to form a grid electrode of the LDMOS device;
depositing a first dielectric layer and etching to form a side wall of the grid, and then injecting a first heavily doped region of the first conduction type and a second heavily doped region of the second conduction type;
eighthly, forming a second dielectric layer, then etching, and forming a field plate isolation dielectric layer on part of the top surface and the side surface of the grid and the STI2 close to the grid;
a ninth step of forming a metal silicide covering layer on the field plate isolation dielectric layer, and etching the second dielectric layer in other areas to form contact holes and other holes;
and step ten, depositing and etching a metal layer to form the extraction electrode of the LDMOS.
Further, in the second step, the depth of STI is greater than STI2.
Further, the third step is an optional step; for the switch LDMOS device, a drift region is formed through ion implantation; for a non-switching LDMOS device, the step of ion implantation to form the drift region can be omitted.
Further, in the fourth step, the gate dielectric layer is silicon oxide or silicon oxynitride.
Further, the fifth step is an optional step; for a switch LDMOS device, a body region is formed through ion implantation; for a non-switching LDMOS device, the step of ion implantation to form the body region can be omitted.
Further, in the eighth step, after forming and etching the metal silicide, the metal silicide remained on the STI2 and forms a field plate with a shield-type structure together with the remained metal silicide on the top of the gate; and a contact lead-out is formed on the field plate and is connected with the source region lead-out through metal.
The invention provides an LDMOS device, which comprises a semiconductor substrate, wherein an epitaxial layer is formed on the semiconductor substrate;
STI and STI2 are arranged on the surface of the epitaxial layer; the depth of the STI is greater than that of the STI2; a buried layer of a second conductive type is also formed in the epitaxial layer; the edge position above the buried layer is provided with a first deep well of the second conduction type, and the buried layer and the first deep well at the edge form an isolation space;
the first deep well also comprises a second well of a second conduction type;
a third well with a first conductivity type is arranged at the outer side of the first deep well at an interval of STI, and a heavily doped lead-out region is arranged in the third well to form a lead-out; the third well forms an isolation ring;
the central region of the isolation space is provided with a body region of the LDMOS device; drain regions of the LDMOS device are arranged on two sides of the body region, and STI2 is arranged on the surface of an epitaxial layer between the drain regions and the body region at intervals;
the body region comprises a source region of the LDMOS device, and an epitaxial surface between the source region and the STI2 is a grid electrode of the LDMOS device;
the top of one side of the grid and the surface of the STI2 are covered with metal silicide to form a field plate.
Further, for the switch LDMOS device, the isolation space further includes a drift region located between the body region and the first deep well.
Furthermore, the field plate is led out through the contact hole and is connected with the source region.
Furthermore, the field plate and the STI2 can improve the electric field distribution of the drift region, are favorable for depletion and expansion of the drift region, raise the internal electric field and improve the breakdown voltage of the device.
Further, the off-state breakdown voltage of the LDMOS device can be adjusted by controlling the depth of the STI2.
According to the LDMOS device and the process method provided by the invention, the field plate connected with the source electrode is formed above the grid electrode and the STI2, so that the electric field of the drift region is raised, the electric field distribution of the drift region of the device is effectively improved, the electric field depletion and expansion of the drift region are facilitated, the breakdown voltage BV of the device can be improved, and meanwhile, the offBV of the device can be improved by controlling the depth of the STI2.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional LDMOS device.
FIGS. 2-11 are schematic diagrams of the process steps of the present invention.
FIG. 12 is a process flow diagram of the present invention.
Description of the reference numerals
1 is a buried layer, 2 is a first deep well (DNW), 3 is a second well, 4 is a third well, 5 is STI,6 is STI2,7 is polysilicon (gate), 8 is an N-type heavily doped region, 9 is a body region, 10 is a P-type heavily doped region, 11 is a contact hole, 12 is a metal silicide (field plate), 13 is a drift region, and 14 is a field plate isolation dielectric layer (second dielectric layer).
Detailed Description
The following detailed description of the present invention is given with reference to the accompanying drawings, and the technical solution of the present invention is clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are each provided with a non-precision ratio for the purpose of convenience and clarity in assisting in describing the embodiments of the present invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Due to the limited size of the drift region of the traditional LDMOS device structure, the breakdown voltage BV of the device cannot be further increased, and the problem of overlarge resistance caused by simply increasing the length of the drift region is solved from other aspects.
An embodiment of the present invention provides an LDMOS device, which is a switch N-type LDMOS device as shown in fig. 12. Includes a semiconductor substrate, such as an MCZ substrate, on which an epitaxial layer is formed.
And the surface of the epitaxial layer is provided with double STI: STI and STI2. The depth of the STI is greater than that of the STI2; an N-type buried layer 1 is also formed in the epitaxial layer; the buried layer 1 is provided with an N-type first deep well 2 at the edge position above the buried layer 1, and the buried layer 1 and the first deep well 2 at the edge of the buried layer form an isolation space.
The first deep well also contains a second well 3 of N-type.
And a P-type third well 4 is arranged at the outer side of the first deep well 2 at an interval of STI, and a P-type heavily doped lead-out region 10 is arranged in the third well 4 to form a lead-out. The third trap forms a peripheral isolation ring structure.
The central region of the isolation space is provided with a body region 9 of the LDMOS device, and a heavily doped N-type region 8 in the body region 9 is a source region of the LDMOS device. The epitaxial surface between the source region and the STI2 is the grid 7 of the LDMOS device.
And the drift region 13 of the LDMOS device is arranged on two sides of the body region 9, the drain region is positioned in the drift region 13, and STI2 is arranged on the surface of the epitaxial layer between the drain region and the body region at an interval.
The body region comprises a source region of the LDMOS device, and the top of one side of the grid and the surface of the STI2 are provided with a field plate isolation dielectric layer which covers the metal silicide and forms a field plate.
The field plate is led out through the contact hole and connected with the source region.
In the above embodiment, the structure of the metal silicide conductive field plate is adopted, and the metal silicide conductive field plate is in short circuit with the source region through the contact hole and the metal connecting line. In some devices, a conductive field plate is not manufactured, and a through hole is directly manufactured on the field plate isolation dielectric layer under the condition that the conductive field plate is not manufactured. Aiming at the improvement of the performance of the STI2 structure, the invention can realize the function of using the dielectric layer as a field plate by only using the dielectric layer on the STI2.
The field plate in the structure of the invention can improve the electric field distribution of the drift region by combining with the STI2, raise the internal electric field, contribute to the depletion expansion of the drift region and improve the breakdown voltage of the device. The off-state breakdown voltage of the LDMOS device can be adjusted by controlling the depth of the STI2.
The process method of the switch N-type LDMOS device, as shown in fig. 3 to 12, includes the following process steps:
the method comprises the steps of firstly, providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate; forming an N-type buried layer 1 in the epitaxial layer by ion implantation; and etching the surface of the epitaxial layer and filling to form the STI2. As shown in fig. 3.
Forming an active region; ion implantation is carried out to form an N-type first deep well 2, and ion implantation is carried out in the first deep well 2 to form an N-type second well 3. The second well 3 is located at an upper position in the first deep well 2 and partially below the STI2.
And ion implantation is carried out outside the first trap to form a third trap 4 of a P type. The P well 4 is arranged in the peripheral area of the device to form an isolation ring structure.
And secondly, etching the epitaxial surface and filling a dielectric layer such as silicon oxide to form STI, wherein the depth of the STI is greater than that of the STI2.
And thirdly, for the switch type LDMOS device, N-type ion implantation is carried out on a local area between the first deep wells 2 on the buried layer 1 to form a drift region. The non-switching LDMOS device can eliminate this step.
And fourthly, as shown in fig. 6, depositing a gate dielectric layer and a polysilicon layer on the surface of the epitaxial layer.
And fifthly, etching the polycrystalline silicon layer aiming at the switch type LDMOS device, opening a body region injection window by etching the polycrystalline silicon layer, and performing ion injection to form a body region 9. For non-switching LDMOS devices, the step of ion implantation to form the body region may be omitted.
And sixthly, etching the polycrystalline silicon layer to form the grid electrode 7 of the LDMOS device.
And seventhly, depositing a first dielectric layer and etching to form a side wall of the grid, and then injecting a P-type first heavily doped region 10 and an N-type second heavily doped region 8.
And eighthly, forming a second dielectric layer, etching, remaining the second dielectric layer on the STI2 after etching, and forming a field plate isolation dielectric layer 14 with a shield-type structure together with the top area of the grid part and the metal silicide reserved on the side surface.
And ninthly, forming a metal silicide covering layer on the field plate isolation dielectric layer, and carrying out a contact hole process. And etching the second dielectric layer in other areas to form a contact hole 11 and other holes. The extraction contact hole formed on the field plate is connected with the source region extraction through metal.
And step ten, depositing a metal layer and etching to form the metal interconnection of the LDMOS. And finishing the manufacture of the device.
According to the process method of the LDMOS device, the field plate connected with the source electrode is formed above the grid electrode and the STI2, so that the electric field of the drift region is raised, the electric field distribution of the drift region of the device is effectively improved, the electric field depletion and expansion of the drift region are facilitated, the breakdown voltage BV of the device can be improved, and meanwhile, the offBV of the device can be improved by controlling the depth of the STI2.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A process method of an LDMOS device is characterized in that: comprises the following process steps:
the method comprises the steps of firstly, providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate; forming a buried layer of a second conductivity type in the epitaxial layer by ion implantation; etching and filling the surface of the epitaxial layer to form STI2;
forming an active region; forming a first deep well of a second conductive type by ion implantation, and forming a second well of the second conductive type by ion implantation in the first deep well;
performing ion implantation on the outer side of the first trap to form a third trap of the first conductivity type;
secondly, etching the epitaxial surface to form STI;
thirdly, performing ion implantation on the local area between the first deep wells above the buried layer to form a drift region;
fourthly, depositing a gate dielectric layer and a polysilicon layer on the surface of the epitaxial layer;
fifthly, etching the polysilicon layer, opening a body region injection window by utilizing the polysilicon layer etching, and performing ion injection to form a body region;
sixthly, etching the polycrystalline silicon layer to form a grid electrode of the LDMOS device;
depositing a first dielectric layer and etching to form a side wall of the grid, and then injecting a first heavily doped region of the first conduction type and a second heavily doped region of the second conduction type;
eighthly, forming a second dielectric layer, then etching, and forming a field plate isolation dielectric layer on part of the top surface and the side surface of the grid and the STI2 close to the grid; ninth, etching the second dielectric layer in other areas to form a contact hole and a common hole;
and step ten, depositing and etching a metal layer to form the extraction electrode of the LDMOS.
2. The process for fabricating an LDMOS device as set forth in claim 1, wherein: in the second step, the depth of the STI is greater than STI2.
3. The process for fabricating an LDMOS device as set forth in claim 1, wherein: the third step is an optional step; for the switch LDMOS device, a drift region is formed through ion implantation; for a non-switching LDMOS device, the step of ion implantation to form the drift region can be omitted.
4. The process of switching an LDMOS device as set forth in claim 1, wherein: and in the fourth step, the gate dielectric layer is silicon oxide or silicon oxynitride.
5. The process for fabricating an LDMOS device as set forth in claim 1, wherein: the fifth step is an optional step; for a switch LDMOS device, a body region is formed through ion implantation; for a non-switching LDMOS device, the step of ion implantation to form the body region can be omitted.
6. The process for fabricating an LDMOS device as set forth in claim 1, wherein: in the ninth step, a conductive material film layer can be selectively covered on the field plate isolation dielectric layer to form a conductive field plate structure; the conductive material film layer is metal silicide or metal.
7. The process for manufacturing an LDMOS device as set forth in claim 6, wherein: if the conductive field plate is not formed, directly manufacturing a through hole on the field plate isolation dielectric layer; if the structure with the conductive field plate is manufactured, after metal silicide is formed and etched, the metal silicide on the STI2 is remained, and the field plate with a shield-type structure is formed together with the remained metal silicide on the top of the grid; and a contact lead-out is formed on the field plate and is connected with the source region lead-out through metal.
8. An LDMOS device, comprising: the semiconductor device comprises a semiconductor substrate, wherein an epitaxial layer is formed on the semiconductor substrate;
STI and STI2 are arranged on the surface of the epitaxial layer; the depth of the STI is greater than that of the STI2; a buried layer of a second conductive type is also formed in the epitaxial layer; the edge position above the buried layer is provided with a first deep well of the second conduction type, and the buried layer and the first deep well at the edge form an isolation space;
the first deep well also comprises a second well of a second conduction type;
a third well which is provided with a first conductivity type and is provided with an STI at intervals is arranged at the outer side of the first deep well, and a heavily doped extraction region is arranged in the third well to form extraction; the third well forms an isolation ring;
a body region of the LDMOS device is arranged in the central region of the isolation space; drain regions of the LDMOS device are arranged on two sides of the body region, and STI2 is arranged on the surface of an epitaxial layer between the drain regions and the body region at intervals;
the body region comprises a source region of the LDMOS device, and an epitaxial surface between the source region and the STI2 is a grid electrode of the LDMOS device;
the top of one side of the grid and the surface of the STI2 are covered with metal silicide and form a field plate.
9. The LDMOS device of claim 8, wherein: for the switch LDMOS device, the isolation space further comprises a drift region which is positioned between the body region and the first deep well.
10. The LDMOS device of claim 8, wherein: the field plate is led out through the contact hole and connected with the source region.
11. The LDMOS device of claim 8, wherein: the field plate and the STI2 can improve the electric field distribution of the drift region, are favorable for the depletion expansion of the drift region, raise the internal electric field and improve the breakdown voltage of the device.
12. The LDMOS device of claim 8, wherein: the off-state breakdown voltage of the LDMOS device can be adjusted by controlling the depth of the STI2.
13. The LDMOS device set forth in any one of claims 8 to 12 wherein: the first conductive type is P type, and the second conductive type is N type; or vice versa.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210998915.0A CN115424932A (en) | 2022-08-19 | 2022-08-19 | LDMOS device and technological method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210998915.0A CN115424932A (en) | 2022-08-19 | 2022-08-19 | LDMOS device and technological method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115424932A true CN115424932A (en) | 2022-12-02 |
Family
ID=84197579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210998915.0A Pending CN115424932A (en) | 2022-08-19 | 2022-08-19 | LDMOS device and technological method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115424932A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115881786A (en) * | 2023-01-19 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | LDMOS device and manufacturing method thereof |
| CN117457747A (en) * | 2023-12-22 | 2024-01-26 | 粤芯半导体技术股份有限公司 | DEMOS structure of embedded flash memory technology and preparation method thereof |
| CN117727801A (en) * | 2024-02-05 | 2024-03-19 | 芯联先锋集成电路制造(绍兴)有限公司 | Method for adjusting breakdown voltage temperature drift of voltage stabilizing tube |
-
2022
- 2022-08-19 CN CN202210998915.0A patent/CN115424932A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115881786A (en) * | 2023-01-19 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | LDMOS device and manufacturing method thereof |
| CN117457747A (en) * | 2023-12-22 | 2024-01-26 | 粤芯半导体技术股份有限公司 | DEMOS structure of embedded flash memory technology and preparation method thereof |
| CN117727801A (en) * | 2024-02-05 | 2024-03-19 | 芯联先锋集成电路制造(绍兴)有限公司 | Method for adjusting breakdown voltage temperature drift of voltage stabilizing tube |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6365942B1 (en) | MOS-gated power device with doped polysilicon body and process for forming same | |
| JP3202021B2 (en) | Punch-through field-effect transistor | |
| US9911840B2 (en) | Self aligned trench MOSFET with integrated diode | |
| CN102237279B (en) | Oxide terminated trench MOSFET with three or four masks | |
| CN100334731C (en) | Trench DMOS transistor with embedded trench schottky rectifier | |
| US8022476B2 (en) | Semiconductor device having vertical and horizontal type gates and method for fabricating the same | |
| JP4024503B2 (en) | Semiconductor device and manufacturing method thereof | |
| US8445958B2 (en) | Power semiconductor device with trench bottom polysilicon and fabrication method thereof | |
| CN115424932A (en) | LDMOS device and technological method | |
| JP2000353805A (en) | Mos gate power device having extended trench and doped region, and process of forming the same | |
| US20200020798A1 (en) | Power mosfet with an integrated pseudo-schottky diode in source contact trench | |
| CN104779166B (en) | A kind of plough groove type divides grid power device and its manufacture method | |
| CN101290936A (en) | Semiconductor device and method for manufactruing of the same | |
| CN108400168B (en) | LDMOS device and manufacturing method thereof | |
| CN104377244A (en) | Device structure lowering LDMOS on resistance | |
| CN112117332B (en) | LDMOS device and process method | |
| CN111063737A (en) | LDMOS device and technological method | |
| CN109755310B (en) | Power transistor with split-gate structure | |
| CN101803030A (en) | Manufacturing method of semiconductor power devices | |
| CN111106043B (en) | Power semiconductor device cell structure, preparation method thereof and power semiconductor device | |
| CN112864250A (en) | Groove type power semiconductor device for improving grid leakage charge and preparation method thereof | |
| CN111223931B (en) | Trench MOSFET and manufacturing method thereof | |
| CN113690303A (en) | Semiconductor device and method for manufacturing the same | |
| CN108091695B (en) | Vertical double-diffused field effect transistor and manufacturing method thereof | |
| CN115547838A (en) | Preparation method of metal oxide semiconductor device and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |