CN111063737A - LDMOS device and technological method - Google Patents
LDMOS device and technological method Download PDFInfo
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 136
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 136
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 39
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses an LDMOS device, which is characterized in that a substrate of a first conduction type is provided with a body region of the first conduction type and a drift region of a second conduction type, and the body region of the first conduction type also comprises a heavily doped first conduction type doping region and a heavily doped second conduction type doping region; a metal silicide is arranged above the first conductive type doped region and the second conductive type doped region; the drift region of the second conduction type is also provided with a heavily doped second conduction type doping region and a metal silicide positioned above the second conduction type doping region; the drift region of the second conduction type is also provided with an isolation silicon oxide layer, one side of the isolation silicon oxide layer extends to the lower part of the polysilicon gate structure, the other side of the isolation silicon oxide layer extends to the second conduction type doping region in the drift region of the second conduction type, and a metal silicification reaction blocking silicon oxide layer is arranged above the isolation silicon oxide layer. The process method of the invention can be compatible with the BCD process.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an NLDMOS device. The invention also relates to a process method of the NLDMOS device.
Background
DMOS (Double-diffused MOS) has the characteristics of high voltage resistance, high current driving capability, extremely low power consumption and the like, and is widely applied to power supplies at presentIn the management chip. In an LDMOS (Lateral Double-diffused MOSFET) device, on-resistance is an important index. In the BCD (Bipolar-CMOS-DMOS) process, although the LDMOS and the CMOS are integrated in the same chip, the requirements of the switching tube application cannot be met due to the contradiction/compromise between the high breakdown voltage bv (Breakdown voltage) and the low characteristic on-Resistance (Specific on-Resistance). The high-voltage LDMOS has the characteristics of high voltage and high current of discrete devices, also absorbs the advantage of high-density intelligent logic control of a low-voltage integrated circuit, realizes the functions which can be completed by a plurality of chips originally by a single chip, greatly reduces the area, reduces the cost, improves the energy efficiency, and accords with the development direction of miniaturization, intellectualization and low energy consumption of modern power electronic devices. Breakdown voltage and on-resistance are key parameters for measuring the high-voltage LDMOS device. Therefore, the breakdown voltage should be reduced as much as possible to obtain the same breakdown voltage
To improve the competitiveness of the product.
In a conventional LDMOS structure, as shown in fig. 1, a field oxide region 103 in an sti (shallow trench isolation) process is formed by the following steps: a) etching silicon to form a shallow trench, b) performing thermal oxidation to form an oxide layer on the surface of the shallow trench, c) filling the oxide layer into the trench, and d) forming field oxide 103 by chemical mechanical polishing. In the locos (local oxidation of silicon) process, 103 is formed by oxidizing localized silicon.
Another LDMOS structure is shown in fig. 2, a field plate silicon oxide layer 103 is formed by depositing a silicon oxide layer on the surface of silicon and selectively etching the silicon oxide layer. In contrast to the structure of fig. 1, the field oxide 103 in fig. 2 is placed on the surface of the substrate or epitaxial layer.
The breakdown voltage BV or the characteristic on-resistance of the LDMOS devices with the two structures
Are not ideal.
Disclosure of Invention
The invention aims to provide an LDMOS device which has better breakdown voltage and on-resistance performance.
Another technical problem to be solved by the present invention is to provide a process method of the LDMOS device.
In order to solve the above problems, the LDMOS device according to the present invention has a body region of a first conductivity type and a drift region of a second conductivity type in a substrate of the first conductivity type.
The substrate surface of the first conductive type is also provided with a polycrystalline silicon grid structure, the polycrystalline silicon grid structure comprises a grid dielectric layer, a polycrystalline silicon grid, metal silicide above the polycrystalline silicon grid and grid side walls, the grid dielectric layer is positioned on the substrate surface and isolates the polycrystalline silicon grid from the substrate, and the side walls are positioned on two sides of the polycrystalline silicon grid.
The polycrystalline silicon gate structure is positioned on the surface of the substrate between the body region of the first conduction type and the drift region of the second conduction type and is overlapped with the body region and the drift region which are positioned on two sides of the polycrystalline silicon gate structure.
The body region of the first conduction type also comprises a heavily doped first conduction type doped region and a heavily doped second conduction type doped region; and a metal silicide is arranged above the first conductive type doped region and the second conductive type doped region.
The drift region of the second conduction type is also provided with a heavily doped second conduction type doping region and a metal silicide positioned above the second conduction type doping region.
The drift region of the second conduction type is also provided with an isolation silicon oxide layer, one side of the isolation silicon oxide layer extends to the lower part of the polysilicon gate structure, and the other side of the isolation silicon oxide layer extends to the second conduction type doping region in the drift region of the second conduction type.
And a metal silicification reaction blocking silicon oxide layer is arranged above the isolation silicon oxide layer.
The further improvement is that the surface of the substrate is also provided with an insulating medium layer and an interlayer medium; the interlayer dielectric is provided with a plurality of contact holes which are respectively contacted with the metal silicide in the body region, the metal silicide above the polysilicon grid, the metal silicification reaction blocking silicon oxide layer above the isolation silicon oxide layer and the surface of the metal silicide in the drift region, so that all structures are led out.
The further improvement is that the surface of the interlayer dielectric is also provided with a first metal layer, wherein the contact hole above the polysilicon gate structure is connected with the contact hole above the metal silicification reaction barrier silicon oxide layer through the first metal layer.
In a further improvement, the thickness of the isolation silicon oxide layer is defined as the thickness of the first field oxygen, and the sum of the thicknesses of the isolation silicon oxide layer and the metal silicidation reaction blocking silicon oxide layer is defined as the thickness of the second field oxygen; the first field oxide and the polysilicon grid form a first field plate, and the second field oxide and the contact hole above the second field oxide form a second field plate.
In a further improvement, the first field plate and the second field plate have different thicknesses, so that the LDMOS device has a better breakdown voltage-characteristic on-resistance relation.
In order to solve the above problems, the process method of the LDMOS device according to the present invention comprises the following process steps:
step one, an isolation silicon oxide layer is formed in a substrate of a first conduction type, and then a body region of the first conduction type and a drift region of a second conduction type are implanted to form the body region and the drift region respectively.
Forming a thermal oxidation layer, depositing a polycrystalline silicon layer, and etching to form a polycrystalline silicon grid and a grid dielectric layer; and depositing an insulating medium layer and etching to form a grid side wall, and then carrying out ion implantation on the heavily doped first conductive type doped region and the heavily doped second conductive type doped region.
Depositing a metal silicification reaction silicon oxide blocking layer and carrying out selective etching to expose the heavily doped first conductive type doping area and the heavily doped second conductive type doping area and the top of the polycrystalline silicon grid, reserving the metal silicification reaction silicon oxide blocking layer for isolating the surface of the silicon oxide layer, then carrying out metal silicification reaction, and forming metal silicide on the top of the polycrystalline silicon grid and above the first conductive type doping area and the second conductive type doping area; and depositing an insulating medium layer and an interlayer medium layer.
And step four, etching the interlayer medium and the insulating medium layer to form a contact hole, filling and flattening, and depositing a first metal layer on the surface of the interlayer medium.
In a further improvement, in the first step, an isolation silicon oxide layer is formed by STI or LOCOS process, and the isolation silicon oxide layer is located on the surface layer in the drift region.
In the second step, the heavily doped region of the first conductivity type is used for leading out the body region of the first conductivity type, and the heavily doped region of the second conductivity type forms a source region and a drain region of the LDMOS device.
The further improvement is that in the fourth step, when the contact holes are etched and filled, a plurality of rows of contact holes are formed above the metal silicification reaction barrier silicon oxide layer, and the plurality of rows of contact holes are in short circuit with the polysilicon gate through the first metal layer to form the second field plate. The contact holes in multiple rows can also be in short circuit with an electrode led out from a source region or a body region of the LDMOS device through the first metal layer to form a second field plate.
In a further improvement, the outer side of the metal silicidation reaction blocking silicon oxide layer does not need to be aligned with the outer side of the isolation oxide layer; and a metal silicification reaction barrier silicon oxide layer is required to be arranged below the contact hole on the outermost side of the metal silicification reaction barrier silicon oxide layer.
The invention provides another LDMOS device, which is provided with a body region of a first conduction type and a drift region of a second conduction type in a substrate of the first conduction type.
The substrate surface of the first conductive type is also provided with a polycrystalline silicon grid structure, the polycrystalline silicon grid structure comprises a grid dielectric layer, a polycrystalline silicon grid, metal silicide above the polycrystalline silicon grid and grid side walls, the grid dielectric layer is positioned on the substrate surface and isolates the polycrystalline silicon grid from the substrate, and the side walls are positioned on two sides of the polycrystalline silicon grid.
The polycrystalline silicon gate structure is positioned on the surface of the substrate between the body region of the first conduction type and the drift region of the second conduction type and is overlapped with the body region and the drift region which are positioned on two sides of the polycrystalline silicon gate structure.
The body region of the first conduction type also comprises a heavily doped first conduction type doped region and a heavily doped second conduction type doped region; and a metal silicide is arranged above the first conductive type doped region and the second conductive type doped region.
The drift region of the second conduction type is also provided with a heavily doped second conduction type doping region and a metal silicide positioned above the second conduction type doping region.
The surface of the drift region of the second conduction type is also provided with an isolation silicon oxide layer, one side of the isolation silicon oxide layer extends to the lower part of the polysilicon gate structure to be connected with the gate dielectric layer, and the other side of the isolation silicon oxide layer is aligned with the nearest side of the second conduction type doped region in the drift region of the second conduction type.
And a metal silicification reaction blocking silicon oxide layer is arranged above the isolation silicon oxide layer.
The further improvement is that the surface of the substrate is also provided with an insulating medium layer and an interlayer medium; the interlayer dielectric is provided with a plurality of contact holes which are respectively contacted with the metal silicide in the body region, the metal silicide above the polysilicon grid, the metal silicification reaction blocking silicon oxide layer above the isolation silicon oxide layer and the surface of the metal silicide in the drift region, so that all structures are led out.
The further improvement is that the surface of the interlayer dielectric is also provided with a first metal layer, wherein the contact hole above the polysilicon gate structure is connected with the contact hole above the metal silicification reaction barrier silicon oxide layer through the first metal layer.
In a further improvement, the thickness of the isolation silicon oxide layer is defined as the thickness of the first field oxygen, and the sum of the thicknesses of the isolation silicon oxide layer and the metal silicidation reaction blocking silicon oxide layer is defined as the thickness of the second field oxygen; the first field oxide and the polysilicon grid form a first field plate, and the second field oxide and the contact hole above the second field oxide form a second field plate.
In a further improvement, the first field plate and the second field plate have different thicknesses, so that the LDMOS device has a better breakdown voltage-characteristic on-resistance relation.
The invention relates to a process method of an LDMOS device, which comprises the following process steps:
step one, an isolation silicon oxide layer is formed on the surface of a substrate of a first conduction type, and then a body region of the first conduction type and a drift region of a second conduction type are implanted to form the body region and the drift region respectively.
Forming a thermal oxidation layer, depositing a polycrystalline silicon layer, and etching to form a polycrystalline silicon grid and a grid dielectric layer; and depositing an insulating medium layer and etching to form a grid side wall, and then carrying out ion implantation on the heavily doped first conductive type doped region and the heavily doped second conductive type doped region.
Depositing a metal silicification reaction silicon oxide blocking layer and carrying out selective etching to expose the heavily doped first conductive type doping area and the heavily doped second conductive type doping area and the top of the polycrystalline silicon grid, reserving the metal silicification reaction silicon oxide blocking layer for isolating the surface of the silicon oxide layer, then carrying out metal silicification reaction, and forming metal silicide on the top of the polycrystalline silicon grid and above the first conductive type doping area and the second conductive type doping area; and depositing an insulating medium layer and an interlayer medium layer.
And step four, etching the interlayer medium and the insulating medium layer to form a contact hole, filling and flattening, and depositing a first metal layer on the surface of the interlayer medium.
In a further improvement, in the first step, the isolation silicon oxide layer is formed by depositing a silicon oxide layer and selectively etching, and the isolation silicon oxide layer is located on the surface layer in the drift region.
In the second step, the heavily doped region of the first conductivity type is used for leading out the body region of the first conductivity type, and the heavily doped region of the second conductivity type forms a source region and a drain region of the LDMOS device.
The further improvement is that in the fourth step, when the contact holes are etched and filled, a plurality of rows of contact holes are formed above the metal silicification reaction barrier silicon oxide layer, and the plurality of rows of contact holes are in short circuit with the polysilicon gate through the first metal layer to form the second field plate. The contact holes in multiple rows can also be in short circuit with an electrode led out from a source region or a body region of the LDMOS device through the first metal layer to form a second field plate.
In a further improvement, the outer side of the metal silicidation reaction blocking silicon oxide layer does not need to be completely aligned with the outer side of the isolation oxide layer; and a metal silicification reaction barrier silicon oxide layer is required to be arranged below the contact hole on the outermost side of the metal silicification reaction barrier silicon oxide layer.
The LDMOS device can be integrated with BCD in process. The field oxygen of the device is composed of two silicon oxide layers with different thicknesses, the thickness of the first field oxygen is the thickness of the isolation silicon oxide layer, the thickness of the second field oxygen is the sum of the thicknesses of the isolation silicon oxide layer and the metal silicification reaction silicon oxide blocking layer, the first field oxygen and the polysilicon gate form a first field plate of the LDMOS device, the second field oxygen and the contact hole form a second field plate of the LDMOS device, and the first field plate and the second field plate are connected together in a short mode through a first metal layer. Two field plates with different thickness field oxygen can obtain better BV-Rsp relation.
Drawings
Fig. 1 is a cross-sectional view of a conventional LDMOS device.
Fig. 2 is a cross-sectional view of another conventional LDMOS device.
FIG. 3 is a diagram of an LDMOS device according to the present invention.
Fig. 4-6 are schematic diagrams of process steps for fabricating the structure shown in fig. 3 according to the present invention.
Fig. 7 shows another LDMOS device provided by the present invention.
Fig. 8-10 are schematic diagrams of process steps for fabricating the structure shown in fig. 7 according to the present invention.
Fig. 11 is a graph of simulation effect of the device structure of the present invention.
Description of the reference numerals
101-a metal silicidation reaction blocking silicon oxide layer, 102-a P-type substrate/a P-type epitaxial layer, 103-an isolation silicon oxide layer, 104-a drift region, 105-a body region, 106-a gate dielectric layer, 107-a polysilicon gate, 108-a heavily doped second conductivity type doped region, 109-a heavily doped first conductivity type doped region, 110-a metal silicide, 111-a side wall, 112-a contact hole, 113-a first metal layer, 114-an interlayer dielectric layer and 115-an insulating dielectric layer.
Detailed Description
In the following embodiments, the present invention is described by taking an N-type LDMOS device as an example, that is, in the embodiment, the first conductivity type is defined as P-type, and the second conductivity type is defined as N-type. In other opposite embodiments, the first conductivity type may be defined as N-type, and the second conductivity type may be defined as P-type, which is not further specifically described in the present invention.
The first embodiment is as follows:
an LDMOS device according to the present invention, as shown in fig. 3, has a P-type body region 105 and an N-type drift region 104 in a P-type substrate 102 (or P-type epitaxy).
The P-type substrate surface is also provided with a polysilicon gate structure, the polysilicon gate structure comprises a gate dielectric layer 106, a polysilicon gate 107, a metal silicide 110 above the polysilicon gate and gate side walls 111, the gate dielectric layer is positioned on the substrate surface and isolates the polysilicon gate from the substrate, and the side walls are positioned on two sides of the polysilicon gate.
The polysilicon gate structure is located on the surface of the substrate between the P-type body region and the N-type drift region, and overlaps with both the body region 105 and the drift region 106 located on both sides of the P-type body region, that is, the polysilicon gate structure covers the body region 105 to the left and covers the isolation silicon oxide layer 103 to the right in fig. 3.
The P-type body region further comprises a heavily doped P-type doped region 109 and a heavily doped N-type doped region 108; there is also a metal silicide above the P-type doped region 109 and the N-type doped region 108. The P-type doped region 109 in the body region is used for leading out the body region, and the N-type doped region is used as a source region of the LDMOS device.
The N-type drift region 104 further has a heavily doped N-type doped region 108 as a drain region of the LDMOS device, and a metal silicide 110 is disposed above the drain region.
The isolation silicon oxide layer 103 in the N-type drift region 104 has one side extending under the polysilicon gate structure and the other side extending to laterally contact the drain region.
The isolation silicon oxide layer 103 also has a metal silicidation reaction blocking silicon oxide layer 101 thereon.
The surface of the substrate is also provided with an insulating dielectric layer 115 and an interlayer dielectric 114, the interlayer dielectric 114 is provided with a plurality of contact holes 112 which are respectively contacted with the metal silicide 110 in the body region 105, the metal silicide above the polysilicon gate, the metal silicidation reaction blocking silicon oxide layer above the isolation silicon oxide layer and the surface of the metal silicide in the drift region, so that all structures are led out.
The surface of the interlayer dielectric is also provided with a first metal layer 113, wherein the contact hole above the polysilicon gate structure and the contact hole above the metal silicidation reaction barrier silicon oxide layer are also in short circuit through the first metal layer 113.
The thickness of the isolation silicon oxide layer 103 is defined as the thickness of the first field oxygen, and the sum of the thicknesses of the isolation silicon oxide layer 103 and the metal silicidation reaction blocking silicon oxide layer 101 is defined as the thickness of the second field oxygen; the first field oxide and the polysilicon grid form a first field plate, and the second field oxide and the contact hole above the second field oxide form a second field plate.
According to the LDMOS device structure, the first field plate and the second field plate have different thicknesses, so that the distribution of an electric field is optimized, the modulation of the electric field is enhanced, and the LDMOS device has a better breakdown voltage-characteristic on-resistance relation.
The above-described LDMOS device is fabricated by the following process steps with reference to fig. 4-6 and fig. 3, respectively:
in the first step, an isolation silicon oxide layer 103 is formed in a P substrate 102 by STI or LOCOS process, and then a P-type body region and an N-type drift region are implanted to form a body region 105 and a drift region 104, respectively.
Step two, forming a thermal oxidation layer, depositing a polycrystalline silicon layer, and etching to form a polycrystalline silicon grid 107 and a grid dielectric layer 106; and depositing an insulating medium layer and etching to form a gate side wall 111, and then performing ion implantation on the heavily doped P-type doped region 109 and the heavily doped N-type doped region 108.
Depositing a metal silicidation reaction barrier silicon oxide layer, performing selective etching to expose the heavily doped P-type doped region and the heavily doped N-type doped region and the top of the polysilicon gate 107, reserving the metal silicidation reaction barrier silicon oxide layer 101 on the surface of the isolation silicon oxide layer, performing metal silicidation reaction, and forming a metal silicide 110 on the top of the polysilicon gate and above the first conductive type doped region and the second conductive type doped region; an insulating dielectric layer 115 and an interlevel dielectric layer 114 are deposited.
And step four, etching the interlayer dielectric and the insulating dielectric layer to form a contact hole 112, filling and flattening, and depositing a first metal layer on the surface of the interlayer dielectric. And when the contact holes are etched and filled, a plurality of rows of contact holes are formed above the metal silicification reaction barrier silicon oxide layer, and the plurality of rows of contact holes are in short circuit with the polysilicon grid through the first metal layer to form a second field plate. The contact holes in multiple rows can also be in short circuit with an electrode led out from a source region or a body region of the LDMOS device through the first metal layer to form a second field plate.
The outer side of the metal silicification reaction barrier silicon oxide layer does not need to be aligned with the outer side of the isolation oxide layer; and a metal silicification reaction silicon oxide blocking layer is required to be arranged below the contact hole on the outermost side of the metal silicification reaction silicon oxide blocking layer, namely the contact hole of the second field plate is required to be in complete contact with the metal silicification reaction silicon oxide blocking layer.
Example two:
as shown in fig. 7, the main structure of another LDMOS device provided by the present invention is substantially the same as that of the first embodiment, and is not repeated herein, but is different from the first embodiment in that the isolation silicon oxide layer 103 is located on the surface of the substrate, and the structure in the first embodiment is that the isolation silicon oxide layer 103 is embedded in the substrate.
One side of the isolation silicon oxide layer 103 extends below the polysilicon gate structure to be connected with the gate dielectric layer, i.e. embedded in the polysilicon gate, and the other side thereof is aligned with the nearest side of the N-type doped region 108 in the N-type drift region.
The isolation silicon oxide layer 103 also has a metal silicidation reaction blocking silicon oxide layer 101 thereon.
The thickness of the isolation silicon oxide layer 103 is defined as the thickness of the first field oxygen, and the sum of the thicknesses of the isolation silicon oxide layer and the metal silicidation reaction blocking silicon oxide layer is defined as the thickness of the second field oxygen; the first field oxide and the polysilicon gate form a first field plate on the left side, and the second field oxide and a contact hole above the second field oxide form a second field plate on the right side.
The first field plate and the second field plate have different thicknesses, so that the LDMOS device has a better breakdown voltage-characteristic on-resistance relation.
The above-described LDMOS device is fabricated by the following process steps with reference to fig. 8-10 and fig. 7, respectively:
firstly, depositing a silicon oxide layer on the surface of a P-type substrate, selectively etching to form an isolation silicon oxide layer 103, and then implanting a P-type body region and an N-type drift region to form a body region 105 and a drift region 104 respectively.
Step two, forming a thermal oxidation layer, depositing a polycrystalline silicon layer, and etching to form a polycrystalline silicon grid 107 and a grid dielectric layer 106; depositing an insulating medium layer and etching to form a grid side wall 111, and then performing ion implantation on the heavily doped P-type doped region 109 and the heavily doped N-type doped region 108; the heavily doped P-type doped region 109 is used for leading out the body region 105, and the heavily doped N-type doped region forms a source region and a drain region of the LDMOS device.
Depositing a metal silicidation reaction barrier silicon oxide layer and performing selective etching to expose the heavily doped first conductive type doping region and the second conductive type doping region and the top of the polycrystalline silicon grid, reserving the metal silicidation reaction barrier silicon oxide layer for isolating the surface of the silicon oxide layer, then performing metal silicidation reaction, and forming metal silicide 110 on the top of the polycrystalline silicon grid and above the first conductive type doping region and the second conductive type doping region; an insulating dielectric layer 115 and an interlevel dielectric layer 114 are deposited.
And step four, etching the interlayer dielectric and the insulating dielectric layer to form a contact hole 112, filling and flattening, and depositing a first metal layer 113 on the surface of the interlayer dielectric. When the contact holes are etched and filled, a plurality of rows of contact holes are formed above the metal silicification reaction barrier silicon oxide layer 101, and the plurality of rows of contact holes are in short circuit with the polysilicon gate through the first metal layer to form a second field plate. The contact holes in multiple rows can also be in short circuit with an electrode led out from a source region or a body region of the LDMOS device through the first metal layer to form a second field plate. The outer side of the metal silicification reaction barrier silicon oxide layer does not need to be completely aligned with the outer side of the isolation oxide layer; and a metal silicification reaction barrier silicon oxide layer is required to be arranged below the contact hole on the outermost side of the metal silicification reaction barrier silicon oxide layer.
The LDMOS device can obtain higher BV-Rsp relation. Through verification, as shown in fig. 11, under the condition that the breakdown voltage BV is not changed, the on-current of the drain terminal can be improved by 17%.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (22)
1. An LDMOS device has a body region of a first conductivity type and a drift region of a second conductivity type in a substrate of the first conductivity type;
the substrate surface of the first conductive type is also provided with a polycrystalline silicon grid structure, the polycrystalline silicon grid structure comprises a grid dielectric layer, a polycrystalline silicon grid, metal silicide above the polycrystalline silicon grid and grid side walls, the grid dielectric layer is positioned on the substrate surface and isolates the polycrystalline silicon grid from the substrate, and the side walls are positioned on two sides of the polycrystalline silicon grid;
the polycrystalline silicon gate structure is positioned on the surface of the substrate between the body region of the first conduction type and the drift region of the second conduction type and is overlapped with the body region and the drift region on the two sides of the polycrystalline silicon gate structure;
the body region of the first conduction type also comprises a heavily doped first conduction type doped region and a heavily doped second conduction type doped region; a metal silicide is arranged above the first conductive type doped region and the second conductive type doped region;
the drift region of the second conduction type is also provided with a heavily doped second conduction type doping region and a metal silicide positioned above the second conduction type doping region;
the method is characterized in that: the drift region of the second conduction type is also provided with an isolating silicon oxide layer, one side of the isolating silicon oxide layer extends to the lower part of the polysilicon gate structure, and the other side of the isolating silicon oxide layer extends to the second conduction type doping region in the drift region of the second conduction type;
and a metal silicification reaction blocking silicon oxide layer is arranged above the isolation silicon oxide layer.
2. The LDMOS device of claim 1, wherein: the surface of the substrate is also provided with an insulating medium layer and an interlayer medium; the interlayer dielectric is provided with a plurality of contact holes which are respectively contacted with the metal silicide in the body region, the metal silicide above the polysilicon grid, the metal silicification reaction blocking silicon oxide layer above the isolation silicon oxide layer and the surface of the metal silicide in the drift region, so that all structures are led out.
3. The LDMOS device of claim 2, wherein: the surface of the interlayer dielectric is also provided with a first metal layer, wherein the contact hole above the polysilicon gate structure is connected with the contact hole above the metal silicification reaction barrier silicon oxide layer through the first metal layer.
4. The LDMOS device of claim 1, wherein: the thickness of the isolation silicon oxide layer is defined as the thickness of first field oxygen, and the sum of the thicknesses of the isolation silicon oxide layer and the metal silicidation reaction blocking silicon oxide layer is defined as the thickness of second field oxygen; the first field oxide and the polysilicon grid form a first field plate, and the second field oxide and the contact hole above the second field oxide form a second field plate.
5. The LDMOS device of claim 4, wherein: the first field plate and the second field plate have different thicknesses, so that the LDMOS device has a better breakdown voltage-characteristic on-resistance relation.
6. The process for fabricating the LDMOS device of claim 1, wherein: comprises the following process steps:
step one, forming an isolation silicon oxide layer in a substrate of a first conduction type, and then injecting a body region of the first conduction type and a drift region of a second conduction type to form the body region and the drift region respectively;
forming a thermal oxidation layer, depositing a polycrystalline silicon layer, and etching to form a polycrystalline silicon grid and a grid dielectric layer; depositing an insulating medium layer and etching to form a grid side wall, and then carrying out ion implantation on the heavily doped first conductive type doped region and the heavily doped second conductive type doped region;
depositing a metal silicification reaction silicon oxide blocking layer and carrying out selective etching to expose the heavily doped first conductive type doping area and the heavily doped second conductive type doping area and the top of the polycrystalline silicon grid, reserving the metal silicification reaction silicon oxide blocking layer for isolating the surface of the silicon oxide layer, then carrying out metal silicification reaction, and forming metal silicide on the top of the polycrystalline silicon grid and above the first conductive type doping area and the second conductive type doping area; depositing an insulating medium layer and an interlayer medium layer;
and step four, etching the interlayer medium and the insulating medium layer to form a contact hole, filling and flattening, and depositing and etching a first metal layer on the surface of the interlayer medium.
7. The process for manufacturing an LDMOS device as set forth in claim 6, wherein: in the first step, an isolation silicon oxide layer is formed by an STI or LOCOS process, and the isolation silicon oxide layer is located on a surface layer in the drift region.
8. The process for manufacturing an LDMOS device as set forth in claim 6, wherein: in the second step, the heavily doped first conduction type doped region is used for leading out the body region of the first conduction type, and the heavily doped second conduction type doped region forms a source region and a drain region of the LDMOS device.
9. The process for manufacturing an LDMOS device as set forth in claim 6, wherein: in the fourth step, when the contact holes are etched and filled, a plurality of rows of contact holes are formed above the metal silicification reaction barrier silicon oxide layer, and the plurality of rows of contact holes are in short circuit with the polysilicon gate through the first metal layer to form the second field plate.
10. The process for fabricating an LDMOS device as set forth in claim 9, wherein: the contact holes in multiple rows are in short circuit with an electrode led out from a source region or a body region of the LDMOS device through the first metal layer to form a second field plate.
11. The process for fabricating an LDMOS device as set forth in claim 9, wherein: the outer side of the metal silicification reaction barrier silicon oxide layer does not need to be aligned with the outer side of the isolation oxide layer; and a metal silicification reaction barrier silicon oxide layer is required to be arranged below the contact hole on the outermost side of the metal silicification reaction barrier silicon oxide layer.
12. An LDMOS device has a body region of a first conductivity type and a drift region of a second conductivity type in a substrate of the first conductivity type;
the substrate surface of the first conductive type is also provided with a polycrystalline silicon grid structure, the polycrystalline silicon grid structure comprises a grid dielectric layer, a polycrystalline silicon grid, metal silicide above the polycrystalline silicon grid and grid side walls, the grid dielectric layer is positioned on the substrate surface and isolates the polycrystalline silicon grid from the substrate, and the side walls are positioned on two sides of the polycrystalline silicon grid;
the polycrystalline silicon gate structure is positioned on the surface of the substrate between the body region of the first conduction type and the drift region of the second conduction type and is overlapped with the body region and the drift region on the two sides of the polycrystalline silicon gate structure;
the body region of the first conduction type also comprises a heavily doped first conduction type doped region and a heavily doped second conduction type doped region; a metal silicide is arranged above the first conductive type doped region and the second conductive type doped region;
the drift region of the second conduction type is also provided with a heavily doped second conduction type doping region and a metal silicide positioned above the second conduction type doping region;
the method is characterized in that: the surface of the drift region of the second conduction type is also provided with an isolation silicon oxide layer, one side of the isolation silicon oxide layer extends to the lower part of the polysilicon gate structure to be connected with the gate dielectric layer, and the other side of the isolation silicon oxide layer is aligned with the nearest side of the second conduction type doped region in the drift region of the second conduction type;
and a metal silicification reaction blocking silicon oxide layer is arranged above the isolation silicon oxide layer.
13. The LDMOS device set forth in claim 12 wherein: the surface of the substrate is also provided with an insulating medium layer and an interlayer medium; the interlayer dielectric is provided with a plurality of contact holes which are respectively contacted with the metal silicide in the body region, the metal silicide above the polysilicon grid, the metal silicification reaction blocking silicon oxide layer above the isolation silicon oxide layer and the surface of the metal silicide in the drift region, so that all structures are led out.
14. The LDMOS device of claim 13, wherein: the surface of the interlayer dielectric is also provided with a first metal layer, wherein the contact hole above the polysilicon gate structure is connected with the contact hole above the metal silicification reaction barrier silicon oxide layer through the first metal layer.
15. The LDMOS device set forth in claim 12 wherein: the thickness of the isolation silicon oxide layer is defined as the thickness of first field oxygen, and the sum of the thicknesses of the isolation silicon oxide layer and the metal silicidation reaction blocking silicon oxide layer is defined as the thickness of second field oxygen; the first field oxide and the polysilicon grid form a first field plate, and the second field oxide and the contact hole above the second field oxide form a second field plate.
16. The LDMOS device set forth in claim 15 wherein: the first field plate and the second field plate have different thicknesses, so that the LDMOS device has a better breakdown voltage-characteristic on-resistance relation.
17. The process for fabricating the LDMOS device of claim 12, wherein: comprises the following process steps:
step one, forming an isolation silicon oxide layer on the surface of a substrate of a first conduction type, and then injecting a body region of the first conduction type and a drift region of a second conduction type to form the body region and the drift region respectively;
forming a thermal oxidation layer, depositing a polycrystalline silicon layer, and etching to form a polycrystalline silicon grid and a grid dielectric layer; depositing an insulating medium layer and etching to form a grid side wall, and then carrying out ion implantation on the heavily doped first conductive type doped region and the heavily doped second conductive type doped region;
depositing a metal silicification reaction silicon oxide blocking layer and carrying out selective etching to expose the heavily doped first conductive type doping area and the heavily doped second conductive type doping area and the top of the polycrystalline silicon grid, reserving the metal silicification reaction silicon oxide blocking layer for isolating the surface of the silicon oxide layer, then carrying out metal silicification reaction, and forming metal silicide on the top of the polycrystalline silicon grid and above the first conductive type doping area and the second conductive type doping area; depositing an insulating medium layer and an interlayer medium layer;
and step four, etching the interlayer medium and the insulating medium layer to form a contact hole, filling and flattening, and depositing a first metal layer on the surface of the interlayer medium.
18. The process for fabricating an LDMOS device as set forth in claim 17, wherein: in the first step, the isolation silicon oxide layer is formed through silicon oxide layer deposition and selective etching process, and the isolation silicon oxide layer is located on the surface layer in the drift region.
19. The process for fabricating an LDMOS device as set forth in claim 17, wherein: in the second step, the heavily doped first conduction type doped region is used for leading out the body region of the first conduction type, and the heavily doped second conduction type doped region forms a source region and a drain region of the LDMOS device.
20. The process for fabricating an LDMOS device as set forth in claim 17, wherein: in the fourth step, when the contact holes are etched and filled, a plurality of rows of contact holes are formed above the metal silicification reaction barrier silicon oxide layer, and the plurality of rows of contact holes are in short circuit with the polysilicon gate through the first metal layer to form the second field plate.
21. The process for fabricating an LDMOS device as set forth in claim 20, wherein: the contact holes in multiple rows are in short circuit with an electrode led out from a source region or a body region of the LDMOS device through the first metal layer to form a second field plate.
22. The process for fabricating an LDMOS device as set forth in claim 20, wherein: the outer side of the metal silicification reaction barrier silicon oxide layer does not need to be completely aligned with the outer side of the isolation oxide layer; and a metal silicification reaction barrier silicon oxide layer is required to be arranged below the contact hole on the outermost side of the metal silicification reaction barrier silicon oxide layer.
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