CN104465404A - Manufacturing method of radio frequency LDMOS device - Google Patents
Manufacturing method of radio frequency LDMOS device Download PDFInfo
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- CN104465404A CN104465404A CN201410837468.6A CN201410837468A CN104465404A CN 104465404 A CN104465404 A CN 104465404A CN 201410837468 A CN201410837468 A CN 201410837468A CN 104465404 A CN104465404 A CN 104465404A
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- ldmos device
- polysilicon gate
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 73
- 229920005591 polysilicon Polymers 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 70
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 46
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 46
- 238000010168 coupling process Methods 0.000 claims abstract description 7
- 238000005859 coupling reaction Methods 0.000 claims abstract description 7
- 238000005516 engineering process Methods 0.000 claims abstract description 7
- 230000008878 coupling Effects 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 124
- 238000000034 method Methods 0.000 claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000428 dust Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract 1
- 230000006872 improvement Effects 0.000 description 13
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
Abstract
The invention discloses a manufacturing method of a radio frequency LDMOS device. The manufacturing method comprises the steps that after a trap P is formed in an epitaxial layer, a first gate dielectric layer grows; photoetching is carried out on the first gate dielectric layer so that the first gate dielectric layer can only cover a drift region; a second gate dielectric layer grows; a polysilicon gate is formed through the deposition and photoetching technology; a channel region, the drift region, a source region, a drain region and a P+ leading-out region are formed; a side wall is formed; a metal silicide barrier dielectric layer is deposited; repeated etching is carried out on the dielectric layers, and a metal silicide forming region is defined through self-alignment; metal silicification is carried out on the deposited metal. The metal silicide forming region of the device can be defined through self-alignment, and the coupling capacitance between a gate electrode and the drain electrode of the device can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, particularly relate to a kind of manufacture method of radio frequency LDMOS device.
Background technology
For promoting the radio-frequency performance of the radio frequency lateral fet (RF LDMOS) of more than puncture voltage 50V, need to reduce parasitic capacitance and resistance.
In existing technique, for reducing resistance, adopt the lamination of polysilicon and metal silicide; Metal silicide can deposit together with polysilicon, and as tungsten silicon, but its every square resistance is generally more than 5 ohm; Another kind is depositing metal, as titanium (Ti) or cobalt (Co) etc. can obtain the resistance of every square 2 ohm.
Because the grid width of RFLDMOS is below 0.5 micron, simultaneously for improving puncture voltage, the close drain terminal side of polysilicon gate is low-doped drift region, can not do low-resistance metal silication, like this due to the problem of alignment precision, be difficult to only to open the blocking layer of metal silicide of polysilicon gate and retain the barrier layer of drift region, also namely due to the reason of alignment precision, when definition is opened to the blocking layer of metal silicide at polysilicon gate top, the region of opening can not just in time at polysilicon gate top, the region of opening can to the lateral offset of polysilicon gate, when the close drain terminal side being displaced to polysilicon gate is outside, the barrier layer at top, drift region also can be opened, thus also can form metal silicide at top, drift region, and to form metal silicide and drift region be that the withstand voltage requirement of low-doped high resistance and height is not inconsistent to top, drift region.Therefore in existing technique, can not directly adopt photoetching process to open polysilicon gate top to form metal silicide.
In order to open the polysilicon gate top of RFLDMOS device to form metal silicide, in existing a kind of process be, adopt BARC antireflecting coating (Bottom Anti Reflective coating, BARC) carving technology is returned, utilize the flowable of BARC and the difference of height of grid, namely the thickness formed at polysilicon gate top after forming BARC is thin, the thickness of polysilicon gate outside is thick, only the region at polysilicon gate top can be exposed after returning quarter so comprehensively, the region of polysilicon gate outside is still protected by dielectric layer, namely the blocking layer of metal silicide on polysilicon gate can be removed by Alignment Method, and then open other region needing metal silication, finally carry out metal silication.Existing this method autoregistration can define the metal silicide forming region at polysilicon gate top, but also needs the extra photoetching process of employing one step to define the region of the formation metal silicide in source region and drain region.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of radio frequency LDMOS device, and energy autoregistration defines the metal silicide forming region of device, can also reduce the coupling capacitance between the grid of device and drain electrode.
For solving the problems of the technologies described above, the manufacture method of radio frequency LDMOS device provided by the invention comprises the steps:
Step one, formation surface of silicon form epitaxial loayer, form P trap, grow the first gate dielectric layer afterwards in epitaxial loayer.
The described first grid dielectric layer of the described first grid dielectric layer outside the forming region of step 2, employing lithographic etch process removal drift region, the forming region of described drift region retains.
Step 3, grow the second gate dielectric layer, the thickness of described second gate dielectric layer is less than the thickness of described first grid dielectric layer.
Step 4, depositing polysilicon carry out chemical wet etching to this polysilicon and form polysilicon gate, superposed the grid structure forming radio frequency LDMOS device by the described second gate dielectric layer bottom described polysilicon gate and its; Second side of described polysilicon gate extends to above described second gate dielectric layer.
Step 5, carry out first time P type ion implantation formed channel region, the first side autoregistration of described channel region and described polysilicon gate; Carry out second time N-type ion implantation and form drift region, the second side autoregistration of described drift region and described polysilicon gate; Carry out third time N-type source and drain ion implantation and form source region and drain region, described source region be arranged in described channel region and and the first side autoregistration of described polysilicon gate, described drain region be in described drift region and and the second side autoregistration of described second gate dielectric layer; Carry out the 4th P type ion implantation and form P+ draw-out area, described P+ draw-out area be arranged in described channel region and and described source contact, for described channel region is drawn; Thermal annealing is adopted to activate described channel region, described drift region, described source region, described drain region and described P+ draw-out area and advance, after thermal annealing, described channel region and described drift region extend to the bottom of described polysilicon gate respectively from both sides, the surface, described channel region that covers by described polysilicon gate for the formation of raceway groove.
Step 6, employing deposit and time carving technology form side wall in the side of described polysilicon gate.
Step 7, depositing metal silicide block media layer.
Step 8, carry out back carving to the described metal silicide block media layer in described radio frequency LDMOS device region and described second gate dielectric layer, polysilicon gate top described in Hui Kehou, the side wall of described polysilicon gate first side silicon that is outside and described first grid dielectric layer second lateral outer exposes, the thickness requirement of the described first grid dielectric layer of deposit described in step one ensures to still have after time quarter of step 6 and time quarter of step 8 remain with certain thickness and covered described drift region, thus autoregistration defines the forming region of metal silicide, the forming region of described metal silicide is the region that silicon exposes.
Step 9, depositing metal, the forming region of carrying out the described metal silicide that metal silication defines in autoregistration forms described metal silicide.
Further improvement is, the material of described first grid dielectric layer is oxide layer.
Further improvement is, the thickness of described first grid dielectric layer is meeting and under autoregistration defines the condition of the forming region of described metal silicide, can reduce the grid of described radio frequency LDMOS device and the coupling capacitance of drain electrode by the thickness increasing described first grid dielectric layer.
Further improvement is, the thickness of described first grid dielectric layer is 300 dust to 800 dusts.
Further improvement is, the material of described second gate dielectric layer is oxide layer.
Further improvement is, the side wall medium layer thickness forming the deposit of described side wall time institute in step 6 is 400 dust to 600 dusts.
Further improvement is, the side wall medium layer forming the deposit of described side wall time institute in step 6 is made up of the silica superposed and silicon nitride successively.
Further improvement is, the requirement at quarter of returning when forming described side wall in step 6 is less than 100 dusts to the loss amount of described first grid dielectric layer.
Further improvement is, in step 7, the material of the described metal silicide block media layer of institute's deposit is silica,
Further improvement is, the thickness of described metal silicide block media layer is 300 dust to 700 dusts.
Further improvement is, in step 4, the thickness of the described polysilicon of institute's deposit is 2500 dust to 3500 dusts.
Further improvement is, the metal of step 9 institute deposit is tungsten, titanium, cobalt.
Further improvement also comprises the steps: after step 9
Step 10, formation faraday shield layer, cover on the ledge structure at the second side place of described polysilicon gate, and between described faraday shield layer and the described polysilicon gate bottom it, isolation has shielding dielectric layer;
Step 11, carry out deep etching, described deep trouth is through described source region, described channel region and described epitaxial loayer and enter into described silicon substrate; In described deep trouth, fill metal form described dark contact hole, described dark contact hole is by described source region, described channel region, described epitaxial loayer and the electrical connection of described silicon substrate;
Step 12, formation interlayer film, contact hole and front metal layer pattern.
The present invention has following beneficial effect:
1, the present invention covers the surface, drift region of radio frequency LDMOS device by forming first grid dielectric layer, utilize first grid dielectric layer to the protection of drift region, can carry out returning the forming region of carving and defining metal silicide simultaneously, so the present invention can realize the metal silicide forming region that autoregistration defines device in radio frequency LDMOS device region comprehensively; Because autoregistration definition does not need to adopt photoetching process, so cost is low, and can also eliminate the registration problems that photoetching process brings, the size of device can be accomplished less.
2, the present invention covers surface, drift region by first grid dielectric layer, and the thickness of first grid dielectric layer is greater than the thickness of second dielectric layer, can make to isolate thicker dielectric layer between polysilicon gate and drift region, so the parasitic capacitance between grid and drain electrode can be lower, so the present invention can also reduce the coupling capacitance between the grid of device and drain electrode, this electric capacity is the direct-coupling of input and output, and reducing this electric capacity radio frequency performance has very large lifting; After after the second lateral ends i.e. gate dielectric layer thickness of close drain terminal of polysilicon gate increases, namely the thickness of first grid dielectric layer is set to be greater than the thickness of second dielectric layer simultaneously, the longitudinal electric field of drain terminal can be reduced, there is lifting to the robustness of device, have inhibitory action to hot carrier in jection (HCI).
3, radio frequency LDMOS device of the present invention generally needs and other MOS device integrates formation, so the MOS device that first grid dielectric layer can have thick gate medium with other is formed simultaneously, so in actual fabrication process, first grid dielectric layer and existing thick gate medium are formed simultaneously, deposit and the lithographic etch process of formation can not be increased, so the present invention can realize when not increasing reticle, realize the autoregistration definition of the metal silicide forming region of radio frequency LDMOS device.
4, the metal silication of source of the present invention is the side wall of the i.e. autoregistration polysilicon gate of self-aligning grid, can reduce the ON resistance of device further, and increase the saturation current of device.
5, due to channel region be the grid side of autoregistration source and the first side of autoregistration polysilicon gate inject and pick into, under being positioned at polysilicon gate, the doping content of channel region, one side, close drain region is lower, increases the gate dielectric layer thickness leaked and namely adopts thicker first grid dielectric layer not affect threshold voltage.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the manufacture method flow chart of embodiment of the present invention radio frequency LDMOS device;
Fig. 2 A-Fig. 2 I is device architecture schematic diagram in each step of manufacture method of embodiment of the present invention radio frequency LDMOS device.
Embodiment
As shown in Figure 1, be the manufacture method flow chart of embodiment of the present invention radio frequency LDMOS device; As shown in Fig. 2 A to Fig. 2 I, it is device architecture schematic diagram in each step of manufacture method of embodiment of the present invention radio frequency LDMOS device; The manufacture method of embodiment of the present invention radio frequency LDMOS device comprises the steps:
Step one, as shown in Figure 2 A, forms silicon substrate 1 surface and forms epitaxial loayer 2, form P trap 3, grow the first gate dielectric layer 4 afterwards in epitaxial loayer 2.In embodiments of the present invention, described silicon substrate 1 is the heavy doping of P type, and described epitaxial loayer 2 is P type light dope, and described epitaxial loayer 2 can be superposed by epitaxial layer and be formed.
The material of described first grid dielectric layer 4 is oxide layer.The thickness requirement of the described first grid dielectric layer 4 of described deposit ensures to still have after time quarter of subsequent step six and time quarter of step 8 remain with certain thickness and covered drift region 8, thus autoregistration defines the forming region of metal silicide 13.In addition, the thickness of described first grid dielectric layer 4 is meeting and under autoregistration defines the condition of the forming region of described metal silicide 13, can reduce the grid of described radio frequency LDMOS device and the coupling capacitance of drain electrode by the thickness increasing described first grid dielectric layer 4.
Be preferably, the thickness of described first grid dielectric layer 4 is 300 dust to 800 dusts, and the representative value of the thickness of described first grid dielectric layer 4 is 550 dusts.
Embodiment of the present invention radio frequency LDMOS device can be integrated on silicon substrate 1 described in same a slice with other MOS device, at this moment, described first grid dielectric layer 4 can adopt the gate dielectric layer of the MOS device of this thickness as other, also namely both can be formed simultaneously, so the described first grid dielectric layer 4 that the embodiment of the present invention is formed in radio frequency LDMOS device region does not need increase new depositing step and increase the light shield formed, also namely to adopt and gate dielectric layer deposit that other MOS device of integrating of radio frequency LDMOS device is original and photoetching process can be formed.
Step 2, as shown in Figure 2 B, adopts lithographic etch process to remove described first grid dielectric layer 4 outside the forming region of drift region 8, the described first grid dielectric layer 4 of forming region of described drift region 8 retains.
Step 3, as shown in Figure 2 C, grow the second gate dielectric layer 5, the thickness of described second gate dielectric layer 5 is less than the thickness of described first grid dielectric layer 4.The material of described second gate dielectric layer 5 is oxide layer.Described second gate dielectric layer 5 is the required gate dielectric layer of embodiment of the present invention radio frequency LDMOS device itself.
Step 4, as shown in Figure 2 D, depositing polysilicon 6 also carries out chemical wet etching to this polysilicon 6 and forms polysilicon gate 6, superposes by described polysilicon gate 6 and the described second gate dielectric layer 5 bottom it grid structure forming radio frequency LDMOS device; Second side of described polysilicon gate 6 extends to above described second gate dielectric layer 5.
Be preferably, the thickness of the described polysilicon 6 of institute's deposit is 2500 dust to 3500 dusts.
Step 5, as shown in Figure 2 D, carries out first time P type ion implantation and forms channel region 7, the first side autoregistration of described channel region 7 and described polysilicon gate 6; Carry out second time N-type ion implantation and form drift region 8, the second side autoregistration of described drift region 8 and described polysilicon gate 6; Carry out third time N-type source and drain ion implantation formation N-type heavily doped source region 9a and drain region 9b, described source region 9a be arranged in described channel region 7 and and the first side autoregistration of described polysilicon gate 6, described drain region 9b be in described drift region 8 and and the second side autoregistration of described second gate dielectric layer 5; Carry out the 4th P type ion implantation and form P+ draw-out area 10, described P+ draw-out area 10 is arranged in described channel region 7 and contacts with described source region 9a, for being drawn described channel region 7; Thermal annealing is adopted to activate described channel region 7, described drift region 8, described source region 9a, described drain region 9b and described P+ draw-out area 10 and advance, after thermal annealing, described channel region 7 and described drift region 8 extend to the bottom of described polysilicon gate 6 respectively from both sides, the surface, described channel region 7 that covers by described polysilicon gate 6 for the formation of raceway groove.
Step 6, as shown in Figure 2 E, adopts deposit and returns carving technology and form side wall 11 in the side of described polysilicon gate 6.
Be preferably, the side wall medium layer forming the deposit of described side wall 11 time institute is made up of the silica 11a superposed and silicon nitride 11b successively.Side wall 11 thickness of dielectric layers forming the deposit of described side wall 11 time institute is 400 dust to 600 dusts.
Requirement at quarter of returning when forming described side wall 11 is less than 100 dusts to the loss amount of described first grid dielectric layer 4, and described first grid dielectric layer 4 loss amount can be made so lower.
Step 7, as shown in Figure 2 F, depositing metal silicide 13 block media layer 12.
Be preferably, the material of described metal silicide 13 block media layer 12 is silica, and thickness is 300 dust to 700 dusts.
Step 8, as shown in Figure 2 G, carry out back carving to the described metal silicide 13 block media layer 12 in described radio frequency LDMOS device region and described second gate dielectric layer 5, polysilicon gate 6 top described in Hui Kehou, the side wall 11 of described polysilicon gate 6 first side silicon that is outside and described first grid dielectric layer 4 second lateral outer exposes, also the thickness namely returning quarter be greater than the thickness that equals described metal silicide 13 block media layer 12 and described second gate dielectric layer 5 and, polysilicon gate 6 top described in such guarantee, the side wall 11 of described polysilicon gate 6 first side silicon that is outside and described first grid dielectric layer 4 second lateral outer exposes.
The thickness requirement of the described first grid dielectric layer 4 of deposit described in step one ensures to still have after time quarter of step 6 and time quarter of step 8 remain with certain thickness and covered described drift region 8, thus autoregistration defines the forming region of metal silicide 13, the forming region of described metal silicide 13 is the region that silicon exposes; Namely time quarter of step 8 is inexcessive yet, and after returning quarter, described first grid dielectric layer 4 still has and remains with certain thickness and covered described drift region 8 yet.
Step 9, as illustrated in figure 2h, depositing metal, the forming region of carrying out the described metal silicide 13 that metal silication defines in autoregistration forms described metal silicide 13.The metal being preferably institute's deposit is tungsten, titanium, cobalt.
Step 10, as shown in figure 2i, adopt deposit to add lithographic etch process and form faraday shield layer 15, cover on the ledge structure at the second side place of described polysilicon gate 6, between described faraday shield layer 15 and the described polysilicon gate 6 bottom it, isolation has shielding dielectric layer 14;
Step 11, carry out deep etching, described deep trouth is through described source region 9a, described channel region 7 and described epitaxial loayer 2 and enter into described silicon substrate 1; In described deep trouth, fill metal form described dark contact hole, described source region 9a, described channel region 7, described epitaxial loayer 2 and described silicon substrate 1 are electrically connected by described dark contact hole;
Step 12, formation interlayer film, contact hole and front metal layer pattern.Wherein said contact hole can contact with the described polysilicon gate 6 of bottom, described source region 9a and described P+ draw-out area 10 and described drain region 9b through described interlayer film, the top of described contact hole contacts with described front metal layer, and described front metal layer draws source electrode, the drain and gate of device respectively.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (13)
1. a manufacture method for radio frequency LDMOS device, is characterized in that, comprises the steps:
Step one, formation surface of silicon form epitaxial loayer, form P trap, grow the first gate dielectric layer afterwards in epitaxial loayer;
The described first grid dielectric layer of the described first grid dielectric layer outside the forming region of step 2, employing lithographic etch process removal drift region, the forming region of described drift region retains;
Step 3, grow the second gate dielectric layer, the thickness of described second gate dielectric layer is less than the thickness of described first grid dielectric layer;
Step 4, depositing polysilicon carry out chemical wet etching to this polysilicon and form polysilicon gate, superposed the grid structure forming radio frequency LDMOS device by the described second gate dielectric layer bottom described polysilicon gate and its; Second side of described polysilicon gate extends to above described second gate dielectric layer;
Step 5, carry out first time P type ion implantation formed channel region, the first side autoregistration of described channel region and described polysilicon gate; Carry out second time N-type ion implantation and form drift region, the second side autoregistration of described drift region and described polysilicon gate; Carry out third time N-type source and drain ion implantation and form source region and drain region, described source region be arranged in described channel region and and the first side autoregistration of described polysilicon gate, described drain region be in described drift region and and the second side autoregistration of described second gate dielectric layer; Carry out the 4th P type ion implantation and form P+ draw-out area, described P+ draw-out area be arranged in described channel region and and described source contact, for described channel region is drawn; Thermal annealing is adopted to activate described channel region, described drift region, described source region, described drain region and described P+ draw-out area and advance, after thermal annealing, described channel region and described drift region extend to the bottom of described polysilicon gate respectively from both sides, the surface, described channel region that covers by described polysilicon gate for the formation of raceway groove;
Step 6, employing deposit and time carving technology form side wall in the side of described polysilicon gate;
Step 7, depositing metal silicide block media layer;
Step 8, carry out back carving to the described metal silicide block media layer in described radio frequency LDMOS device region and described second gate dielectric layer, polysilicon gate top described in Hui Kehou, the side wall of described polysilicon gate first side silicon that is outside and described first grid dielectric layer second lateral outer exposes, the thickness requirement of the described first grid dielectric layer of deposit described in step one ensures to still have after time quarter of step 6 and time quarter of step 8 remain with certain thickness and covered described drift region, thus autoregistration defines the forming region of metal silicide, the forming region of described metal silicide is the region that silicon exposes,
Step 9, depositing metal, the forming region of carrying out the described metal silicide that metal silication defines in autoregistration forms described metal silicide.
2. the manufacture method of radio frequency LDMOS device as claimed in claim 1, is characterized in that: the material of described first grid dielectric layer is oxide layer.
3. the manufacture method of radio frequency LDMOS device as claimed in claim 1 or 2, it is characterized in that: the thickness of described first grid dielectric layer is meeting and under autoregistration defines the condition of the forming region of described metal silicide, can reduce the grid of described radio frequency LDMOS device and the coupling capacitance of drain electrode by the thickness increasing described first grid dielectric layer.
4. the manufacture method of radio frequency LDMOS device as claimed in claim 1 or 2, is characterized in that: the thickness of described first grid dielectric layer is 300 dust to 800 dusts.
5. the manufacture method of radio frequency LDMOS device as claimed in claim 1, is characterized in that: the material of described second gate dielectric layer is oxide layer.
6. the manufacture method of radio frequency LDMOS device as claimed in claim 1, is characterized in that: the side wall medium layer thickness forming the deposit of described side wall time institute in step 6 is 400 dust to 600 dusts.
7. the manufacture method of radio frequency LDMOS device as claimed in claim 1, is characterized in that: the side wall medium layer forming the deposit of described side wall time institute in step 6 is made up of the silica superposed and silicon nitride successively.
8. the manufacture method of radio frequency LDMOS device as claimed in claim 1, is characterized in that: the requirement at quarter of returning when forming described side wall in step 6 is less than 100 dusts to the loss amount of described first grid dielectric layer.
9. the manufacture method of radio frequency LDMOS device as claimed in claim 1, is characterized in that: in step 7, the material of the described metal silicide block media layer of institute's deposit is silica.
10. the manufacture method of the radio frequency LDMOS device as described in claim 1 or 9, is characterized in that: the thickness of described metal silicide block media layer is 300 dust to 700 dusts.
The manufacture method of 11. radio frequency LDMOS device as claimed in claim 1, is characterized in that: in step 4, the thickness of the described polysilicon of institute's deposit is 2500 dust to 3500 dusts.
The manufacture method of 12. radio frequency LDMOS device as claimed in claim 1, is characterized in that: the metal of step 9 institute deposit is tungsten, titanium, cobalt.
The manufacture method of 13. radio frequency LDMOS device as claimed in claim 1, is characterized in that: also comprise the steps: after step 9
Step 10, formation faraday shield layer, cover on the ledge structure at the second side place of described polysilicon gate, and between described faraday shield layer and the described polysilicon gate bottom it, isolation has shielding dielectric layer;
Step 11, carry out deep etching, described deep trouth is through described source region, described channel region and described epitaxial loayer and enter into described silicon substrate; In described deep trouth, fill metal form described dark contact hole, described dark contact hole is by described source region, described channel region, described epitaxial loayer and the electrical connection of described silicon substrate;
Step 12, formation interlayer film, contact hole and front metal layer pattern.
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| CN108039371A (en) * | 2017-12-01 | 2018-05-15 | 德淮半导体有限公司 | LDMOS transistor and its manufacture method |
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| CN111092123A (en) * | 2019-12-10 | 2020-05-01 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
| CN112216745A (en) * | 2020-12-10 | 2021-01-12 | 北京芯可鉴科技有限公司 | High-voltage asymmetric LDMOS device and preparation method thereof |
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