CN104241358A - Radio frequency ldmos device and manufacturing method thereof - Google Patents
Radio frequency ldmos device and manufacturing method thereof Download PDFInfo
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- CN104241358A CN104241358A CN201310244707.2A CN201310244707A CN104241358A CN 104241358 A CN104241358 A CN 104241358A CN 201310244707 A CN201310244707 A CN 201310244707A CN 104241358 A CN104241358 A CN 104241358A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 103
- 239000010703 silicon Substances 0.000 claims description 103
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 100
- 238000000407 epitaxy Methods 0.000 claims description 72
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 72
- 229920005591 polysilicon Polymers 0.000 claims description 70
- 150000002500 ions Chemical class 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 28
- 238000002347 injection Methods 0.000 claims description 27
- 239000007924 injection Substances 0.000 claims description 27
- 238000005516 engineering process Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 230000003071 parasitic effect Effects 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses a radio frequency LDMOS device. A buried layer is contained in a drift region, wherein the doping type of the drift region and the doping type of the buried layer are opposite. The buried layer is surrounded by the drift region and a drain region. The buried layer and a channel region are spaced at a certain distance. The doping concentration of the buried layer and the doping concentration of the drift region meet the requirement that when the working voltage is applied to the drain region, the buried layer and the drift region are exhausted completely. Under the condition that when the working voltage is applied to the drain region, the buried layer and the drift region are exhausted completely, the higher the doping concentration of the drain region is, the smaller the source-drain on-resistance of the radio frequency LDMOS device is. When the working voltage is applied to the drain region, the larger the completely exhausted region formed in the buried layer and the drift region is, the smaller the source-drain stray capacitance of the radio frequency LDMOS device is. The invention further discloses a manufacturing method of the radio frequency LDMOS device. By the adoption of the radio frequency LDMOS device, the source-drain on-resistance and the source-drain stray capacitance of the radio frequency LEDMOS device can be reduced at the same time, and the performance of the device is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of radio frequency LDMOS device; The invention still further relates to a kind of manufacture method of radio frequency LDMOS device.
Background technology
Radio frequency lateral fet (RF LDMOS) is the conventional device being applied to radio-frequency (RF) base station and broadcasting station.High-breakdown-voltage, low source and drain conducting resistance (RDSON) and low source and drain parasitic capacitance (Coss) are the prerequisite device properties of RF LDMOS.In order to reduce the parasitic capacitance between source region and raceway groove, substrate most possibly, usually adopt heavily doped backing material to add lightly doped epitaxial loayer, and utilize the dark contact hole of tungsten to connect source region, raceway groove, epitaxial loayer and substrate.As shown in Figure 1, be the structural representation of existing radio frequency LDMOS device, for N-type device, existing radio frequency LDMOS device comprises: the silicon substrate 101 of the heavy doping of P type and P+ doping, the doping content of silicon substrate 101 is greater than 1e20cm
-3; The lightly doped silicon epitaxy layer 102 of P type, the doping content of silicon epitaxy layer 102 and thickness depend on the drain terminal operating voltage of device, and drain terminal operating voltage is higher, silicon epitaxy layer 102 adulterate lower, thickness is thicker; N-type drift region 103, is formed in silicon epitaxy layer 102; P type doping channel region 104, channel region 104 and drift region 103 adjacent in the horizontal; Gate dielectric layer 107 and polysilicon gate 108; The source region 105 of N-type heavy doping and N+ doping, drain region 106; In source region 105, the surface of drain region 106 and polysilicon gate 108 is formed with metal silicide 112; Shielding dielectric layer 109 and faraday shield layer 110, on the side covering the drain terminal of polysilicon gate 108 and end face; Dark contact hole 111, be made up of the metal be filled in deep trouth such as tungsten, deep trouth passes source region 105, channel region 104 and silicon epitaxy layer 102 and enters into silicon substrate 101, and source region 105, channel region 104, silicon epitaxy layer 102 and silicon substrate 101 are electrically connected by dark contact hole 111.
When hyperfrequency is applied, the requirement of RDSON and Coss of radio frequency LDMOS device is higher.When wanting RDSON to keep lower, need the doping content improving drift region 103 as far as possible, but when this may cause drain region 106 end to add high pressure, drift region 103 can not fully-depleted and cause puncture voltage to decline.The principal element restricting Coss decline is in addition the junction capacitance of drift region 103 to silicon substrate 101, as drift region 103 concentration improves, also can increase this junction capacitance, be unfavorable for the decline of Coss equally.Therefore, RDSON and Coss two parameters restrict mutually, and the concentration of existing device architecture not by increasing drift region makes both all reduce, so the device property of existing radio frequency LDMOS is difficult to reach excellent properties simultaneously.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of radio frequency LDMOS device, can reduce source and drain conducting resistance and the source and drain parasitic capacitance of device simultaneously, improves the performance of device.For this reason, the present invention also provides a kind of manufacture method of radio frequency LDMOS device.
For solving the problems of the technologies described above, radio frequency LDMOS device provided by the invention comprises:
The heavily doped silicon substrate of first conduction type.
The silicon epitaxy layer of the first conduction type doping, this silicon epitaxy layer is formed in described surface of silicon.
Drift region, is made up of the second conductive type ion injection region be formed in the selection area of described silicon epitaxy layer, and the degree of depth of equal with the top surface of described silicon epitaxy layer, the described drift region of top surface of described drift region is less than the thickness of described silicon epitaxy layer.
Channel region, be made up of the first conductive type ion injection region be formed in the selection area of described silicon epitaxy layer, described channel region and described drift region adjacent in the horizontal, the degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than or equal to the degree of depth of described drift region.
Polysilicon gate, be formed at above described channel region, described polysilicon gate and described silicon epitaxy zone isolation have gate dielectric layer, and channel region described in described polysilicon gate cover part also extends to above described drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove.
Source region, is made up of the second conduction type heavily doped region be formed in described channel region, the first side autoregistration of described source region and described polysilicon gate.
Drain region, is made up of the second conduction type heavily doped region be formed in described drift region, and the second side of described drain region and described polysilicon gate is separated by a lateral separation.
Faraday shield layer, covers on the side of the second side of described polysilicon gate and end face and between described faraday shield layer and described polysilicon gate, isolation has shielding dielectric layer.
Dark contact hole, be made up of the metal be filled in deep trouth, described deep trouth passes described source region, described channel region and described silicon epitaxy layer and enters into described silicon substrate, and described dark contact hole is by described source region, described channel region, described silicon epitaxy layer and the electrical connection of described silicon substrate.
The buried regions of the first conduction type doping, described buried regions is arranged in described drift region and is surrounded by described drift region and described drain region, the isolated segment distance of described buried regions and described channel region, the doping content of described buried regions and described drift region meets described buried regions and described drift region when to add operating voltage in described drain region and exhausts completely; Meeting when described drain region adds operating voltage under the complete depletion conditions of described buried regions and described drift region, the doping content of described drift region is higher, and the source and drain conducting resistance of radio frequency LDMOS device is less; The complete depleted region that when adding operating voltage in described drain region, described buried regions and described drift region are formed is larger, and the source and drain parasitic capacitance of described radio frequency LDMOS device is less.
Further improvement is, described buried regions and described drain region contact; Or described buried regions and described drain region do not contact.
Further improvement is, the degree of depth of described buried regions be the junction depth of described drift region 1/1 to two/3rd between.
Further improvement is, the second conductive type ion injection region of described drift region is injected to add after furnace anneal advances by second conductive type ion and formed; Or the second conductive type ion injection region of described drift region is connected to form by the ion implanted region repeatedly injecting the degree of depth different; Described buried regions is made up of the first conductive type ion injection region.
Further improvement is, described radio frequency LDMOS device is N-type device, and described first conduction type is P type, and described second conduction type is N-type; Or described radio frequency LDMOS device is P type device, and described first conduction type is N-type, and described second conduction type is P type.
For solving the problems of the technologies described above, the manufacture method of radio frequency LDMOS device provided by the invention comprises the steps:
Step one, the heavily doped surface of silicon Epitaxial growth of the first conduction type formed first conduction type doping silicon epitaxy layer.
Step 2, the second conductive type ion injection technology is adopted to form drift region in the selection area of described silicon epitaxy layer, the selection area forming described drift region is defined by photoetching process, and the degree of depth of equal with the top surface of described silicon epitaxy layer, the described drift region of top surface of described drift region is less than the thickness of described silicon epitaxy layer.
Step 3, adopt the first conductive type ion injection technology formed in described drift region first conduction type doping buried regions, described buried regions is surrounded by the drain region of described drift region and follow-up formation, the isolated segment distance in channel region of described buried regions and follow-up formation, the doping content of described buried regions and described drift region meets described buried regions and described drift region when to add operating voltage in described drain region and exhausts completely; Meeting when described drain region adds operating voltage under the complete depletion conditions of described buried regions and described drift region, the doping content of described drift region is higher, and the source and drain conducting resistance of radio frequency LDMOS device is less; The complete depleted region that when adding operating voltage in described drain region, described buried regions and described drift region are formed is larger, and the source and drain parasitic capacitance of described radio frequency LDMOS device is less.
Step 4, be formed with the described silicon epitaxy layer superficial growth gate dielectric layer of described buried regions.
Step 5, at described gate dielectric layer surface deposition polysilicon.
Step 6, employing lithographic etch process carry out etching to described polysilicon and form polysilicon gate, and described polysilicon gate is as the grid of described radio frequency LDMOS device; Second side of described polysilicon gate extends to above described drift region.
Step 7, in the selection area of described silicon epitaxy layer carry out first conductive type ion inject formed described channel region, the selection area forming described channel region is defined by photoetching process and the first side autoregistration of the selection area of described channel region and described polysilicon gate, annealing push away trap after described channel region and described drift region adjacent in the horizontal, the degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than or equal to the degree of depth of described drift region; The described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove.
Step 8, forming the described silicon substrate front deposition dielectric layer behind described channel region, described shielding dielectric layer covers the described silicon epitaxy layer surface outside the end face of described polysilicon gate and side surface and described polysilicon gate.
Step 9, at described shielding dielectric layer surface deposit faraday shield layer.
Step 10, dry etch process is adopted to etch described faraday shield layer, after etching on the described faraday shield layer side that covers the second side of described polysilicon gate and end face.
Step 11, the second conduction type heavy doping ion of carrying out are injected and are formed source region and drain region, the first side autoregistration of described source region and described polysilicon gate; Second side of described drain region and described polysilicon gate is separated by a lateral separation.
Step 12, depositing metal silicide annealed alloy, described metal silicide is formed at described source region, described drain region and not by described polycrystalline silicon gate surface that described faraday shield layer covers.
Step 13, carry out deep etching, described deep trouth is through described source region, described channel region and described silicon epitaxy layer and enter into described silicon substrate; In described deep trouth, fill metal form described dark contact hole, described dark contact hole is by described source region, described channel region, described silicon epitaxy layer and the electrical connection of described silicon substrate.
Further improvement is, described buried regions and described drain region contact; Or described buried regions and described drain region do not contact.
Further improvement is, the degree of depth of described buried regions be the junction depth of described drift region 1/1 to two/3rd between.
Further improvement is, the second conductive type ion injection technology of drift region described in step 2 is that primary ions is injected, and this primary ions is injected and added that furnace anneal advances the described drift region of formation; Or the second conductive type ion injection technology of described drift region is repeatedly the different ion implantation of Implantation Energy, the ion implanted region that repeatedly degree of depth that formed of ion implantation is different is directly connected to form after described drift region or ion implanted region furnace anneal that repeatedly degree of depth that formed of ion implantation is different advance and forms described drift region.
Further improvement is, described radio frequency LDMOS device is N-type device, and described first conduction type is P type, and described second conduction type is N-type, the N-type ion implantation technology condition of described drift region is: implanted dopant is phosphorus, and Implantation Energy scope is 20KeV to 500KeV; Or described radio frequency LDMOS device is P type device, and described first conduction type is N-type, and described second conduction type is P type, the P type ion implantation technology condition of described drift region is: implanted dopant is boron, and Implantation Energy scope is 10KeV to 300KeV.
The present invention to be surrounded by drift region and the doping type buried regions contrary with drift region completely by forming one in drift region, being provided with of buried regions helps improve exhausting of drift region, thus can realize in the doping content ensureing can improve under the condition that buried regions and drift region exhaust completely drift region as far as possible, thus the raising of the doping content of drift region can reduce the source and drain conducting resistance of device.Buried regions can make buried regions and drift region be formed complete depleted region after improving exhausting of drift region is maximum, exhausting completely of drift region can make the source and drain parasitic capacitance of device get minimum value, and source and drain parasitic capacitance can be reduced further, so the present invention can realize the reduction of source and drain parasitic capacitance by expanding complete depletion region scope.The present invention can realize reducing source and drain conducting resistance and source and drain parasitic capacitance simultaneously, and relative to existing device architecture, the present invention can the performance of optimised devices greatly.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing radio frequency LDMOS device;
Fig. 2 is the structural representation of embodiment of the present invention radio frequency LDMOS device;
Fig. 3 A-Fig. 3 K is the structural representation of radio frequency LDMOS device in each step of the embodiment of the present invention one method.
Embodiment
As shown in Figure 2, be the structural representation of the embodiment of the present invention one radio frequency LDMOS device; The embodiment of the present invention one radio frequency LDMOS device comprises:
The heavily doped silicon substrate 1 of first conduction type.The doping content of silicon substrate 1 is greater than 1e20cm
-3.
The silicon epitaxy layer 2 of the first conduction type doping, this silicon epitaxy layer 2 is formed at described silicon substrate 1 on the surface.The doping content of described silicon epitaxy layer 2 and thickness depend on the drain terminal operating voltage of device, and drain terminal operating voltage is higher, silicon epitaxy layer 2 adulterate lower, thickness is thicker; Be preferably, the doping content scope 5 × 10 of silicon epitaxy layer 2
14cm
-3to 2 × 10
15cm
-3.
Drift region 3, be made up of the second conductive type ion injection region be formed in the selection area of described silicon epitaxy layer 2, top surface and the degree of depth of equal, the described drift region 3 of the top surface of described silicon epitaxy layer 2 of described drift region 3 are less than the thickness of described silicon epitaxy layer 2.Second conductive type ion injection region of described drift region 3 is injected to add after furnace anneal advances by second conductive type ion and is formed; Or the second conductive type ion injection region of described drift region 3 is connected to form by the ion implanted region repeatedly injecting the degree of depth different.
Channel region 7, be made up of the first conductive type ion injection region be formed in the selection area of described silicon epitaxy layer 2, described channel region 7 and described drift region 3 adjacent in the horizontal, top surface and the degree of depth of equal, the described channel region 7 of the top surface of described silicon epitaxy layer 2 of described channel region 7 are less than or equal to the degree of depth of described drift region 3.
Polysilicon gate 6, is formed at above described channel region 7, and between described polysilicon gate 6 and described silicon epitaxy layer 2, isolation has gate dielectric layer 5.Be preferably, the material of gate dielectric layer 5 is silica.Channel region 7 described in described polysilicon gate 6 cover part also extends to above described drift region 3, and the surface, described channel region 7 covered by described polysilicon gate 6 is for the formation of raceway groove.
Source region 9, is made up of the second conduction type heavily doped region be formed in described channel region 7, the first side autoregistration of described source region 9 and described polysilicon gate 6.
Drain region 8, is made up of the second conduction type heavily doped region be formed in described drift region 3, and the second side of described drain region 8 and described polysilicon gate 6 is separated by a lateral separation.
Faraday shield layer 11, covers on the side of the second side of described polysilicon gate 6 and end face and between described faraday shield layer 11 and described polysilicon gate 6, isolation has shielding dielectric layer 10.Be preferably, the material of shielding dielectric layer 10 is silica.
In described source region 9, described drain region 8 and the front face surface of described polysilicon gate 6 that do not covered by described faraday shield layer 11 be all formed with metal silicide 12.
Dark contact hole 13, be made up of the metal be filled in deep trouth, described deep trouth passes described source region 9, described channel region 7 and described silicon epitaxy layer 2 and enters into described silicon substrate 1, and described source region 9, described channel region 7, described silicon epitaxy layer 2 and described silicon substrate 1 are electrically connected by described dark contact hole 13.Be preferably, dark contact hole 13 is made up of the tungsten be filled in deep trouth.
The buried regions 4 of the first conduction type doping, described buried regions 4 is arranged in described drift region 3 and is surrounded by described drift region 3 and described drain region 8, the isolated segment distance of described buried regions 4 and described channel region 7, the doping content of described buried regions 4 and described drift region 3 meets described buried regions 4 and described drift region 3 when to add operating voltage in described drain region 8 and exhausts completely, and the operating voltage in described drain region 8 is added by the drain electrode be formed on described drain region 8.Meeting when described drain region 8 adds operating voltage described buried regions 4 and described drift region 3 completely under depletion conditions, the doping content of described drift region 3 is higher, and the source and drain conducting resistance of radio frequency LDMOS device is less; The complete depleted region that when adding operating voltage in described drain region 8, described buried regions 4 and described drift region 3 are formed is larger, and the source and drain parasitic capacitance of described radio frequency LDMOS device is less.
Described buried regions 4 and described drain region 8 contact, at this moment there is overlapping region in described buried regions 4 and described drain region 8, the impurity of the described buried regions 4 in this overlapping region is all compensated by described drain region 8, and the doping type of the doping type i.e. described overlapping region identical with described drain region 8 of last described overlapping region is the second conduction type.In other embodiments, also can not contact for described buried regions and described drain region.
Described buried regions 4 is made up of the first conductive type ion injection region, the degree of depth of described buried regions 4 be the junction depth of described drift region 3 1/1 to two/3rd between.
Namely the structure of the embodiment of the present invention one radio frequency LDMOS device is applicable to N-type device, is also applicable to P type device.When the embodiment of the present invention one radio frequency LDMOS device is N-type device, described first conduction type is P type, and described second conduction type is N-type; Or when the embodiment of the present invention one radio frequency LDMOS device is P type device, described first conduction type is N-type, and described second conduction type is P type.
In the embodiment of the present invention, by implanting buried regions 4 in drift region 3, the conduction type of buried regions 4 is contrary with drift region 3, and buried regions 4 is positioned at drift region 3 body, and four periderm drift regions 3 surround, when drain terminal adds high pressure, whole drift region 3 exhausts, and middle buried regions 4 also exhausts simultaneously, and buried regions 4 helps its surrounding drift region 3 to exhaust, therefore the doping content of drift region 3 can also improve, to reduce conducting resistance under guarantee fully-depleted.Found by TCAD simulation, implant buried regions 4, RDSON and Coss can be made to decline 20% respectively, successful.
As shown in Fig. 3 A to Fig. 3 K, it is the structural representation of radio frequency LDMOS device in each step of the embodiment of the present invention one method.For solving the problems of the technologies described above, the manufacture method of the embodiment of the present invention one radio frequency LDMOS device comprises the steps:
Step one, as shown in Figure 3A, the heavily doped silicon substrate 1 of the first conduction type on the surface epitaxial growth form the silicon epitaxy layer 2 of the first conduction type doping.The doping content of described silicon substrate 1 is greater than 1e20cm
-3.The doping content of described silicon epitaxy layer 2 and thickness depend on the drain terminal operating voltage of device, and drain terminal operating voltage is higher, silicon epitaxy layer 2 adulterate lower, thickness is thicker.Be preferably, the doping content scope 5 × 10 of silicon epitaxy layer 2
14cm
-3to 2 × 10
15cm
-3.
Step 2, as shown in Figure 3 B, the second conductive type ion injection technology is adopted to form drift region 3 in the selection area of described silicon epitaxy layer 2, the selection area forming described drift region 3 is defined by photoetching process, and top surface and the degree of depth of equal, the described drift region 3 of the top surface of described silicon epitaxy layer 2 of described drift region 3 are less than the thickness of described silicon epitaxy layer 2.
Second conductive type ion injection technology of described drift region 3 is that primary ions is injected, and this primary ions is injected and added that furnace anneal advances the described drift region 3 of formation.Or, second conductive type ion injection technology of described drift region 3 is repeatedly the different ion implantation of Implantation Energy, and the ion implanted region that repeatedly degree of depth that formed of ion implantation is different is directly connected to form after described drift region 3 or ion implanted region furnace anneal that repeatedly degree of depth that formed of ion implantation is different advance and forms described drift region 3.
Step 3, as shown in Figure 3 C, adopt the first conductive type ion injection technology in described drift region 3, form the buried regions 4 of the first conduction type doping, described buried regions 4 is surrounded by the drain region 8 of described drift region 3 and follow-up formation, the isolated segment distance in channel region 7 of described buried regions 4 and follow-up formation.The doping content of described buried regions 4 and described drift region 3 meets described buried regions 4 and described drift region 3 when to add operating voltage in described drain region 8 and exhausts completely, and the operating voltage in described drain region 8 is added by the drain electrode be formed on described drain region 8.Meeting when described drain region 8 adds operating voltage described buried regions 4 and described drift region 3 completely under depletion conditions, the doping content of described drift region 3 is higher, and the source and drain conducting resistance of radio frequency LDMOS device is less; The complete depleted region that when adding operating voltage in described drain region 8, described buried regions 4 and described drift region 3 are formed is larger, and the source and drain parasitic capacitance of described radio frequency LDMOS device is less.
The degree of depth of described buried regions 4 be the junction depth of described drift region 3 1/1 to two/3rd between.
Step 4, as shown in Figure 3 D, be formed with the described silicon epitaxy layer 2 superficial growth gate dielectric layer 5 of described buried regions 4.The material being preferably gate dielectric layer 5 is silica, adopts thermal oxidation technology to be formed.
Step 5, as shown in FIGURE 3 E, at described gate dielectric layer 5 surface deposition polysilicon 6.Described polysilicon 6 is the second conduction type heavy doping, and the doping of described polysilicon 6 is by the doping in place during deposit or by carrying out comprehensive ion implantation doping after the deposit of described polysilicon 6 completes.
Step 6, as illustrated in Figure 3 F, adopt lithographic etch process to carry out etching formation polysilicon gate 6 to described polysilicon 6, described polysilicon gate 6 is as the grid of described radio frequency LDMOS device; Second side of described polysilicon gate 6 extends to above described drift region 3.
Step 7, as shown in Figure 3 G, first conductive type ion that carries out in the selection area of described silicon epitaxy layer 2 injects the described channel region 7 of formation, the photoetching offset plate figure 7a that the selection area forming described channel region 7 is formed by photoetching process defines and the first side autoregistration of the selection area of described channel region 7 and described polysilicon gate 6, annealing push away trap after described channel region 7 and described drift region 3 adjacent in the horizontal, top surface and the degree of depth of equal, the described channel region 7 of the top surface of described silicon epitaxy layer 2 of described channel region 7 are less than or equal to the degree of depth of described drift region 3; The surface, described channel region 7 covered by described polysilicon gate 6 is for the formation of raceway groove.
Step 8, as shown in fig. 31, forming the described silicon substrate 1 front deposition dielectric layer 10 behind described channel region 7, described shielding dielectric layer 10 covers described silicon epitaxy layer 2 surface outside the end face of described polysilicon gate 6 and side surface and described polysilicon gate 6.
Can select, the formation source region 9 in subsequent step 11 and the step in drain region 8 are formed before can being placed on described shielding dielectric layer 10 depositing technics.As shown in figure 3h, carry out the second conduction type heavy doping ion and inject formation source region 9 and drain region 8, the first side autoregistration of described source region 9 and described polysilicon gate 6; Second side of described drain region 8 and described polysilicon gate 6 is separated by a lateral separation.
Step 9, as shown in figure 3j, at described shielding dielectric layer 10 surface deposition faraday shield layer 11.
Step 10, as shown in figure 3j, adopts dry etch process to etch described faraday shield layer 11, on the side that after etching, described faraday shield layer 11 covers the second side of described polysilicon gate 6 and end face.
Step 11, when not carrying out the ion implantation in source region 9 and drain region 8 in step 8, now can complete the ion implantation in source region 9 and drain region 8: as shown in Fig. 3 K, carry out the second conduction type heavy doping ion and inject formation source region 9 and drain region 8, the first side autoregistration of described source region 9 and described polysilicon gate 6; Second side of described drain region 8 and described polysilicon gate 6 is separated by a lateral separation.
Buried regions 4 described in the embodiment of the present invention and described drain region 8 contact, at this moment there is overlapping region in described buried regions 4 and described drain region 8, the impurity of the described buried regions 4 in this overlapping region is all compensated by described drain region 8, and the doping type of the doping type i.e. described overlapping region identical with described drain region 8 of last described overlapping region is the second conduction type.In other embodiments, also can not contact for described buried regions and described drain region.
Step 12, as shown in Fig. 3 K, depositing metal silicide 12 annealed alloy, described metal silicide 12 is formed at described source region 9, described drain region 8 and not by described polysilicon gate 6 surface that described faraday shield layer 11 covers.
Step 13, as shown in Figure 2, carry out deep etching, described deep trouth is through described source region 9, described channel region 7 and described silicon epitaxy layer 2 and enter into described silicon substrate 1; In described deep trouth, fill metal form described dark contact hole 13, described source region 9, described channel region 7, described silicon epitaxy layer 2 and described silicon substrate 1 are electrically connected by described dark contact hole 13.
Follow-up conventional later process can be carried out afterwards.
In the embodiment of the present invention one method, described radio frequency LDMOS device can be N-type device or P type device, and when the radio frequency LDMOS device that the embodiment of the present invention one method is formed is N-type device, described first conduction type is P type, and described second conduction type is N-type; Now the N-type ion implantation technology condition of drift region described in step 2 is: implanted dopant is phosphorus, and Implantation Energy scope is 20KeV to 500KeV; When adopting described furnace anneal, described furnace anneal temperature range is 800 DEG C to 1200 DEG C.
When the radio frequency LDMOS device that the embodiment of the present invention one method is formed is P type device, described first conduction type is N-type, and described second conduction type is P type; Now the P type ion implantation technology condition of drift region described in step 2 is: the P type ion implantation technology condition of described drift region is: implanted dopant is boron, and Implantation Energy scope is 10KeV to 300KeV; When adopting described furnace anneal, described furnace anneal temperature range is 800 DEG C to 1200 DEG C.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a radio frequency LDMOS device, is characterized in that, comprising:
The heavily doped silicon substrate of first conduction type;
The silicon epitaxy layer of the first conduction type doping, this silicon epitaxy layer is formed in described surface of silicon;
Drift region, is made up of the second conductive type ion injection region be formed in the selection area of described silicon epitaxy layer, and the degree of depth of equal with the top surface of described silicon epitaxy layer, the described drift region of top surface of described drift region is less than the thickness of described silicon epitaxy layer;
Channel region, be made up of the first conductive type ion injection region be formed in the selection area of described silicon epitaxy layer, described channel region and described drift region adjacent in the horizontal, the degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than or equal to the degree of depth of described drift region;
Polysilicon gate, be formed at above described channel region, described polysilicon gate and described silicon epitaxy zone isolation have gate dielectric layer, and channel region described in described polysilicon gate cover part also extends to above described drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove;
Source region, is made up of the second conduction type heavily doped region be formed in described channel region, the first side autoregistration of described source region and described polysilicon gate;
Drain region, is made up of the second conduction type heavily doped region be formed in described drift region, and the second side of described drain region and described polysilicon gate is separated by a lateral separation;
Faraday shield layer, covers on the side of the second side of described polysilicon gate and end face and between described faraday shield layer and described polysilicon gate, isolation has shielding dielectric layer;
Dark contact hole, be made up of the metal be filled in deep trouth, described deep trouth passes described source region, described channel region and described silicon epitaxy layer and enters into described silicon substrate, and described dark contact hole is by described source region, described channel region, described silicon epitaxy layer and the electrical connection of described silicon substrate;
The buried regions of the first conduction type doping, described buried regions is arranged in described drift region and is surrounded by described drift region and described drain region, the isolated segment distance of described buried regions and described channel region, the doping content of described buried regions and described drift region meets described buried regions and described drift region when to add operating voltage in described drain region and exhausts completely; Meeting when described drain region adds operating voltage under the complete depletion conditions of described buried regions and described drift region, the doping content of described drift region is higher, and the source and drain conducting resistance of radio frequency LDMOS device is less; The complete depleted region that when adding operating voltage in described drain region, described buried regions and described drift region are formed is larger, and the source and drain parasitic capacitance of described radio frequency LDMOS device is less.
2. radio frequency LDMOS device as claimed in claim 1, is characterized in that: described buried regions and described drain region contact; Or described buried regions and described drain region do not contact.
3. radio frequency LDMOS device as claimed in claim 1, is characterized in that: the degree of depth of described buried regions be the junction depth of described drift region 1/1 to two/3rd between.
4. radio frequency LDMOS device as described in claim 1 or 3, is characterized in that: the second conductive type ion injection region of described drift region is injected to add after furnace anneal advances by second conductive type ion and formed; Or the second conductive type ion injection region of described drift region is connected to form by the ion implanted region repeatedly injecting the degree of depth different; Described buried regions is made up of the first conductive type ion injection region.
5. radio frequency LDMOS device as claimed in claim 1, it is characterized in that: described radio frequency LDMOS device is N-type device, described first conduction type is P type, and described second conduction type is N-type; Or described radio frequency LDMOS device is P type device, and described first conduction type is N-type, and described second conduction type is P type.
6. a manufacture method for radio frequency LDMOS device, is characterized in that, comprises the steps:
Step one, the heavily doped surface of silicon Epitaxial growth of the first conduction type formed first conduction type doping silicon epitaxy layer;
Step 2, the second conductive type ion injection technology is adopted to form drift region in the selection area of described silicon epitaxy layer, the selection area forming described drift region is defined by photoetching process, and the degree of depth of equal with the top surface of described silicon epitaxy layer, the described drift region of top surface of described drift region is less than the thickness of described silicon epitaxy layer;
Step 3, adopt the first conductive type ion injection technology formed in described drift region first conduction type doping buried regions, described buried regions is surrounded by the drain region of described drift region and follow-up formation, the isolated segment distance in channel region of described buried regions and follow-up formation, the doping content of described buried regions and described drift region meets described buried regions and described drift region when to add operating voltage in described drain region and exhausts completely; Meeting when described drain region adds operating voltage under the complete depletion conditions of described buried regions and described drift region, the doping content of described drift region is higher, and the source and drain conducting resistance of radio frequency LDMOS device is less; The complete depleted region that when adding operating voltage in described drain region, described buried regions and described drift region are formed is larger, and the source and drain parasitic capacitance of described radio frequency LDMOS device is less;
Step 4, be formed with the described silicon epitaxy layer superficial growth gate dielectric layer of described buried regions;
Step 5, at described gate dielectric layer surface deposition polysilicon;
Step 6, employing lithographic etch process carry out etching to described polysilicon and form polysilicon gate, and described polysilicon gate is as the grid of described radio frequency LDMOS device; Second side of described polysilicon gate extends to above described drift region;
Step 7, in the selection area of described silicon epitaxy layer carry out first conductive type ion inject formed described channel region, the selection area forming described channel region is defined by photoetching process and the first side autoregistration of the selection area of described channel region and described polysilicon gate, annealing push away trap after described channel region and described drift region adjacent in the horizontal, the degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than or equal to the degree of depth of described drift region; The described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove;
Step 8, forming the described silicon substrate front deposition dielectric layer behind described channel region, described shielding dielectric layer covers the described silicon epitaxy layer surface outside the end face of described polysilicon gate and side surface and described polysilicon gate;
Step 9, at described shielding dielectric layer surface deposit faraday shield layer;
Step 10, dry etch process is adopted to etch described faraday shield layer, after etching on the described faraday shield layer side that covers the second side of described polysilicon gate and end face;
Step 11, the second conduction type heavy doping ion of carrying out are injected and are formed source region and drain region, the first side autoregistration of described source region and described polysilicon gate; Second side of described drain region and described polysilicon gate is separated by a lateral separation;
Step 12, depositing metal silicide annealed alloy, described metal silicide is formed at described source region, described drain region and not by described polycrystalline silicon gate surface that described faraday shield layer covers;
Step 13, carry out deep etching, described deep trouth is through described source region, described channel region and described silicon epitaxy layer and enter into described silicon substrate; In described deep trouth, fill metal form described dark contact hole, described dark contact hole is by described source region, described channel region, described silicon epitaxy layer and the electrical connection of described silicon substrate.
7. method as claimed in claim 6, is characterized in that: described buried regions and described drain region contact; Or described buried regions and described drain region do not contact.
8. method as claimed in claim 6, is characterized in that: the degree of depth of described buried regions be the junction depth of described drift region 1/1 to two/3rd between.
9. method as claimed in claim 6, is characterized in that: the second conductive type ion injection technology of drift region described in step 2 is that primary ions is injected, and this primary ions is injected and added that furnace anneal advances and form described drift region; Or the second conductive type ion injection technology of described drift region is repeatedly the different ion implantation of Implantation Energy, the ion implanted region that repeatedly degree of depth that formed of ion implantation is different is directly connected to form after described drift region or ion implanted region furnace anneal that repeatedly degree of depth that formed of ion implantation is different advance and forms described drift region.
10. method as described in claim 6 or 9, it is characterized in that: described radio frequency LDMOS device is N-type device, described first conduction type is P type, described second conduction type is N-type, the N-type ion implantation technology condition of described drift region is: implanted dopant is phosphorus, and Implantation Energy scope is 20KeV to 500KeV; Or described radio frequency LDMOS device is P type device, and described first conduction type is N-type, and described second conduction type is P type, the P type ion implantation technology condition of described drift region is: implanted dopant is boron, and Implantation Energy scope is 10KeV to 300KeV.
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| CN108242467A (en) * | 2016-12-27 | 2018-07-03 | 无锡华润上华科技有限公司 | LDMOS device and preparation method thereof |
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