CN104701368B

CN104701368B - Radio frequency LDMOS device and its manufacture method

Info

Publication number: CN104701368B
Application number: CN201310655616.8A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-12-06
Filing date: 2013-12-06
Publication date: 2018-04-17
Anticipated expiration: 2033-12-06
Also published as: CN104701368A

Abstract

The invention discloses a kind of radio frequency LDMOS device, drift region is non-uniform doping structure, and for raceway groove to the first, the 3rd and second drift region is followed successively by between drain region, the doping concentration of the first drift region is minimum, the electric field strength and hot carrier's effect near channel region can be reduced, improves the reliability of device；Second drift region uses higher doping concentration, can reduce the conducting resistance of device；Depletion drift region can effectively be helped, reduce the output capacitance of device by being formed at the contra-doping coating on the second drift region surface, it can also prevent from not covering the influence of the electric charge and interfacial state of the shielding dielectric layer of faraday shield layer to device, device property is more stablized.Second drift region can further increase the driving current of device in the case of the reliability and output capacitance of device is not influenced for transition region, reduce the conducting resistance of device.The invention also discloses a kind of manufacture method of radio frequency LDMOS device.

Description

Radio frequency LDMOS device and its manufacture method

Technical field

The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of radio frequency LDMOS device；The present invention is also It is related to a kind of manufacture method of radio frequency LDMOS device.

Background technology

Radio frequency lateral fet（RF LDMOS）It is the common device applied to RF base station and broadcasting station.High strike Wear voltage, low source and drain conducting resistance（RDSON）With low source and drain parasitic capacitance（Coss）It is the prerequisite device of RF LDMOS institutes Characteristic.In order to reduce the parasitic capacitance between source region and raceway groove, substrate, the substrate material of generally use heavy doping most possibly Add the epitaxial layer being lightly doped, and utilize tungsten depth contact hole connection source region, raceway groove, epitaxial layer and substrate.As shown in Figure 1, it is existing The structure diagram of radio frequency LDMOS device, by taking N-type device as an example, existing radio frequency LDMOS device includes：P-type heavy doping, that is, P+ mixes Miscellaneous silicon substrate 101, the doping concentration of silicon substrate 101 are more than 1e20cm^-3；The silicon epitaxy layer 102 that p-type is lightly doped, silicon epitaxy layer 102 doping concentration and thickness depends on the drain terminal operating voltage of device, and drain terminal operating voltage is higher, and silicon epitaxy layer 102 adulterates It is lower, thickness is thicker；N-type drift region 103, is formed in silicon epitaxy layer 102；The channel region 104 of p-type doping, 104 He of channel region Drift region 103 is adjacent in the horizontal；Gate dielectric layer 107 and polysilicon gate 108；The source region 105 of N-type heavy doping, that is, N+ doping, Drain region 106；On the surface of source region 105, drain region 106 and polysilicon gate 108 formed with metal silicide 112；Shield dielectric layer 109 With faraday shield layer 110, on the side and top surface of the drain terminal for being covered in polysilicon gate 108；Deep contact hole 111, by being filled in Metal such as tungsten in deep trouth forms, and deep trouth is through source region 105, channel region 104 and silicon epitaxy layer 102 and enters silicon substrate 101 In, source region 105, channel region 104, silicon epitaxy layer 102 and silicon substrate 101 are electrically connected by deep contact hole 111.

In hyperfrequency in application, the requirement higher of the RDSON and Coss to radio frequency LDMOS device.RDSON is wanted to keep relatively low When, it is necessary to improve the doping concentration of drift region 103 as far as possible, but this is likely to result in drift region 103 when 106 end of drain region adds high pressure It is unable to fully- depleted and causes breakdown voltage to decline.In addition it is that silicon substrate 101 is arrived in drift region 103 to restrict the principal element that Coss declines Junction capacity, as 103 concentration of drift region improve, can also increase the junction capacity, equally be unfavorable for the decline of Coss.Therefore, RDSON Mutually restricted with two parameters of Coss, existing device architecture cannot make both at the same time simply by the concentration of increase drift region All reduce, so the device property of existing radio frequency LDMOS is difficult to reach excellent properties.

The content of the invention

The technical problems to be solved by the invention are to provide a kind of radio frequency LDMOS device, can reduce the source and drain of device at the same time Conducting resistance and source and drain parasitic capacitance, increase driving current, improve the radiofrequency characteristics of device.For this reason, the present invention also provides one kind The manufacture method of radio frequency LDMOS device.

In order to solve the above technical problems, radio frequency LDMOS device provided by the invention includes：

The silicon substrate of first conduction type heavy doping.

The silicon epitaxy layer of first conduction type doping, the silicon epitaxy layer are formed in the surface of silicon.

First drift region, the second conductive type ion injection district's groups being formed from the selection area of the silicon epitaxy layer Into the depth of top surface the first drift region equal with the top surface of the silicon epitaxy layer, described of first drift region Less than the thickness of the silicon epitaxy layer.

Channel region, the first conductive type ion injection region composition being formed from the selection area of the silicon epitaxy layer, First side of first drift region and the channel region are in contact in the horizontal, the top surface of the channel region and the silicon The depth of equal, the described channel region of top surface of epitaxial layer is less than or equal to the depth of first drift region.

Polysilicon gate, is formed above the channel region, the polysilicon gate and the silicon epitaxy zone isolation have grid Jie Matter layer, channel region described in the polysilicon gate covering part is simultaneously extended to above first drift region, by the polysilicon gate The channel region surface of covering is used to form raceway groove.

Source region, the second conduction type heavily doped region composition being formed from the channel region, the source region and described more First side autoregistration of crystal silicon grid.

Drain region, the second conduction type heavily doped region composition being formed from first drift region, the drain region and institute The second side for stating polysilicon gate is separated by a lateral separation.

Second drift region, the second conductive type ion injection region being formed from the subregion of first drift region Composition, the first side of the first side of second drift region and first drift region at a distance, second drift Second side in area and the drain region laterally contact.

Contra-doping coating, is formed from second drift region surface and is formed formed with the first conduction type doped region.

3rd drift region, the second conductive type ion injection region being formed from the subregion of first drift region Composition, at a distance, the described 3rd drifts about for the first side of the 3rd drift region and the first side of first drift region First side of second side in area and second drift region is in contact or the second side of the 3rd drift region extend to it is described In second drift region so that the 3rd drift region and second drift region portion overlap.

It is made of first drift region, second drift region, the 3rd drift region and the contra-doping coating The drift region of radio frequency LDMOS device.

Dielectric layer is shielded, is formed in the table of on the side and top surface of the second side of the polysilicon gate and drift region On face.

Faraday shield layer, is formed on the shielding dielectric layer, the faraday shield layer covers the polysilicon gate The second side side and the second side of top surface and the faraday shield layer extend to above the drift region.

It is region one to make the region between the first side of the 3rd drift region and the first side of first drift region, institute The drift region for stating region one is made of the subregion of first drift region；Second side of the polysilicon gate is located at institute State the surface in region one, the second side of the faraday shield layer is located at the surface of the 3rd drift region or described Second side of faraday shield layer is located at the surface of second drift region.

The doping concentration of 3rd drift region is more than the doping concentration of first drift region, the 3rd drift region Doping concentration is less than the doping concentration of second drift region；The doping concentration of first drift region is smaller, the region one Smaller, the described radio frequency LDMOS device of electric field strength reliability it is higher；The doping concentration of second drift region is bigger, institute The source and drain conducting resistance for stating radio frequency LDMOS device is smaller；The contra-doping coating is used for the consumption for increasing by second drift region Use up and reduce the source and drain parasitic capacitance of the radio frequency LDMOS device；3rd drift region is first drift region and described Transitional region between second drift region.

A further improvement is that the junction depth of the contra-doping coating is less than the 1/5 of the junction depth of second drift region, institute The bulk concentration for stating contra-doping coating is more than 2 times of bulk concentration of second drift region.

A further improvement is that the bulk concentration of first drift region is 1e16cm^-3~5e16cm^-3；Second drift The bulk concentration in area is 5e16cm^-3~1e17cm^-3；The bulk concentration of 3rd drift region is 2e16cm^-3~6e16cm^-3。

A further improvement is that the radio frequency LDMOS device is N-type device, first conduction type is p-type, described Second conduction type is N-type；Alternatively, the radio frequency LDMOS device is P-type device, first conduction type is N-type, described Second conduction type is p-type.

In order to solve the above technical problems, the manufacture method of radio frequency LDMOS device provided by the invention includes the following steps：

Step 1: the surface of silicon Epitaxial growth in the first conduction type heavy doping forms the doping of the first conduction type Silicon epitaxy layer.

Step 2: first is formed in the selection area of the silicon epitaxy layer using the second conductive type ion injection technology Drift region, the selection area for forming first drift region are defined by photoetching process, the top surface of first drift region and The depth of equal, described first drift region of top surface of the silicon epitaxy layer is less than the thickness of the silicon epitaxy layer；Described The position that the position of first side of one drift region is in contact for first drift region with the channel region being subsequently formed.

Step 3: defining the forming region of the second drift region using photoetching process, noted using the second conductive type ion Enter technique and second drift region is formed in the forming region of second drift region, injected using the second conductive type ion Technique forms contra-doping coating on the surface of second drift region；Second drift region is located at first drift region In subregion and the first side of the first side of second drift region and first drift region is at a distance.

Step 4: defining the forming region of the 3rd drift region using photoetching process, noted using the second conductive type ion Enter technique and form the 3rd drift region in the forming region of the 3rd drift region；3rd drift region is positioned at described the In the subregion of one drift region, the first side of the 3rd drift region and the first side of first drift region be separated by one section away from It is in contact from, the second side of the 3rd drift region and the first side of second drift region or the 3rd drift region Second side extends in second drift region so that the 3rd drift region and second drift region portion overlap.

It is made of first drift region, second drift region, the 3rd drift region and the contra-doping coating The drift region of radio frequency LDMOS device；Make between the first side of the 3rd drift region and the first side of first drift region Region is region one, and the drift region in the region one is made of the subregion of first drift region.

Step 5: grow gate dielectric layer on the silicon epitaxy layer surface formed with the drift region.

Step 6: carry out heavy doping in the gate dielectric layer surface deposition polysilicon and to the polysilicon.

Step 7: carrying out first time etching to the polysilicon using lithographic etch process, this is etched source for the first time The polysilicon of side removes, and the border after the first time etching is the first side of the polysilicon gate being subsequently formed.

Step 8: the first conductive type ion of carry out in the selection area of the silicon epitaxy layer injects to form the ditch Road area, the selection area for forming the channel region are defined and the selection area of the channel region and the polycrystalline by photoetching process First side autoregistration of Si-gate, the channel region and first drift region are adjacent in the horizontal, the top of the channel region The depth of surface channel region equal with the top surface of the silicon epitaxy layer, described is less than or equal to the depth of first drift region Degree.

Step 9: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate, institute State grid of the polysilicon gate as the radio frequency LDMOS device；Second side of the polysilicon gate extends to first drift Area top and the second side of the polysilicon gate are located at the surface in the region one；Described in being covered by the polysilicon gate Channel region surface is used to form raceway groove.

Step 10: in the silicon substrate front deposition dielectric layer, the shielding dielectric layer covers the polysilicon gate Top surface and side surface and the polysilicon gate outside the silicon epitaxy layer surface.

Step 11: in the shielding dielectric layer surface deposit faraday shield layer.

Step 12: the faraday shield layer is performed etching using dry etch process, the faraday after etching Shielded layer covers the side of the second side of the polysilicon gate and the second side of top surface and the faraday shield layer extends to institute State above drift region, and the second side of the faraday shield layer is located at the surface of the 3rd drift region or the method The second side of shielded layer is drawn to be located at the surface of second drift region.

Inject to form source region and drain region Step 13: carrying out the second conduction type heavy doping ion, the source region and described First side autoregistration of polysilicon gate；The drain region and the second side of the polysilicon gate are separated by a lateral separation and described Second side of two drift regions and the drain region laterally contact.

Step 14: deposit metal silicide and annealed alloy, the metal silicide is formed at the source region, described Drain region and the polycrystalline silicon gate surface not covered by the faraday shield layer.

Step 15: carrying out deep etching, the deep trouth passes through the source region, the channel region and the silicon epitaxy layer simultaneously Enter in the silicon substrate；Metal is filled in the deep trouth and forms the deep contact hole, the depth contact hole is by the source Area, the channel region, the silicon epitaxy layer and the silicon substrate are electrically connected.

Step 2: grow gate dielectric layer on the silicon epitaxy layer surface.

Step 3: carry out heavy doping in the gate dielectric layer surface deposition polysilicon and to the polysilicon.

Step 4: carrying out first time etching to the polysilicon using lithographic etch process, this is etched source for the first time The polysilicon of side removes, and the border after the first time etching is the first side of the polysilicon gate being subsequently formed.

Step 5: the first conductive type ion of carry out in the selection area of the silicon epitaxy layer injects to form the ditch Road area, the selection area for forming the channel region are defined and the selection area of the channel region and the polycrystalline by photoetching process First side autoregistration of Si-gate；The top surface of the channel region is equal with the top surface of the silicon epitaxy layer, the raceway groove The depth in area is less than the thickness of the silicon epitaxy layer.

Step 6: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate, institute State grid of the polysilicon gate as the radio frequency LDMOS device；Channel region described in the polysilicon gate covering part, by described more The channel region surface of crystal silicon grid covering is used to form raceway groove.

Step 7: first is formed in the selection area of the silicon epitaxy layer using the second conductive type ion injection technology Drift region, the selection area of formation first drift region is defined by photoetching process and the selection area of first drift region With the second side autoregistration of the polysilicon gate；The top surface of first drift region and the top surface of the silicon epitaxy layer The depth of equal, described first drift region is less than the thickness of the silicon epitaxy layer and the depth of the channel region is less than or equal to described The depth of first drift region；First side of first drift region and the channel region are in contact in the horizontal, the polysilicon Second side of grid is extended to above first drift region.

Step 8: defining the forming region of the second drift region using photoetching process, noted using the second conductive type ion Enter technique and second drift region is formed in the forming region of second drift region, injected using the second conductive type ion Technique forms contra-doping coating on the surface of second drift region；Second drift region is located at first drift region In subregion and the first side of the first side of second drift region and first drift region is at a distance.

Step 9: defining the forming region of the 3rd drift region using photoetching process, noted using the second conductive type ion Enter technique and form the 3rd drift region in the forming region of the 3rd drift region；3rd drift region is positioned at described the In the subregion of one drift region, the first side of the 3rd drift region and the first side of first drift region be separated by one section away from It is in contact from, the second side of the 3rd drift region and the first side of second drift region or the 3rd drift region Second side extends in second drift region so that the 3rd drift region and second drift region portion overlap.

It is made of first drift region, second drift region, the 3rd drift region and the contra-doping coating The drift region of radio frequency LDMOS device；Make between the first side of the 3rd drift region and the first side of first drift region Region is region one, and the drift region in the region one is made of the subregion of first drift region；The polysilicon Second side of grid is located at the surface in the region one.

A further improvement is that the second conductive type ion injection technology of first drift region is noted for primary ions Enter, primary ions injection promotes to form first drift region plus furnace anneal；Or the second of first drift region For conductive type ion injection technology for the different ion implanting of multiple Implantation Energy, the depth that multiple ion implanting is formed is different The different ion implanting of ion implanted region is directly connected to be formed first drift region or multiple ion implanting is formed depth Area's furnace anneal forms first drift region after promoting.

A further improvement is that the radio frequency LDMOS device is N-type device, first conduction type is p-type, described Second conduction type is N-type, the Implantation Energy of the N-type ion implantation technology of first drift region be more than 100KeV, it is described The impurity of first drift region, second drift region and the 3rd drift region is phosphorus, and the contra-doping coating is mixed Impurity is boron；Alternatively, the radio frequency LDMOS device is P-type device, first conduction type is N-type, and described second is conductive Type is p-type, and the Implantation Energy of the p-type ion implantation technology of first drift region is more than 50KeV, first drift The impurity in area, second drift region and the 3rd drift region is boron, and the impurity of the contra-doping coating is Phosphorus.

Device of the present invention is using the drift region of horizontal non-uniform doping, first drift region in channel terminal drift region, that is, region one Doping concentration it is relatively low, middle drift region i.e. the 3rd drift doping concentration secondly, i.e. the second drift region in drain terminal drift region is mixed Miscellaneous concentration highest, and have contra-doping coating on drain terminal drift region.Due to the present invention drain terminal drift region doping concentration compared with Height, can make the total doping concentration in the drift region of device higher, so as to reduce the source and drain conducting resistance of device.And due to the present invention The doping concentration of channel terminal drift region is arranged to lower value, the electric field strength at channel terminal drift region, such energy can be reduced The hot carrier's effect of device is weaker, improves device reliability.In addition, the contra-doping coating on drain terminal drift region surface can be effective Ground helps depletion drift region, and drift region exhausts expansion and can reduce source and drain parasitic capacitance, so the present invention can reduce device Output capacitance.Middle drift region has higher-doped concentration relative to channel terminal drift region, and can realize is not influencing channel terminal Electric field strength at drift region, so as to not influencing under conditions of the reliability of device the further driving current of increase device, drop The conducting resistance of low device.In short, the present invention can reduce the source and drain conducting resistance and source and drain parasitic capacitance of device at the same time, increase is driven Streaming current, improves the radiofrequency characteristics of device, radio frequency LDMOS device of the present invention is obtained low on-resistance, low output capacitance, height The high-performance of driving current.

Brief description of the drawings

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：

Fig. 1 is the structure diagram of existing radio frequency LDMOS device；

Fig. 2 is the structure diagram of radio frequency LDMOS device of the embodiment of the present invention；

Fig. 3 A- Fig. 3 J are the structure diagrams of radio frequency LDMOS device in each step of one method of the embodiment of the present invention.

Embodiment

As shown in Fig. 2, it is the structure diagram of radio frequency LDMOS device of the embodiment of the present invention；Radio frequency of the embodiment of the present invention LDMOS device includes：

The silicon substrate 1 of first conduction type heavy doping.Preferably, the doping concentration of the silicon substrate 1 is more than 1e20cm^-3。

The silicon epitaxy layer 2 of first conduction type doping, the silicon epitaxy layer 2 are formed on 1 surface of silicon substrate.

First drift region 3, the second conductive type ion injection region being formed from the selection area of the silicon epitaxy layer 2 Composition, the top surface of first drift region 3 first drift region 3 equal with the top surface of the silicon epitaxy layer 2, described Depth is less than the thickness of the silicon epitaxy layer 2.

Second conductive type ion injection technology of first drift region 3 is injected for primary ions, primary ions note Enter and promote to form first drift region 3 plus furnace anneal；Or the second conductive type ion note of first drift region 3 Enter technique for the different ion implanting of multiple Implantation Energy, the different ion implanted region of the depth that multiple ion implanting is formed is direct The different ion implanted region furnace anneal of depth that connection forms first drift region 3 or repeatedly ion implanting is formed pushes away First drift region 3 is formed into rear.The ion implanting of first drift region 3 uses ability ion implanting gradual to realize Impurity genesis analysis and deeper drift region knot, alleviate the hot carrier's effect of device.The ion note of first drift region 3 It can be that autoregistration is injected to enter, and can be to be injected by the non-self-aligned of lithographic definition.

Channel region 9, the first conductive type ion injection district's groups being formed from the selection area of the silicon epitaxy layer 2 Into, the first side of first drift region 3 and the channel region 9 are in contact in the horizontal, the top surface of the channel region 9 and The depth of equal, the described channel region 9 of top surface of the silicon epitaxy layer 2 is less than or equal to the depth of first drift region 3.

Polysilicon gate 8, is formed at the top of channel region 9, isolating between the polysilicon gate 8 and the silicon epitaxy layer 2 has Gate dielectric layer 7, preferably, the material of gate dielectric layer 5 is silica.Channel region 9 described in 8 covering part of polysilicon gate simultaneously prolongs The top of the first drift region 3 is reached, is used to form raceway groove by 9 surface of the channel region that the polysilicon gate 8 covers.

Source region 11, the second conduction type heavily doped region composition being formed from the channel region 9, the source region 11 and institute State the first side autoregistration of polysilicon gate 8.

Drain region 10, the second conduction type heavily doped region composition being formed from first drift region 3, the drain region 10 It is separated by a lateral separation with the second side of the polysilicon gate 8.In the source region 11, the drain region 10 and the polysilicon gate 8 Surface all formed with metal silicide 12.

Second drift region 4, the second conductive type ion injection being formed from the subregion of first drift region 3 District's groups into, the first side of the first side of second drift region 4 and first drift region 3 at a distance, described second The second side and the drain region 10 laterally contact of drift region 4.

Contra-doping coating 5, is formed from 4 surface of the second drift region and adulterates district's groups formed with the first conduction type Into.The junction depth of the contra-doping coating 5 is less than the 1/5 of the junction depth of second drift region 4, the contra-doping coating 5 Bulk concentration is more than 2 times of the bulk concentration of second drift region 4.

3rd drift region 6, the second conductive type ion injection being formed from the subregion of first drift region 3 District's groups into, the first side of the 3rd drift region 6 and the first side of first drift region 3 at a distance, the described 3rd First side of the second side of drift region 6 and second drift region 4 is in contact or the second side of the 3rd drift region 6 is prolonged Reach in second drift region 4 so that the 3rd drift region 6 and 4 part of the second drift region overlaps.

By first drift region 3, second drift region 4, the 3rd drift region 6 and the contra-doping coating 5 Form the drift region of radio frequency LDMOS device.

Dielectric layer 13 is shielded, is formed on the side and top surface of the second side of the polysilicon gate 8 and the drift region Surface on.The shielding dielectric layer 13 on the top surface of the polysilicon gate 8 and the metal in the embodiment of the present invention Silicide contacts.Preferably, the material of the shielding dielectric layer 13 is silica, silicon nitride or silicon oxynitride.

Faraday shield layer 14, is formed on the shielding dielectric layer 13, the faraday shield layer 14 covers described more Second side of the side of the second side of crystal silicon grid 8 and top surface and the faraday shield layer 14 is extended to above the drift region.

It is region one to make the region between the first side of the 3rd drift region 6 and the first side of first drift region 3, The drift region in the region one is made of the subregion of first drift region 3；The second side position of the polysilicon gate 8 In the surface in the region one, the second side of the faraday shield layer 14 be located at the 3rd drift region 6 surface or Second side of faraday shield layer 14 described in person is located at the surface of second drift region 4；Namely the faraday shield layer Second drift region 4 can not covered or part cover by 14 by all or part of covering in the 3rd drift region 6, described The part in region one is covered by the polysilicon gate 8, is partly covered by the faraday shield layer 14.

The doping concentration of 3rd drift region 6 is more than the doping concentration of first drift region 3, the 3rd drift region 6 doping concentration is less than the doping concentration of second drift region 4；Preferably：The bulk concentration of first drift region 3 is 1e16cm^-3~5e16cm^-3；The bulk concentration of second drift region 4 is 5e16cm^-3~1e17cm^-3；3rd drift region 6 Bulk concentration is 2e16cm^-3~6e16cm^-3.The doping concentration of first drift region 3 is used for the electric-field strength for adjusting the region one Degree, the doping concentration of first drift region 3 is smaller, the hot current-carrying in smaller, the described region one of electric field strength in the region one Sub- effect is smaller, and the reliability of the radio frequency LDMOS device is higher；The doping concentration of second drift region 4 is used to adjust institute The source and drain conducting resistance of radio frequency LDMOS device is stated, the doping concentration of second drift region 4 is bigger, the radio frequency LDMOS device Source and drain conducting resistance it is smaller；The contra-doping coating 5 is used to increase exhausting and reducing described penetrate for second drift region 4 The source and drain parasitic capacitance of frequency LDMOS device；In addition, the presence of the contra-doping coating 5, moreover it is possible to realize not by the faraday Isolation between drift region that shielded layer 14 is covered and the shielding dielectric layer 13 at top, can eliminate the shielding medium The influence of electric charge and interfacial state to device in layer 13, makes the characteristic of device more stablize.3rd drift region 6 is described the Transitional region between one drift region 3 and second drift region 4, since the reliability of device is by first drift region 3 Doping concentration determines, the output capacitance of device is together decided on by second drift region 4 and the contra-doping coating 5, described 3rd drift region 6 in the case of the reliability and the output capacitance of device for not influencing device, can further increase the drive of device Streaming current, reduces the conducting resistance of device.

The junction depth of the contra-doping coating 5 is less than the 1/5 of the junction depth of second drift region 4, the contra-doping covering The bulk concentration of layer 5 is more than 2 times of the bulk concentration of second drift region 4.

The structure of radio frequency LDMOS device of the embodiment of the present invention is suitable for N-type device, is also applied for P-type device.When this hair When bright embodiment radio frequency LDMOS device is N-type device, first conduction type is p-type, and second conduction type is N-type, The Implantation Energy of the N-type ion implantation technology of first drift region 3 is first drift region 3, described the more than 100KeV The impurity of two drift regions 4 and the 3rd drift region 6 is phosphorus, and the impurity of the contra-doping coating 5 is boron.Or Person, when radio frequency LDMOS device of the embodiment of the present invention is P-type device, first conduction type is N-type, and described second is conductive Type is p-type, and the Implantation Energy of the p-type ion implantation technology of first drift region 3 is more than 50KeV, first drift The impurity in area 3, second drift region 4 and the 3rd drift region 6 is boron, and the doping of the contra-doping coating 5 is miscellaneous Matter is phosphorus.

It is the structural representation of radio frequency LDMOS device in each step of one method of the embodiment of the present invention as shown in Fig. 3 A to Fig. 3 J Figure, for manufacturing device of the embodiment of the present invention as shown in Figure 2, the manufacture method of one radio frequency LDMOS device of the embodiment of the present invention Include the following steps：

Step 1: as shown in Figure 3A, first is formed in the 1 surface Epitaxial growth of silicon substrate of the first conduction type heavy doping The silicon epitaxy layer 2 of conduction type doping.Preferably, the doping concentration of the silicon substrate 1 is more than 1e20cm^-3。

Step 2: as shown in Figure 3B, using the second conductive type ion injection technology in the selected area of the silicon epitaxy layer 2 The first drift region 3 is formed in domain, the selection area for forming first drift region 3 is defined by photoetching process, first drift The depth of the top surface in area 3 first drift region 3 equal with the top surface of the silicon epitaxy layer 2, described is less than outside the silicon Prolong the thickness of layer 2；The position of first side of first drift region 3 is first drift region 3 and the channel region 9 being subsequently formed The position being in contact.

Second conductive type ion injection technology of first drift region 3 is injected for primary ions, primary ions note Enter and promote to form first drift region 3 plus furnace anneal；Or the second conductive type ion note of first drift region 3 Enter technique for the different ion implanting of multiple Implantation Energy, the different ion implanted region of the depth that multiple ion implanting is formed is direct The different ion implanted region furnace anneal of depth that connection forms first drift region 3 or repeatedly ion implanting is formed pushes away First drift region 3 is formed into rear.The ion implanting of first drift region 3 uses ability ion implanting gradual to realize Impurity genesis analysis and deeper drift region knot, alleviate the hot carrier's effect of device.

Step 3: as shown in Figure 3 C, the forming region of the second drift region 4 is defined using photoetching process, is led using second Electric types of ion injection technology forms second drift region 4 in the forming region of second drift region 4, is led using second Electric types of ion injection technology forms contra-doping coating 5 on the surface of second drift region 4；Second drift region 4 In the subregion of first drift region 3 and the first side of second drift region 4 and first drift region 3 Side is at a distance.The junction depth of the contra-doping coating is less than the 1/5 of the junction depth of second drift region, described counter to mix The bulk concentration of miscellaneous coating is more than 2 times of the bulk concentration of second drift region.

Step 4: as shown in Figure 3D, the forming region of the 3rd drift region 6 is defined using photoetching process, led using second Electric types of ion injection technology forms the 3rd drift region 6 in the forming region of the 3rd drift region 6；3rd drift Move area 6 to be located in the subregion of first drift region 3, the first side and first drift region 3 of the 3rd drift region 6 The first side at a distance, the second side of the 3rd drift region 6 and the first side of second drift region 4 be in contact, Or the second side of the 3rd drift region 6 extends in second drift region 4 so that the 3rd drift region 6 and described the Two drift regions, 4 part overlaps.

By first drift region 3, second drift region 4, the 3rd drift region 6 and the contra-doping coating 5 Form the drift region of radio frequency LDMOS device；Make the first side of the 3rd drift region 6 and the first side of first drift region 3 Between region be region one, the drift region in the region one is made of the subregion of first drift region 3.

The doping concentration of 3rd drift region 6 is more than the doping concentration of first drift region 3, the 3rd drift region 6 doping concentration is less than the doping concentration of second drift region 4；Preferably, the bulk concentration of first drift region 3 is 1e16cm^-3~5e16cm^-3；The bulk concentration of second drift region 4 is 5e16cm^-3~1e17cm^-3；3rd drift region 6 Bulk concentration is 2e16cm^-3~6e16cm^-3。

The doping concentration of first drift region 3 is smaller, and the electric field strength in the region one is smaller, the radio frequency LDMOS The reliability of device is higher；The doping concentration of second drift region 4 is bigger, the source and drain electric conduction of the radio frequency LDMOS device Hinder smaller；The contra-doping coating 5 is used to increase exhausting and reducing the radio frequency LDMOS device for second drift region 4 Source and drain parasitic capacitance；Transition region of 3rd drift region 6 between first drift region 3 and second drift region 4 Domain.

Step 5: as shown in FIGURE 3 E, grow gate dielectric layer 7 on 2 surface of the silicon epitaxy layer formed with the drift region. Preferably, the gate dielectric layer 7 is gate oxide.

Step 6: as shown in FIGURE 3 E, carry out in the 7 surface deposition polysilicon 8 of gate dielectric layer and to the polysilicon 8 weight Doping.

Step 7: as shown in FIGURE 3 E, first time etching is carried out to the polysilicon using lithographic etch process, this is for the first time Etching removes the polysilicon of source side, and the border after the first time etching is the polysilicon gate 8 being subsequently formed First side.

Step 8: as illustrated in Figure 3 F, carry out the first conductive type ion note in the selection area of the silicon epitaxy layer 2 Enter to be formed the channel region 9, formed the channel region 9 selection area defined by photoetching process and the channel region 9 it is selected Region and the first side autoregistration of the polysilicon gate 8, the channel region 9 and first drift region 3 are adjacent in the horizontal, The depth of the top surface of the channel region 9 channel region 9 equal with the top surface of the silicon epitaxy layer 2, described is less than or equal to The depth of first drift region 3.

Step 9: as shown in Figure 3 G, the polysilicon is carried out described in second of etching formation using lithographic etch process Polysilicon gate 8, grid of the polysilicon gate 8 as the radio frequency LDMOS device；The second side extension of the polysilicon gate 8 It is located at the surface in the region one to the second side of the top of the first drift region 3 and the polysilicon gate 8；By described more 9 surface of the channel region that crystal silicon grid 8 cover is used to form raceway groove.

As shown in figure 3h, depositing silicide barrier oxide layer, metal silicide is formed using lithographic etch process by needing The silicide barrier oxide layer in 12 region removes, and simultaneously short annealing forms the metal silicide 12, institute to deposit metal State 12 surface of source region 9 and drain region that metal silicide 12 is located at the surface of the polysilicon gate 8 and is subsequently formed.Above-mentioned institute The formation process for stating metal silicide 12 is located in progress before follow-up shielding dielectric layer 13 is formed, the metal silicide 12 formation process can also be placed in follow-up step ten four and carry out.

Step 10: as shown in fig. 31, in the positive deposition dielectric layer 13 of the silicon substrate 1, and to the shielding medium Layer 13 carries out chemical wet etchings, after etching, the shielding dielectric layer 13 cover the polysilicon gate 8 top surface and side surface and 2 surface of the silicon epitaxy layer outside the polysilicon gate 8.

Step 11: as shown in figure 3j, in the shielding 13 surface deposition faraday shield layer 14 of dielectric layer.

Step 12: as shown in figure 3j, being performed etching using dry etch process to the faraday shield layer 14, etch The faraday shield layer 14 covers side and top surface and the faraday shield layer 14 of the second side of the polysilicon gate 8 afterwards The second side extend to above the drift region, and the second side of the faraday shield layer 14 is located at the 3rd drift region 6 Surface or the second side of the faraday shield layer 14 be located at the surface of second drift region 4, namely the method Draw shielded layer 14 to cover the 3rd drift region 6 is all or part of, second drift region 4 is not covered or part Covering, the part in the region one is covered by the polysilicon gate 8, is partly covered by the faraday shield layer 14.In Fig. 3 J Second side of the faraday shield layer 14 is located at the surface of second drift region 4, namely the faraday shield layer 14 3rd drift region 6 can all be covered, 4 part of the second drift region be covered, the part in the region one is by institute Polysilicon gate 8 is stated to cover, partly covered by the faraday shield layer 14.

Step 13: inject to form source region 11 and drain region 10 as shown in Fig. 2, carrying out the second conduction type heavy doping ion, First side autoregistration of the source region 11 and the polysilicon gate 8；The drain region 10 and the second side of the polysilicon gate 8 are separated by The laterally contact of the second side and the drain region 10 of one lateral separation and second drift region 4.

Step 14: when to be formed 12 processing step of metal silicide in step 9, can be in this step Carried out in rapid；The forming region of metal silicide 12 is defined using silicide barrier oxide layer, deposit metal silicide 12 is simultaneously Annealed alloy, the metal silicide 12 are formed at the source region 11, the drain region 10 and not by the faraday shield layers 8 surface of the polysilicon gate of 14 coverings.

Step 15: carrying out deep etching, the deep trouth passes through the source region 11, the channel region 9 and the silicon epitaxy Layer 2 is simultaneously entered in the silicon substrate 1；Metal is filled in the deep trouth and forms the deep contact hole, the depth contact hole will The source region 11, the channel region 9, the silicon epitaxy layer 2 and the silicon substrate 1 are electrically connected.

The structure of radio frequency LDMOS device manufactured by one method of the embodiment of the present invention is suitable for N-type device, is also applied for P-type device.When radio frequency LDMOS device is N-type device, in one method of the embodiment of the present invention, first conduction type is P Type, second conduction type are N-type, the Implantation Energy of the N-type ion implantation technology of first drift region 3 be more than 100KeV, the impurity of first drift region 3, second drift region 4 and the 3rd drift region 6 is phosphorus, described anti- The impurity for adulterating coating 5 is boron.Alternatively, when radio frequency LDMOS device is P-type device, one method of the embodiment of the present invention In, first conduction type is N-type, and second conduction type is p-type, the p-type ion implanting work of first drift region 3 The Implantation Energy of skill is more than 50KeV, and first drift region 3, second drift region 4 and the 3rd drift region 6 are mixed Impurity is boron, and the impurity of the contra-doping coating 5 is phosphorus.

Two method of the embodiment of the present invention is also used for manufacturing device of the embodiment of the present invention as shown in Figure 2, the embodiment of the present invention It is that first drift region 3 is formed using photoetching process rather than self-registered technology in one method, and two method of the embodiment of the present invention In be first drift region 3 is formed using self-registered technology, as shown in Fig. 2, two radio frequency LDMOS device of the embodiment of the present invention Manufacture method includes the following steps：

Step 1: 1 surface Epitaxial growth the first conduction type of formation of silicon substrate in the first conduction type heavy doping is mixed Miscellaneous silicon epitaxy layer 2.Preferably, the doping concentration of the silicon substrate 1 is more than 1e20cm^-3。

Step 2: grow gate dielectric layer 7 on 2 surface of silicon epitaxy layer.Preferably, the gate dielectric layer 7 is gate oxidation Layer.

Step 3: carry out heavy doping in the 7 surface deposition polysilicon 8 of gate dielectric layer and to the polysilicon 8.

Step 4: carrying out first time etching to the polysilicon using lithographic etch process, this is etched source for the first time The polysilicon of side removes, and the border after the first time etching is the first side of the polysilicon gate 8 being subsequently formed.

Step 5: the first conductive type ion of carry out in the selection area of the silicon epitaxy layer 2 inject to be formed it is described Channel region 9, the selection area for forming the channel region 9 are defined and the selection area of the channel region 9 and described by photoetching process First side autoregistration of polysilicon gate 8；The top surface of the channel region 9 is equal with the top surface of the silicon epitaxy layer 2, institute The depth for stating channel region 9 is less than the thickness of the silicon epitaxy layer 2.

Step 6: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate 8, institute State grid of the polysilicon gate 8 as the radio frequency LDMOS device；Channel region 9 described in 8 covering part of polysilicon gate, by institute 9 surface of the channel region for stating the covering of polysilicon gate 8 is used to form raceway groove.

Step 7: is formed in the selection area of the silicon epitaxy layer 2 using the second conductive type ion injection technology One drift region 3, formed first drift region 3 selection area defined by photoetching process and first drift region 3 it is selected Region and the second side autoregistration of the polysilicon gate 8；The top surface of first drift region 3 and the silicon epitaxy layer 2 The depth of equal, described first drift region 3 of top surface is less than the thickness of the silicon epitaxy layer 2 and the depth of the channel region 9 Less than or equal to the depth of first drift region 3；First side of first drift region 3 and the channel region 9 phase in the horizontal Contact, the second side of the polysilicon gate 8 extend to the top of the first drift region 3.

Step 8: defining the forming region of the second drift region 4 using photoetching process, noted using the second conductive type ion Enter technique and second drift region 4 is formed in the forming region of second drift region 4, noted using the second conductive type ion Enter technique and form contra-doping coating 5 on the surface of second drift region 4；Second drift region 4 is positioned at the described first drift Move in the subregion in area 3 and the first side of the first side of second drift region 4 and first drift region 3 is separated by one section Distance.The junction depth of the contra-doping coating is less than the 1/5 of the junction depth of second drift region, the body of the contra-doping coating Concentration is more than 2 times of the bulk concentration of second drift region.

Step 9: defining the forming region of the 3rd drift region 6 using photoetching process, noted using the second conductive type ion Enter technique and form the 3rd drift region 6 in the forming region of the 3rd drift region 6；3rd drift region 6 is located at institute In the subregion for stating the first drift region 3, the first side of the 3rd drift region 6 and the first side phase of first drift region 3 Every a distance, the second side of the 3rd drift region 6 and the first side of second drift region 4 are in contact or described Second side of three drift regions 6 extends in second drift region 4 so that the 3rd drift region 6 and second drift region 4 Part is overlapping.

Depositing silicide barrier oxide layer, the institute in the region of metal silicide 12 is formed using lithographic etch process by needing The removal of silicide barrier oxide layer is stated, simultaneously short annealing forms the metal silicide 12, the metal silicide to deposit metal 12 positioned at the surface of the polysilicon gate 8 and 12 surface of source region 9 and drain region being subsequently formed.Metal silicide described above 12 formation process is located in before follow-up shielding dielectric layer 13 is formed and carries out, the formation process of the metal silicide 12 Also it can be placed in follow-up step ten four and carry out.

Step 10: in the positive deposition dielectric layer 13 of the silicon substrate 1, the shielding dielectric layer 13 covers the polycrystalline 2 surface of the silicon epitaxy layer outside the top surface and side surface and the polysilicon gate 8 of Si-gate 8.

Step 11: in the shielding 13 surface deposition faraday shield layer 14 of dielectric layer.

Step 12: the faraday shield layer 14 is performed etching using dry etch process, the farad after etching Shielded layer 14 covers the side of the second side of the polysilicon gate 8 and the second side of top surface and the faraday shield layer 14 is prolonged Reach above the drift region, and the second side of the faraday shield layer 14 be located at the 3rd drift region 6 surface or Second side of faraday shield layer 14 described in person is located at the surface of second drift region 4, namely the faraday shield layer Second drift region 4 can not covered or part cover by 14 by all or part of covering in the 3rd drift region 6, described The part in region one is covered by the polysilicon gate 8, is partly covered by the faraday shield layer 14.Faraday described in Fig. 3 J Second side of shielded layer 14 is located at the surface of second drift region 4, namely the faraday shield layer 14 can be by described in The all coverings of 3rd drift region 6,4 part of the second drift region are covered, the part in the region one is by the polysilicon gate 8 Covering, partly covered by the faraday shield layer 14.

Inject to form source region 11 and drain region 10 Step 13: carrying out the second conduction type heavy doping ion, the source region 11 With the first side autoregistration of the polysilicon gate 8；The drain region 10 and the second side of the polysilicon gate 8 be separated by one laterally away from From and the laterally contact of the second side of second drift region 4 and the drain region 10.

The structure of radio frequency LDMOS device manufactured by two method of the embodiment of the present invention is suitable for N-type device, is also applied for P-type device.When radio frequency LDMOS device is N-type device, in two method of the embodiment of the present invention, first conduction type is P Type, second conduction type are N-type, the Implantation Energy of the N-type ion implantation technology of first drift region 3 be more than 100KeV, the impurity of first drift region 3, second drift region 4 and the 3rd drift region 6 is phosphorus, described anti- The impurity for adulterating coating 5 is boron.Alternatively, when radio frequency LDMOS device is P-type device, two method of the embodiment of the present invention In, first conduction type is N-type, and second conduction type is p-type, the p-type ion implanting work of first drift region 3 The Implantation Energy of skill is more than 50KeV, and first drift region 3, second drift region 4 and the 3rd drift region 6 are mixed Impurity is boron, and the impurity of the contra-doping coating 5 is phosphorus.

The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should It is considered as protection scope of the present invention.

Claims

A kind of 1. radio frequency LDMOS device, it is characterised in that including：

The silicon substrate of first conduction type heavy doping；

The silicon epitaxy layer of first conduction type doping, the silicon epitaxy layer are formed in the surface of silicon；

First drift region, the second conductive type ion injection region composition being formed from the selection area of the silicon epitaxy layer, The depth of top surface the first drift region equal with the top surface of the silicon epitaxy layer, described of first drift region is less than The thickness of the silicon epitaxy layer；

Channel region, the first conductive type ion injection region composition being formed from the selection area of the silicon epitaxy layer are described First side of the first drift region and the channel region are in contact in the horizontal, the top surface of the channel region and the silicon epitaxy The depth of equal, the described channel region of top surface of layer is less than or equal to the depth of first drift region；

Polysilicon gate, is formed above the channel region, and the polysilicon gate and the silicon epitaxy zone isolation have gate dielectric layer, Channel region described in the polysilicon gate covering part is simultaneously extended to above first drift region, is covered by the polysilicon gate The channel region surface is used to form raceway groove；

Source region, the second conduction type heavily doped region composition being formed from the channel region, the source region and the polysilicon First side autoregistration of grid；

Drain region, the second conduction type heavily doped region composition being formed from first drift region, the drain region and described more Second side of crystal silicon grid is separated by a lateral separation；

Second drift region, the second conductive type ion injection district's groups being formed from the subregion of first drift region Into, the first side of the first side of second drift region and first drift region at a distance, second drift region The second side and the drain region laterally contact；

Contra-doping coating, is formed from second drift region surface and is formed formed with the first conduction type doped region；

3rd drift region, the second conductive type ion injection district's groups being formed from the subregion of first drift region Into, the first side of the 3rd drift region and the first side of first drift region at a distance, the 3rd drift region The second side and the first side of second drift region be in contact or the second side of the 3rd drift region extends to described In two drift regions so that the 3rd drift region and second drift region portion overlap；

Radio frequency is formed by first drift region, second drift region, the 3rd drift region and the contra-doping coating The drift region of LDMOS device；

Dielectric layer is shielded, is formed in the surface of on the side and top surface of the second side of the polysilicon gate and drift region On；

Faraday shield layer, is formed on the shielding dielectric layer, and the faraday shield layer covers the of the polysilicon gate Second side of the side of two sides and top surface and the faraday shield layer is extended to above the drift region；

It is region one to make the region between the first side of the 3rd drift region and the first side of first drift region, the area The drift region in domain one is made of the subregion of first drift region；Second side of the polysilicon gate is located at the area The surface in domain one, the second side of the faraday shield layer are located at the surface of the 3rd drift region or the farad Second side of shielded layer is located at the surface of second drift region；

The doping concentration of 3rd drift region is more than the doping of the doping concentration, the 3rd drift region of first drift region Concentration is less than the doping concentration of second drift region；The doping concentration of first drift region is smaller, the electricity in the region one The reliability of smaller, the described radio frequency LDMOS device of field intensity is higher；The doping concentration of second drift region is bigger, described to penetrate The source and drain conducting resistance of frequency LDMOS device is smaller；The contra-doping coating is used to increase exhausting simultaneously for second drift region Reduce the source and drain parasitic capacitance of the radio frequency LDMOS device；3rd drift region is first drift region and described second Transitional region between drift region.
2. radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The junction depth of the contra-doping coating is less than described The 1/5 of the junction depth of second drift region, the bulk concentration of the contra-doping coating are more than the 2 of the bulk concentration of second drift region Times.
3. radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The bulk concentration of first drift region is 1e16cm^-3 ~5e16cm^-3；The bulk concentration of second drift region is 5e16cm^-3~1e17cm^-3；The bulk concentration of 3rd drift region is 2e16cm^-3~6e16cm^-3。
4. radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The radio frequency LDMOS device is N-type device, described First conduction type is p-type, and second conduction type is N-type；Alternatively, the radio frequency LDMOS device is P-type device, it is described First conduction type is N-type, and second conduction type is p-type.
5. a kind of manufacture method of radio frequency LDMOS device, it is characterised in that include the following steps：

Step 1: the silicon of surface of silicon Epitaxial growth formation the first conduction type doping in the first conduction type heavy doping Epitaxial layer；

Step 2: the first drift is formed in the selection area of the silicon epitaxy layer using the second conductive type ion injection technology Area, the selection area for forming first drift region are defined by photoetching process, the top surface of first drift region and described The depth of equal, described first drift region of top surface of silicon epitaxy layer is less than the thickness of the silicon epitaxy layer；First drift Move the position that the position of first side in area is in contact for first drift region with the channel region being subsequently formed；

Step 3: defining the forming region of the second drift region using photoetching process, work is injected using the second conductive type ion Skill forms second drift region in the forming region of second drift region, using the second conductive type ion injection technology Contra-doping coating is formed on the surface of second drift region；Second drift region is located at the part of first drift region In region and the first side of the first side of second drift region and first drift region is at a distance；

Step 4: defining the forming region of the 3rd drift region using photoetching process, work is injected using the second conductive type ion Skill forms the 3rd drift region in the forming region of the 3rd drift region；3rd drift region is positioned at the described first drift Move area subregion in, the first side of the 3rd drift region and the first side of first drift region at a distance, Second side of the 3rd drift region and the first side of second drift region be in contact or the 3rd drift region second Side extends in second drift region so that the 3rd drift region and second drift region portion overlap；

Radio frequency is formed by first drift region, second drift region, the 3rd drift region and the contra-doping coating The drift region of LDMOS device；Make the region between the first side of the 3rd drift region and the first side of first drift region For region one, the drift region in the region one is made of the subregion of first drift region；

The doping concentration of 3rd drift region is more than the doping of the doping concentration, the 3rd drift region of first drift region Concentration is less than the doping concentration of second drift region；The doping concentration of first drift region is smaller, the electricity in the region one The reliability of smaller, the described radio frequency LDMOS device of field intensity is higher；The doping concentration of second drift region is bigger, described to penetrate The source and drain conducting resistance of frequency LDMOS device is smaller；The contra-doping coating is used to increase exhausting simultaneously for second drift region Reduce the source and drain parasitic capacitance of the radio frequency LDMOS device；3rd drift region is first drift region and described second Transitional region between drift region；

Step 5: grow gate dielectric layer on the silicon epitaxy layer surface formed with the drift region；

Step 6: carry out heavy doping in the gate dielectric layer surface deposition polysilicon and to the polysilicon；

Step 7: carrying out first time etching to the polysilicon using lithographic etch process, this is etched source side for the first time The polysilicon remove, the border after first time etching is the first side of the polysilicon gate being subsequently formed；

Step 8: the first conductive type ion of carry out in the selection area of the silicon epitaxy layer injects to form the raceway groove Area, the selection area for forming the channel region are defined and the selection area of the channel region and the polysilicon by photoetching process First side autoregistration of grid, the channel region and first drift region are adjacent in the horizontal, the top table of the channel region The depth of face channel region equal with the top surface of the silicon epitaxy layer, described is less than or equal to the depth of first drift region；

Step 9: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate, it is described more Grid of the crystal silicon grid as the radio frequency LDMOS device；Second side of the polysilicon gate is extended on first drift region Side and the second side of the polysilicon gate are located at the surface in the region one；The raceway groove covered by the polysilicon gate Area surface is used to form raceway groove；

Step 10: in the silicon substrate front deposition dielectric layer, the shielding dielectric layer covers the top of the polysilicon gate The silicon epitaxy layer surface outside face and side surface and the polysilicon gate；

Step 11: in the shielding dielectric layer surface deposit faraday shield layer；

Step 12: the faraday shield layer is performed etching using dry etch process, the Faraday shield after etching Layer covers the side of the second side of the polysilicon gate and the second side of top surface and the faraday shield layer extends to the drift Move above area, and the second side of the faraday shield layer is located at the surface of the 3rd drift region or the faraday Second side of shielded layer is located at the surface of second drift region；

Inject to form source region and drain region Step 13: carrying out the second conduction type heavy doping ion, the source region and the polycrystalline First side autoregistration of Si-gate；The drain region and the second side of the polysilicon gate are separated by a lateral separation and second drift The second side and the drain region for moving area laterally contact；

Step 14: deposit metal silicide and annealed alloy, the metal silicide are formed at the source region, the drain region The polycrystalline silicon gate surface not covered by the faraday shield layer；

Step 15: carrying out deep etching, the deep trouth is through the source region, the channel region and the silicon epitaxy layer and enters Into the silicon substrate；Metal is filled in the deep trouth and forms deep contact hole, the depth contact hole is by the source region, the ditch Road area, the silicon epitaxy layer and the silicon substrate are electrically connected.
6. a kind of manufacture method of radio frequency LDMOS device, it is characterised in that include the following steps：

Step 1: the silicon of surface of silicon Epitaxial growth formation the first conduction type doping in the first conduction type heavy doping Epitaxial layer；

Step 2: grow gate dielectric layer on the silicon epitaxy layer surface；

Step 3: carry out heavy doping in the gate dielectric layer surface deposition polysilicon and to the polysilicon；

Step 4: carrying out first time etching to the polysilicon using lithographic etch process, this is etched source side for the first time The polysilicon remove, the border after first time etching is the first side of the polysilicon gate being subsequently formed；

Step 5: the first conductive type ion of carry out in the selection area of the silicon epitaxy layer injects to form channel region, shape Selection area into the channel region defined by photoetching process and the selection area of the channel region and the polysilicon gate Side autoregistration；The depth of the top surface of channel region channel region equal with the top surface of the silicon epitaxy layer, described Less than the thickness of the silicon epitaxy layer；

Step 6: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate, it is described more Grid of the crystal silicon grid as the radio frequency LDMOS device；Channel region described in the polysilicon gate covering part, by the polysilicon The channel region surface of grid covering is used to form raceway groove；

Step 7: the first drift is formed in the selection area of the silicon epitaxy layer using the second conductive type ion injection technology Area, the selection area of formation first drift region is defined by photoetching process and the selection area of first drift region and institute State the second side autoregistration of polysilicon gate；The top surface of first drift region and the top surface phase of the silicon epitaxy layer The depth of thickness and the channel region that the depth of flat, described first drift region is less than the silicon epitaxy layer is less than or equal to described the The depth of one drift region；First side of first drift region and the channel region are in contact in the horizontal, the polysilicon gate The second side extend to above first drift region；

Step 8: defining the forming region of the second drift region using photoetching process, work is injected using the second conductive type ion Skill forms second drift region in the forming region of second drift region, using the second conductive type ion injection technology Contra-doping coating is formed on the surface of second drift region；Second drift region is located at the part of first drift region In region and the first side of the first side of second drift region and first drift region is at a distance；

Step 9: defining the forming region of the 3rd drift region using photoetching process, work is injected using the second conductive type ion Skill forms the 3rd drift region in the forming region of the 3rd drift region；3rd drift region is positioned at the described first drift Move area subregion in, the first side of the 3rd drift region and the first side of first drift region at a distance, Second side of the 3rd drift region and the first side of second drift region be in contact or the 3rd drift region second Side extends in second drift region so that the 3rd drift region and second drift region portion overlap；

Radio frequency is formed by first drift region, second drift region, the 3rd drift region and the contra-doping coating The drift region of LDMOS device；Make the region between the first side of the 3rd drift region and the first side of first drift region For region one, the drift region in the region one is made of the subregion of first drift region；The polysilicon gate Second side is located at the surface in the region one；

The doping concentration of 3rd drift region is more than the doping of the doping concentration, the 3rd drift region of first drift region Concentration is less than the doping concentration of second drift region；The doping concentration of first drift region is smaller, the electricity in the region one The reliability of smaller, the described radio frequency LDMOS device of field intensity is higher；The doping concentration of second drift region is bigger, described to penetrate The source and drain conducting resistance of frequency LDMOS device is smaller；The contra-doping coating is used to increase exhausting simultaneously for second drift region Reduce the source and drain parasitic capacitance of the radio frequency LDMOS device；3rd drift region is first drift region and described second Transitional region between drift region；

Step 10: in the silicon substrate front deposition dielectric layer, the shielding dielectric layer covers the top of the polysilicon gate The silicon epitaxy layer surface outside face and side surface and the polysilicon gate；

Step 11: in the shielding dielectric layer surface deposit faraday shield layer；

Step 12: the faraday shield layer is performed etching using dry etch process, the Faraday shield after etching Layer covers the side of the second side of the polysilicon gate and the second side of top surface and the faraday shield layer extends to the drift Move above area, and the second side of the faraday shield layer is located at the surface of the 3rd drift region or the faraday Second side of shielded layer is located at the surface of second drift region；

Inject to form source region and drain region Step 13: carrying out the second conduction type heavy doping ion, the source region and the polycrystalline First side autoregistration of Si-gate；The drain region and the second side of the polysilicon gate are separated by a lateral separation and second drift The second side and the drain region for moving area laterally contact；

Step 14: deposit metal silicide and annealed alloy, the metal silicide are formed at the source region, the drain region The polycrystalline silicon gate surface not covered by the faraday shield layer；

Step 15: carrying out deep etching, the deep trouth is through the source region, the channel region and the silicon epitaxy layer and enters Into the silicon substrate；Metal is filled in the deep trouth and forms deep contact hole, the depth contact hole is by the source region, the ditch Road area, the silicon epitaxy layer and the silicon substrate are electrically connected.
7. such as 5 or 6 the method for claim, it is characterised in that：The junction depth of the contra-doping coating is less than the described second drift The 1/5 of the junction depth in area is moved, the bulk concentration of the contra-doping coating is more than 2 times of the bulk concentration of second drift region.
8. such as 5 or 6 the method for claim, it is characterised in that：The second conductive type ion injection of first drift region Technique is injected for primary ions, and primary ions injection promotes to form first drift region plus furnace anneal；It is or described Second conductive type ion injection technology of the first drift region is the different ion implanting of multiple Implantation Energy, multiple ion implanting The ion implanted region that the depth of formation is different is directly connected to the depth to form first drift region or multiple ion implanting is formed Spend after different ion implanted region furnace anneals promotes and form first drift region.
9. such as 5 or 6 the method for claim, it is characterised in that：The radio frequency LDMOS device is N-type device, and described first leads Electric type is p-type, and second conduction type is N-type, and the Implantation Energy of the N-type ion implantation technology of first drift region is More than 100KeV, the impurity of first drift region, second drift region and the 3rd drift region is phosphorus, described anti- The impurity for adulterating coating is boron；Alternatively, the radio frequency LDMOS device is P-type device, first conduction type is N Type, second conduction type are p-type, the Implantation Energy of the p-type ion implantation technology of first drift region be more than 50KeV, the impurity of first drift region, second drift region and the 3rd drift region are boron, the contra-doping The impurity of coating is phosphorus.
10. such as 5 or 6 the method for claim, it is characterised in that：The bulk concentration of first drift region is 1e16cm^-3~ 5e16cm^-3；The bulk concentration of second drift region is 5e16cm^-3~1e17cm^-3；The bulk concentration of 3rd drift region is 2e16cm^-3~6e16cm^-3。