CN101385151B - Lateral power transistor with self-biasing electrodes - Google Patents
Lateral power transistor with self-biasing electrodes Download PDFInfo
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- CN101385151B CN101385151B CN200780005748.9A CN200780005748A CN101385151B CN 101385151 B CN101385151 B CN 101385151B CN 200780005748 A CN200780005748 A CN 200780005748A CN 101385151 B CN101385151 B CN 101385151B
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Abstract
A semiconductor power transistor includes a drift region of a first conductivity type and a well region of a second conductivity type in the drift region such that the well region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type is in the well region, and a second highly doped silicon region is in the drift region. The second highly doped silicon region is laterally spaced from the well region such that upon biasing the transistor in a conducting state, a current flows laterally between first and second highly doped silicon regions through the drift region. Each of a plurality of trenches extending into the drift region perpendicular to the current flow includes a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.
Description
The cross reference of related application
The application requires the rights and interests of No. the 60/774th, 900, the U.S. Provisional Application submitted on February 16th, 2006, and it is open to be incorporated into this by quoting as proof.
Also be incorporated into this 10/951st, No. 259 in No. the 10/269th, 126, the U. S. application of submission on October 3rd, 2002 and the U. S. application of submitting to September 26 in 2004 by quoting as proof.
Background technology
The application relates to semiconductor power device, more specifically, relates to the lateral power with the automatic bias electrode that is integrated into wherein.Fig. 1 illustrates the viewgraph of cross-section of traditional (Silicon-on-insulator) MOSFET lateral 100.Extend on highly doped N type district 102 light dope N type drift region 104.Distinguishing the P type tagma 106 and the highly doped N type drain region 114 that separate each other by the N type lightly doped drain (LDD) of horizontal expansion all is formed in the drift region 104.In tagma 106, form highly doped N type source region 110, and in tagma 106, form heavy body (heavybody) district 108.Grid 118 extends on the surface in tagma 106, and overlap source region 110 and LDD district 112.Grid 118 is by the region insulation of gate insulator 116 below it.The part that is in the tagma 106 under the grid 118 directly forms MOSFET channel region 120.
During operation, when descending MOSFET 100 to be bias voltage in working order, electric current 110 laterally flows to drain region 114 by channel region 120 and LDD district 112 from the source region.As most conventional MOS FET, the improvement in performance of (Silicon-on-insulator) MOSFET lateral 100 is subject to the competition purpose of higher blocking ability of realization and lower conducting resistance (Rdson).Though LDD district 112 produces improved Rdson, this improvement is subject to transistorized blocking ability.For example, the degree of depth that can extend of the doping content in LDD district 112 and LDD district all strictly is subject to breakdown voltage transistor.
These obstruction to improvement in performance also are present in the lateral power of other types, for example, and transversal I GBT, horizontal pn diode and lateral direction schottky diode.Therefore, existence is for the technology requirement of blocking ability, conducting resistance and other performance parameters that can improve the multiclass lateral power thus.
Summary of the invention
According to embodiments of the invention, the semiconductor power transistor comprises the drift region of first conductivity type and the well region of second conductivity type in this drift region, makes to form the pn knot between well region and the drift region.The first highly doped silicon area (silicon region) of first conductivity type is in well region, and the second highly doped silicon area is in the drift region.In a single day the second highly doped silicon area and well region laterally separate, and make under conduction state bias voltage to be added to transistor, electric current just laterally flows between the first highly doped silicon area and the second highly doped silicon area by the drift region.Each groove that extends to a plurality of grooves in the drift region perpendicular to electric current includes dielectric layer and at least one conductive electrode that covers at least a portion that is lining in trenched side-wall.
According to another embodiment of the present invention, semiconductor diode comprises the drift region of first conductivity type and the anode region of second conductivity type in this drift region, makes to form the pn knot between anode region and the drift region.The first highly doped silicon area of first conductivity type is in the drift region, and laterally separate with the anode region, in a single day make under conduction state bias voltage to be added to semiconducter power diode, electric current just laterally flows between the anode region and the first highly doped silicon area by the drift region.Each groove that extends to a plurality of grooves in the drift region perpendicular to electric current all comprises dielectric layer and at least one conductive electrode that covers at least a portion that is lining in trenched side-wall.
According to another embodiment of the present invention, Schottky diode comprises the drift region of first conductivity type and the light dope silicon area of first conductivity type in this drift region.Conductor layer extends on the light dope silicon area and contacts with this light dope silicon area, with between form Schottky contacts.In a single day the highly doped silicon area and the light dope silicon area of first conductivity type in the drift region laterally separate, and make under conduction state bias voltage to be added to Schottky diode, electric current just laterally flows between light dope silicon area and highly doped silicon area by the drift region.Each groove that extends to a plurality of grooves in the drift region perpendicular to electric current all comprises dielectric layer and at least one conductive electrode that covers at least a portion that is lining in trenched side-wall.
According to another embodiment of the present invention, as get off to form semiconductor transistor.In the drift region, form well region, with between form the pn knot.The drift region is first conductivity type, and well region is second conductivity type.In well region, form the first highly doped silicon area of first conductivity type.In the drift region, form the second highly doped silicon area.In a single day the second highly doped silicon area and well region laterally separate, and make under conduction state bias voltage to be added to semiconductor transistor, electric current just laterally flows between the first highly doped silicon area and the second highly doped silicon area by the drift region.Formation is perpendicular to a plurality of grooves in the drift region of extending to of electric current.The dielectric layer of at least a portion that is lining in trenched side-wall is covered in formation.In each groove, form at least one conductive electrode.
According to another embodiment of the present invention, as get off to form semiconductor diode.In the drift region, form the anode region, with between form the pn knot.The drift region is first conductivity type, and the anode region is second conductivity type.In the drift region, form the first highly doped silicon area of first conductivity type.In a single day laterally separate in the first highly doped silicon area and the anode region, make under conduction state bias voltage to be added to semiconducter power diode, electric current just laterally flows between the anode region and the first highly doped silicon area by the drift region.
According to another embodiment of the present invention, as get off to form Schottky diode.In the drift region of first conductivity type, form the light dope silicon area of first conductivity type.Be formed on the light dope silicon area conductor layer that extends and contact with this light dope silicon area, with between form Schottky contacts.In the drift region, form the highly doped silicon area of first conductivity type.In a single day highly doped silicon area and light dope silicon area laterally separate, and make under conduction state bias voltage to be added to Schottky diode, electric current just laterally flows between light dope silicon area and highly doped silicon area by the drift region.Formation is perpendicular to a plurality of grooves in the drift region of extending to of electric current.The dielectric layer of at least a portion that is lining in trenched side-wall is covered in formation.In each groove, form at least one conductive electrode.
Description of drawings
Fig. 1 illustrates the viewgraph of cross-section of the simplification of traditional (Silicon-on-insulator) MOSFET lateral 100;
Fig. 2 and Fig. 3 illustrate the viewgraph of cross-section of the simplification of the (Silicon-on-insulator) MOSFET lateral structure that has two different automatic bias electrode structures that are integrated into wherein according to an exemplary embodiment of the present invention;
Fig. 4 and Fig. 5 are the simulation results that the Electric Field Distribution in the drift region of conventional MOS FET among Fig. 1 and the exemplary MOSFET embodiment shown in Fig. 3 is shown respectively;
Fig. 6 to Figure 16 illustrates the isometric view of simplification that is integrated into the multiple lateral power structure of automatic bias electrode structure wherein according to having of other exemplary embodiment of the present invention; And
Figure 17 A to Figure 17 C illustrates the top layout views according to three representative configuration of the automatic bias electrode of the embodiment of the invention.
Embodiment
According to the present invention, the automatic bias electrode is integrated in the multiple lateral power, thereby changes Electric Field Distribution in the barrier layer of these devices with the blocking ability of the identical device of the doping content of improving the barrier layer.Alternatively, for identical blocking ability, the automatic bias electrode is implemented in the higher doping content of use in the barrier layer, improves the conducting resistance and the power consumption of device thus.
Fig. 2 illustrates the viewgraph of cross-section of the simplification of planar gate (planar-gate) (Silicon-on-insulator) MOSFET lateral 200 that has the automatic bias electrode according to an exemplary embodiment of the present invention.Extend on highly doped N type semiconductor district 202 light dope N type drift region 204.In one embodiment, drift region 204 and the high doping semiconductor district 202 below it all are epitaxial loayers.In another embodiment, drift region 204 is epitaxial loayers, and high doping semiconductor district 202 is N+ substrates.In another embodiment, by dopant being injected and advancing high-doped zone 202 to form drift region 204, wherein, this high-doped zone self can be epitaxial loayer or substrate.
The demand that the doping of electrode 224 is carefully controlled has advantageously been eliminated in the existence of dielectric layer 226, otherwise will need it to guarantee charge balance.Similarly, comprise among the embodiment of doped silicon that dielectric layer 226 prevents that dopant in the doped silicon is to outdiffusion at electrode 224.
Method according to the manufacturing MOSFET 200 of the embodiment of the invention is as follows.Use conventional art on drift region 204, to form gate dielectric 216 and gate electrode 218.Use tradition shelter (masking) and injections/propelling (drive-in) technology in the drift region 204 formation tagmas 206, source region 210, drain region 214 and heavy tagma 208.Notice, source region 210 and tagma 208 are self-aligned to the edge of gate electrode 218.Use known technology to form unshowned a plurality of metal level (for example, source metal level and leakage metal level) and dielectric layer.Use tradition to shelter and the next groove 222 that in drift region 204, forms of etch techniques.Then, form dielectric layer 226 and be lining in trenched side-wall and bottom to cover.In one embodiment, dielectric layer 226 has
Scope in thickness.Determine a doping content that factor is drift region 204 in the thickness of dielectric layer 226.For drift region, can use thinner dielectric layer 226 with higher-doped concentration.
Next, deposition and dark etching polysilicon layer, thus have end face with the adjacent platforms surface co-planar with the embedding groove 222 of polysilicon.Make the polysilicon in each groove recessed a little, thereby expose along a plurality of parts of the dielectric layer 226 of last trenched side-wall.A plurality of parts of the layer 226 that is exposed are the parts that are removed, thereby expose the drift region 204 along last trenched side-wall.Carry out second polysilicon deposition and dark etching,, make polysilicon electrode electrical short in each groove thus to the drift region with the top of embedding each groove.
Depend on manufacturing technology, be used for a plurality of layers the material and the restriction of other processing and design, can carry out the treatment step that forms the automatic bias electrode at the place of a plurality of stages that handles.For example, if electrode 224 comprises polysilicon, so then can the initial stage in processing carry out the step that forms trenched electrodes because polysilicon can withstand high temperature.Yet,, need making after a while after carrying out high-temperature process carry out the step that is used to form trenched electrodes in the processing if electrode 224 comprises metal.
Fig. 3 illustrates the optional automatic bias electrode structure/technique that according to the present invention another exemplary embodiment is integrated with MOSFET 300.In Fig. 3, the electrode 324 in the groove 322 electrically contacts along the bottom section 328 of groove 322 rather than along top and drift region 304 as the groove among the MOSFET 200.Except the treatment step that the formation trenched electrodes structurally associated with next description joins, the manufacturing process that is used to form MOSFET 300 is similar to the manufacture process that is used for above-mentioned MOSFET 200.
Use tradition to shelter and in drift region 304, form groove 322 with etch techniques.Although further extension groove 322 is to be terminated in the high-doped zone 302, because the more low-doped automatic bias electrode 324 that helps of drift region 304, it is more favourable therefore to stop groove 322 in drift region 304.This will describe in more detail following.Next, use conventional art to form and cover the dielectric layer 326 that is lining in trenched side-wall and bottom.Next, the directional etch of dielectric layer 326 is only removed the horizontal-extending portion of dielectric layer 326.Therefore drift region 304 becomes exposure along the bottom section 328 of groove 322.Formation then, is recessed into groove 322 with it such as the conductive electrode of in-situ doped (in-situdoped) (P type) polysilicon.Next, on electrode 324, form another dielectric layer with closed groove 322.Therefore, electrode 328 electrically contacts with drift region 304 along channel bottom zone 328.
Between P type electrode 224 among the MOSFET 200 and the N type drift region 204 and MOSFET 300 in P type electrode 324 and N type drift region 304 between be electrically connected and cause electrode 224 and 324 self-bias are pressed onto voltage greater than zero.In one embodiment, put upside down the doping polarity in the All Ranges in MOSFET 200 and 300, form the P channel mosfet thus.In this embodiment, being electrically connected between P type drift region and the N type channel electrode causes the electrode self-bias to be pressed onto minus voltage.
As shown by the simulation result among Fig. 4 and Fig. 5, the automatic bias electrode is used for changing the electric field in the drift region.Fig. 4 illustrates the Electric Field Distribution in the drift region 104 of the conventional MOS FET 100 among Fig. 1.As can be seen, electric field reaches peak value near the curvature in tagma 106, then, reduces gradually to the drain region, forms triangle area thus below electric field curve.Fig. 5 illustrates the Electric Field Distribution in the drift region 304 of the MOSFET 300 among Fig. 3.As can be seen, except the peak value of the curvature in tagma 306, introduce two extra peak values by two automatic bias electrodes 324.Therefore, increased the area of electric field curve below, it has increased transistorized puncture voltage again.As indicated among Fig. 4 and Fig. 5, for 5 * 10
15/ cm
3Identical drift region doping content, puncture voltage is brought up to the 125V of MOSFET 300 from the 75V of the MOSFET 100 of prior art.This equals in 66% improvement in the puncture voltage.
Fig. 6 illustrates the isometric view according to the simplification of the MOSFET 600 of the embodiment of the invention, peels off a plurality of layers therein to appear following zone.MOSFET 600 is similar to MOSFET 300 except the following a few features that further describes.The isometric view of Fig. 6 illustrates one of many possible placement pattern of automatic bias electrode in the drift region 604.As can be seen, arrange the automatic bias electrode with staggered general layout, but those skilled in the art it is also envisioned that many other structures.In one embodiment, the position of electrode and number depend on the doping content of drift region 604 to a certain extent.The doping content of drift region 604 is high more, then can place many more electrodes in the drift region, and therefore obtains higher puncture voltage.Similarly, the number of electrode can be subject to the current density requirements of device.
In optional embodiment, the LDD district that is similar to the LDD district 112 among the conventional MOS FET 100 is incorporated among the MOSFET 600.This LDD district will have the doping content higher than the drift region 604 that forms this LDD district therein, and therefore then allowing more if desired, the automatic bias electrode of more number is included in the drift region.The LDD district has reduced the conducting resistance of device significantly and has increased puncture voltage together with the number of the automatic bias electrode that is increased.
Fig. 6 also show electrically contact source region 610 and heavy tagma 608 source conductor 632 (for example, comprise metal) and the drain conductor 634 that electrically contacts drain region 614 is (for example, comprise metal) and the dielectric layer 630 that source conductor 632, grid 618 and drain conductor 634 is insulated from each other.Go out as shown, channel electrode 624 terminates in the upper surface place of drift region 604, makes dielectric layer 630 complete coated electrodes 624.In another embodiment, the electrode 324 that is similar among the MOSFET 300 of electrode 624 is recessed in its corresponding groove.
Another difference between the MOSFET 600 and 300 is that in MOSFET 600, trenched electrodes 624 runs through drift region 604 fully, and terminates in the more low-doped silicon area 602.This causes electrode 624 with more low-doped silicon area 602 rather than drift region 604 contacts.This is favourable, is by the lower doped region 602 of contact (as contrasting with higher doped drift region 604), and electrode 624 can automatic bias and do not obtain the electromotive force (will obtain this electromotive force under the situation of the higher doped silicon region of electrode contact) of silicon area.
Fig. 7 illustrates the isometric view of the simplification of the lateral insulated gate bipolar transistor (IGBT) 700 that has integrated automatic bias electrode according to an exemplary embodiment of the present invention.Extend on light dope N type district 702 N type drift region 704.In one embodiment, drift region 704 and light doping section 702 all are epitaxial loayers.In another embodiment, drift region 704 is epitaxial loayers, and light doping section 702 is N-substrates.In another embodiment, form drift region 704 by dopant is injected and is advanced to light doping section 702, light doping section self can be epitaxial loayer or substrate.
Groove 722 runs through drift region 704, and terminates in the silicon area 702.Insulating barrier 726 covers the sidewall that is lining in groove rather than the bottom of groove.Conductive electrode 724 embedding each groove 722 also electrically contact silicon area 702 along the bottom section 728 of groove.In one embodiment, the conductibility of conductive electrode 724 is opposite with the conductibility of silicon area 702, and therefore supposes the N type conductibility of silicon area 702, and then the conductivity of conductive electrode is the P type.In another embodiment, conductive electrode 724 comprises highly doped P type polysilicon or the silicon or the metal that mix.
Although the difference on needing to consider to move (for example, hole current and electronic current all help the conduction of current among the IGBT), but relate to the many considerations relevant (for example, the placement of electrode and frequency are to the doping content of drift region) and be applied to IGBT700 equally with previous embodiment.
Fig. 8 illustrates the isometric view of the simplification of the transverse diode 800 with integrated automatic bias electrode of another exemplary embodiment according to the present invention.Extend on light dope N type district 802 N type drift region 804.In embodiment formerly, silicon area 802 can be epitaxial loayer or substrate, and can be epitaxial loayer maybe can form by dopant is injected and is advanced to silicon area 802 in drift region 804.
In drift region 804, form p type anode district 806 and highly doped N type (N+) district 814.Go out as shown, anode region 806 and N+ district 814 separate transverse to each other.Plate conductor layer 832 (for example, comprising metal) electrically contacts anode region 806, and cathode conductor layer 834 (for example, comprising metal) electrically contacts N+ district 814.Dielectric layer 830 makes plate conductor layer 832 and cathode conductor layer 834 insulated from each other.Trenched electrodes 824 have with Fig. 6 and Fig. 7 in the structure of similar, and therefore not described.In embodiment formerly, for identical drift region doping content, automatic bias electrode 824 is used for improving the blocking ability of diode 800.
Fig. 9 illustrates the isometric view of the simplification of the lateral direction schottky diode 900 with integrated automatic bias electrode of another exemplary embodiment according to the present invention.The structure of lateral direction schottky diode 900 is similar to diode 800 to a great extent, yet, replace p type anode district 806, in drift region 904, form shallow light dope N type district 906.Plate conductor 932 (for example, comprising Schottky barrier metal) forms the Schottky contacts with shallow N type district 906.In a distortion, form shallow p type island region and replace N type district 906, thus, plate conductor 932 forms the Schottky contacts with p type island region.In embodiment formerly, for identical drift region doping content, automatic bias electrode 924 is used for improving the blocking ability of Schottky diode 900.
Figure 10 illustrates the isometric view of simplification of the distortion of (Silicon-on-insulator) MOSFET lateral 600, and drain plug (drain plug) 1034 (for example, comprising metal) in depth extends in the drift region 1004 therein.In one embodiment, drain plug 1034 extends to and the electrode trenches 1022 approximately uniform degree of depth.The advantage of this embodiment is that drain plug (drain plug) 1034 is used for the electric current of expansion (spread) by drift region 1004, further reduces the conducting resistance of MOSFET thus.This combines with the automatic bias electrode and has reduced transistorized conducting resistance and power consumption significantly.
Figure 11 illustrates the isometric view of simplification of the distortion of (Silicon-on-insulator) MOSFET lateral 1000, removes therein outside the drain plug 1134, and the highly doped N type drain region 1114 that surrounds this drain plug 1134 is incorporated in this structure.Drain region 1114 further reduces the resistance of transistor current path, and reduces the contact resistance of drain plug.Before coming embedding groove, carry out two pass (two-pass) angle of N type impurity then and inject and form drain region 1114 by forming groove with drain plug (for example, metal).
Figure 12 at the high conductive plunger 1234 in the collector terminal place of IGBT 1200 (for example illustrates according to the present invention another exemplary embodiment, metal) and the execution mode of optional highly doped P type collector region 1214, itself and IGBT 700 are similar on aspect other of structure.Figure 13 at the high conductive plunger 1334 in the cathode terminal place of transverse diode 1300 (for example illustrates according to the present invention another exemplary embodiment, metal) and the execution mode in highly doped N type district 1214, the transverse diode 800 among itself and Fig. 8 is similar on aspect other of structure.。In embodiment in front, connector 1334 and N+ district 1314 help to improve the conducting resistance of diode.Also in Schottky diode 900 to realize high conductive plunger with the similar fashion shown in Figure 130 0.
Fig. 6 to Figure 13 is illustrated in the higher-doped n type layer (for example, the layer 604 among Fig. 6) on the more low-doped n type layer (for example, the layer 602 among Fig. 6).In a distortion of these structures, on highly doped substrate, be epitaxially formed each layer in these two layers.In another distortion, higher-doped n type layer is an epitaxial loayer, and following more low-doped n type layer can be a substrate.In another distortion, by n type dopant being injected and being advanced to the n type layer that light dope n type layer forms higher-doped, this light dope n type layer self can be epitaxial loayer or the substrate that extends on substrate.
Figure 14 illustrates the execution mode that uses silicon-on-insulator (SOI) technology or buried dielectric (burieddielectric) technology automatic bias electrode in MOSFET 1400.Go out as shown, except forming outside this structure on the dielectric layer 1440 (for example, comprising oxide), MOSFET 1400 is similar to the MOSFET among Fig. 6.In one embodiment, silicon area 1402 and 1404 is the epitaxial loayers that sequentially are formed on the dielectric layer 1440.In another embodiment, by being injected and be advanced to the silicon area 1402 that is epitaxially formed, dopant forms drift region 1404.At dielectric layer 1440 is under the situation of buried dielectric, and traditional Semiconductor substrate (not shown) is positioned under the dielectric layer 1440.Use SOT or buried dielectric to be implemented in other lateral powers (comprising transversal I GBT, transverse diode and lateral direction schottky diode) of disclosure herein for considering that those skilled in the art of the present disclosure is conspicuous.
Figure 15 illustrates the distortion of the MOSFET of Figure 14, wherein, has eliminated the light dope silicon area 1402 among the MOSFET1400, makes electrode 1424 terminate in the drift region 1504 and electrically contacts this drift region.Figure 16 illustrates another distortion, wherein, MOSFET 1600 is formed in the individual layer of silicon 1604.Other transversal devices of realizing having integrated automatic bias electrode in the mode that is similar to the embodiment shown in Figure 15 and Figure 16 will be conspicuous for considering those skilled in the art of the present disclosure.
Figure 17 A to Figure 17 C illustrates the top layout views of three representative configuration of automatic bias electrode.In Figure 17 A, each electrode 1724A is by dielectric layer 1726A and drift region 1704A insulation.With with Fig. 6 to Figure 16 in the similarly staggered general layout of structure come electrode among the Pareto diagram 17A.In Figure 17 B, a large amount of electrode 1724B are placed among dielectric well (dielectric well) 1726B that follows extension.Figure 17 C also illustrates the electrode 1724C that follows arrangement, but each electrode insulate partly by dielectric layer 1726C and drift region 1704C.Though the electrode among Figure 17 A to Figure 17 C is square, they can have alternatively such as circle, hexagon and oval-shaped many other shapes.
Notice, can be with the LDD district to be incorporated among a plurality of embodiment of disclosing herein one or more with the similar mode of above-mentioned mode about Fig. 6.Similarly, though Fig. 6 to Figure 16 illustrates the upper surface place that trenched electrodes terminates in the drift region, but among other embodiment of the transversal device in Fig. 6 to Figure 16, the electrode 324 among trenched electrodes and the MOSFET 300 is recessed in its corresponding groove similarly.
Multiple lateral direction power MOSFET and the IGBT embodiment with the describing that illustrate in this article have planar gate structure, yet, have disclosed in No. the 10/269th, 126, the U.S. Patent application of being submitted on October 3rd, 2002 (its open be incorporated into this) by quoting as proof those the (Silicon-on-insulator) MOSFET lateral of trench gate structure and IGBT in realize that the automatic bias electrode is for considering that those skilled in the art of the present disclosure are conspicuous.Similarly, have disclosed in No. the 10/951st, 259, the U.S. Patent application of being submitted on September 26th, 2004 (its open be incorporated into this) by quoting as proof those the (Silicon-on-insulator) MOSFET lateral of dhield grid (shielded gate) structure and IGBT in realize that the automatic bias electrode will be conspicuous for considering those skilled in the art of the present disclosure.
Though the detailed description for various embodiments of the present invention is provided above, these embodiment many optionally, modification, combination and equivalent all be possible.For example, though the exemplary lateral power device embodiment among Fig. 6 to Figure 16 incorporates the automatic bias electrode into, it makes and to contact with adjacent silicon area along the bottom of electrode, but revise embodiment or its tangible distortion of these lateral powers, make that electrode will be conspicuous along the adjacent silicon area of its top (being similar to shown in Fig. 2) contact concerning considering those skilled in the art of the present disclosure.Similarly, it all only is exemplary purpose that being used for of should be appreciated that in this article to be provided described multiple size, doping content and different semiconductor layer or all material type of insulating barrier, is not intended to restriction.For example, can be reversed in the doping polarity and the automatic bias electrode of the multiple silicon area among the embodiment described herein, with the device of the opposite polarity type that obtains specific embodiment.For these and other reasons, therefore, top description will not be regarded as limitation of the scope of the invention, and scope of the present invention is limited by appended claim.
Claims (18)
1. semiconductor transistor comprises:
The drift region of first conductivity type;
The well region of second conductivity type in the described drift region forms the pn knot between described well region and the described drift region;
The first highly doped silicon area of described first conductivity type in the described well region;
The second highly doped silicon area in the described drift region, the described second highly doped silicon area and described well region are laterally isolated, make in a single day under conduction state bias voltage to be added to described semiconductor transistor, electric current laterally flows between the first highly doped silicon area and the second highly doped silicon area by described drift region; And
Perpendicular to a plurality of grooves in the described drift region of extending to of described electric current, each groove all has the dielectric layer that covers at least a portion that is lining in described trenched side-wall and along the upper side wall of each groove or contact at least one conductive electrode of described drift region along the bottom electrical of each groove.
2. semiconductor transistor according to claim 1, wherein, extend on the 3rd silicon area of described first conductivity type described drift region, and described the 3rd silicon area has the doping content higher than described drift region.
3. semiconductor transistor according to claim 1, wherein, extend on the 3rd silicon area described drift region, and described the 3rd silicon area has the doping content lower than the doping content of described drift region.
4. semiconductor transistor according to claim 3, wherein, described the 3rd silicon area extends on dielectric layer.
5. semiconductor transistor according to claim 1, wherein, extend on dielectric layer described drift region.
6. semiconductor transistor according to claim 1, wherein, each conductive electrode all is second conductivity types.
7. semiconductor transistor according to claim 3, also be included in the LDD district of described first conductivity type that extends in the top of the described drift region between the described well region and the described second highly doped silicon area, described LDD district has the doping content higher than described drift region.
8. semiconductor transistor according to claim 1, wherein, described a plurality of electrodes with staggered general layout between the described well region and the described second highly doped silicon area.
9. semiconductor transistor according to claim 1, wherein, described semiconductor transistor is that the MOSFET and the described first highly doped silicon area form the source region, and the described second highly doped silicon area be described first conductivity type and form the drain region, described device also comprises:
Planar gate is extended and overlap described source region and described drift region on the part of described well region.
10. semiconductor transistor according to claim 9 also comprises high conductive drain connector, extends to the described second highly doped silicon area.
11. semiconductor transistor according to claim 10, wherein, described high conductive drain connector and described a plurality of groove extend to the essentially identical degree of depth.
12. semiconductor transistor according to claim 1, wherein, described semiconductor transistor is IGBT, and the described second highly doped silicon area be described second conductivity type and form collector region, described device also comprises:
Planar gate is extended and the overlap described first highly doped silicon area and described drift region on the part of described well region.
13. semiconductor transistor according to claim 12 also comprises high conduction collector electrode connector, extends to described collector region.
14. semiconductor transistor according to claim 13, wherein, described high conduction collector electrode connector and described a plurality of groove extend to the essentially identical degree of depth.
15. a method that forms semiconductor transistor comprises:
Form well region in the drift region of first conductivity type, described well region is second conductivity type, forms the pn knot between described drift region and the described well region;
In described well region, form the first highly doped silicon area of described first conductivity type;
In described drift region, form the second highly doped silicon area, the described second highly doped silicon area and described well region laterally separate, make in a single day under conduction state bias voltage to be added to described semiconductor transistor, electric current laterally flows between the first highly doped silicon area and the second highly doped silicon area by described drift region;
Formation is perpendicular to a plurality of grooves that extend to described drift region of described electric current;
The dielectric layer of at least a portion that is lining in described trenched side-wall is covered in formation; And
In each groove, form along the upper side wall of each groove or contact at least one conductive electrode of described drift region along the bottom electrical of each groove.
16. method according to claim 15 also is included on the substrate of described first conductivity type and forms epitaxial loayer, described epitaxial loayer forms described drift region, and described substrate has the doping content higher than described drift region.
17. method according to claim 15, wherein, the step of described at least one conductive electrode of formation comprises the polysilicon layer that forms the described a plurality of grooves of filling, and described polysilicon layer is in-situ doped to have second conductivity type.
18. method according to claim 15 also comprises the planar gate of extending on the predetermined surface zone that is formed on described drift region.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77490006P | 2006-02-16 | 2006-02-16 | |
| US60/774,900 | 2006-02-16 | ||
| US11/404,062 US7473976B2 (en) | 2006-02-16 | 2006-04-12 | Lateral power transistor with self-biasing electrodes |
| US11/404,062 | 2006-04-12 | ||
| PCT/US2007/061718 WO2007098317A2 (en) | 2006-02-16 | 2007-02-06 | Lateral power devices with self-biasing electrodes |
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| CN101385151B true CN101385151B (en) | 2013-07-24 |
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| CN102945838A (en) * | 2012-11-05 | 2013-02-27 | 电子科技大学 | High voltage interconnection structure |
| CN106549052B (en) * | 2015-09-17 | 2021-05-25 | 联华电子股份有限公司 | Lateral diffusion metal oxide semiconductor transistor and manufacturing method thereof |
| CN110739345B (en) * | 2019-08-30 | 2021-03-30 | 电子科技大学 | Self-biased split gate trench type power MOSFET device |
| CN118522769B (en) * | 2024-07-22 | 2024-10-01 | 江苏应能微电子股份有限公司 | High-voltage ESD protection device for latch-up resistance |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445019B2 (en) * | 2000-03-23 | 2002-09-03 | Koninklijke Philips Electronics N.V. | Lateral semiconductor device for withstanding high reverse biasing voltages |
| CN1494160A (en) * | 2002-09-25 | 2004-05-05 | ��ʽ���綫֥ | Power semiconductor element |
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2007
- 2007-02-06 CN CN200780005748.9A patent/CN101385151B/en not_active Expired - Fee Related
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445019B2 (en) * | 2000-03-23 | 2002-09-03 | Koninklijke Philips Electronics N.V. | Lateral semiconductor device for withstanding high reverse biasing voltages |
| CN1494160A (en) * | 2002-09-25 | 2004-05-05 | ��ʽ���綫֥ | Power semiconductor element |
Also Published As
| Publication number | Publication date |
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| CN101385151A (en) | 2009-03-11 |
| MY147514A (en) | 2012-12-31 |
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