CN113921610B - LDMOS device structure and manufacturing method thereof - Google Patents

LDMOS device structure and manufacturing method thereof Download PDF

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Publication number
CN113921610B
CN113921610B CN202111118014.XA CN202111118014A CN113921610B CN 113921610 B CN113921610 B CN 113921610B CN 202111118014 A CN202111118014 A CN 202111118014A CN 113921610 B CN113921610 B CN 113921610B
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insulating layer
region
conductivity type
conductive
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CN113921610A (en
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吴兵
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Abstract

The invention provides an LDMOS device structure and a manufacturing method thereof, wherein the structure comprises the following steps: a substrate of a first conductivity type, an upper surface of which is formed an epitaxial layer of the first conductivity type; the grid structure is positioned on the upper surface of the epitaxial layer; a first conductivity type well region and a second conductivity type drift region within the epitaxial layer; a source region within the first conductivity type well region and a drain region within the second conductivity type drift region; the first insulating layer is positioned on the upper surface of the epitaxial layer; and a first conductive via extending through the first insulating layer, the source region and the epitaxial layer and extending to the substrate contact, and the first conductive via being in contact with the upper surface of the source region to connect the source region and the first conductive via of the substrate based on the first conductive via, so that on-resistance of the source region can be reduced, EAS capability of the device is improved, and overall performance of the device is enhanced.

Description

LDMOS device structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an LDMOS device structure and a manufacturing method thereof.
Background
The LDMOS (Lateral Double Diffused Metal Oxide Semiconductor, lateral double-diffused metal oxide semiconductor) device has the advantages of high gain, high voltage resistance, high output power, good thermal stability, high efficiency and the like as a power device, and is widely used for a radio frequency power amplifier, a power switch, a DC/DC converter, a high-voltage I/O circuit and the like. In order to ensure the output power and gain effect of the device, the on-resistance of the source region of the LDMOS device is generally adopted to measure the performance of the device.
An LDMOS device structure known in the art, as shown in fig. 1, comprises a substrate 101, an epitaxial layer 102, a well region 103, a drift region 104, a source region 105, a drain region 106, a gate 107, a field plate 108, a first insulating layer 109, a second insulating layer 110, a third insulating layer 111, a source region conductive trench 112, a drain region conductive trench 113, a drain electrode 114, and a source electrode 115. In the prior art, the source region conductive trench 113 is formed by etching the multi-layer structures such as the second insulating layer 110, the field plate 108, the first insulating layer 109, the epitaxial layer 102, etc., and a conductive material is injected into the source region conductive trench 113 to form a conductive channel between the source region 106 and the substrate 101; however, since the source region conductive trench 112 and the source region 105 are only based on sidewall contact, the contact condition is prone to be poor, so that the contact resistance becomes large, which affects not only the stability of the on-resistance of the device, but also the stability of EAS (Energy Avalanche Stress) avalanche energy of the device, thereby greatly affecting the performance of the device.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an LDMOS device structure and a method for manufacturing the same, which are used for solving the problem that in the prior art, the source electrode and the conductive trench of the LDMOS device are only contacted through the sidewall, resulting in an increase of the contact resistance.
To achieve the above and other related objects, the present invention provides, in a first aspect, an LDMOS device structure comprising: a substrate of a first conductivity type, an upper surface of which is formed an epitaxial layer of the first conductivity type; the grid structure is positioned on the upper surface of the epitaxial layer; the first conductive type well region and the second conductive type drift region are both positioned in the epitaxial layer, and the conductive types of the first conductive type well region and the second conductive type drift region are opposite; the source region is of a second conductivity type and is positioned in the first conductivity type well region; the drain region is of the first conductivity type and is positioned in the drift region of the second conductivity type; the first insulating layer covers the upper surface and the two side walls of the grid structure and the upper surface of the epitaxial layer; a first conductive via extending through the substrate including the first insulating layer, the source region, and the epitaxial layer, and extending into contact with the substrate; the first conductive channel is in contact with the upper surface of the source region to connect the source region and the substrate; a second insulating layer over the first conductive via and the first insulating layer; a second conductive path extending to contact the drain region; a drain electrode connected to the drain region by connecting to the second conductive path; a gate electrode connected to the gate structure; and a source electrode located on a surface of the substrate remote from the epitaxial layer.
In an embodiment of the present invention, the first conductive channel and the upper surface contact area of the source area form a protruding eave; based on the protruding eave, the first conductive channel is divided into an upper portion and a lower portion, and the width of the upper portion of the first conductive channel is larger than that of the lower portion of the first conductive channel.
In an embodiment of the invention, the first insulation layer separates the upper portion of the first conductive channel from the gate structure, and the separation width is 0.1-0.3 um.
In an embodiment of the present invention, the LDMOS device structure further includes: and a body contact region of a first conductivity type within the substrate, the first conductive via connecting the body contact region with the source region.
In an embodiment of the present invention, the LDMOS device structure further includes: a first conductivity type doped region within the epitaxial layer; the first conductivity type doped region is adjacent to the first conductive via and connects the source region and the substrate, respectively.
In an embodiment of the present invention, the LDMOS device structure further includes a shielding conductor layer and a third insulating layer; the shielding conductor layer is positioned on the first insulating layer and is positioned above part of the grid structure and part of the second conductive type drift region; the third insulating layer covers an upper surface and side walls of the shield conductor layer, and covers an upper surface of the first insulating layer exposed by the shield conductor layer.
In an embodiment of the present invention, the second insulating layer is located above the first conductive via and the first insulating layer, and includes: the second insulating layer is located on the upper surface of the first conductive channel and the upper surface of the third insulating layer above the first insulating layer.
In one embodiment of the present invention, the first conductive via extends through the first insulating layer, the source region, and the epitaxial layer, and includes: the first conductive path extends sequentially through the third insulating layer, the first insulating layer, the source region, and the epitaxial layer
In an embodiment of the present invention, the second conductive channel extends to the drain region, and includes: the second conductive via extending into contact with the drain region, comprising: the second conductive channel extends through the second insulating layer, the third insulating layer and the first insulating layer in sequence, and the second conductive channel extends to contact the drain region.
The present invention provides in a second aspect a method for manufacturing an LDMOS device, comprising: providing a substrate of a first conductivity type, and forming an epitaxial layer of the first conductivity type on the surface of the substrate of the first conductivity type; forming a grid structure on the upper surface of the epitaxial layer; forming a first conductive type well region and a second conductive type drift region in the epitaxial layer respectively; forming a source region of a second conductivity type within the first conductivity type well region; wherein the first conductivity type is opposite the second conductivity type; forming an insulating layer over the upper surface of the epitaxial layer and the gate structure; forming a first trench extending through the substrate layer including the first insulating layer, the source region, and the epitaxial layer, and the first conductive via extending to contact the substrate to expose an upper surface of the substrate layer and an upper surface of the source region; filling a first conductive material in the first groove to form a first conductive channel; the first conductive channel is in contact with the upper surface of the source region, and the lower surface of the first conductive channel is in contact with the substrate to connect the source region and the substrate; forming a second insulating layer, wherein the second insulating layer is positioned above the first conductive channel and the first insulating layer; forming a second trench extending into the second conductivity type drift region; forming a second conductivity type drain region in the second conductivity type drift region exposed by the second trench; filling a second conductive material in the second groove to form a second conductive channel; the second conductive channel is connected with the drain region; forming a drain electrode and a gate electrode, connecting the drain electrode to the drain region through the second conductive channel, and connecting the gate electrode to the gate structure; and forming a source electrode, wherein the source electrode covers the surface of the substrate far away from the epitaxial layer.
In an embodiment of the present invention, the step of forming the first trench includes: forming the first trench with the first insulating layer as a mask, the first trench extending through the first insulating layer, the source region and the epitaxial layer, and the first conductive via extending into contact with the substrate to expose the substrate; the first insulating layer is anisotropically etched according to the thickness of the source region to expose the upper surface of the source region, and the width of the upper surface of the exposed source region is not greater than the width of the source region, so that the first trench and the gate structure are isolated based on the first insulating layer.
In an embodiment of the present invention, when the first insulating layer is etched, a width of the same-direction etching is controlled, so that a width of the first insulating layer between the upper portion of the first conductive channel and the gate structure is 0.1-0.3 um.
In an embodiment of the present invention, the manufacturing method further includes: after forming the first trench and before filling the first trench, a body contact region of a first conductivity type is formed in the substrate exposed by the first trench, such that after formation of the first conductive via, a connection between the body contact region of the first conductivity type and the source region is based on the first conductive via.
In an embodiment of the present invention, after forming the first trench and before filling the first trench, a first conductivity type doped region is formed adjacent to the first trench on the first insulator; the first conductivity type doped region connects the source region and the substrate.
In an embodiment of the present invention, the step of forming the first conductivity type doped region includes: and implanting ions of the first conductivity type into the side wall of the first insulator adjacent to the first groove at an angle of 0-7 degrees compared with the vertical direction.
In an embodiment of the present invention, the step of forming the second trench includes: and forming the second groove by taking the second insulating layer as a mask, wherein the second groove extends to be contacted with the drain region so as to expose the drain region, and the second groove comprises the second insulating layer and the first insulating layer.
In an embodiment of the present invention, the method for manufacturing an LDMOS device further includes, after forming the first insulating layer and before forming the first trench: forming a shielding conductor layer, wherein the shielding conductor layer is positioned on the upper surface of the first insulating layer; and etching the shield conductor layer to expose at least a portion of the second conductivity type drift region and a portion of the first insulating layer over the gate structure; a third insulating layer is formed covering the upper surface and the side walls of the shield conductor layer and covering the upper surface of the first insulating layer exposed by the shield conductor layer.
In an embodiment of the present invention, the step of forming the first trench includes: the third insulating layer is used as a mask to form the first groove, the first groove extends through the third insulating layer, the first insulating layer, the source region and the epitaxial layer, and the first groove extends to be in contact with the substrate so as to expose the substrate.
In an embodiment of the present invention, the step of forming the second trench includes: and forming a second groove by taking the second insulating layer as a mask, wherein the second groove extends to be contacted with the drain region so as to expose the drain region, and the second groove comprises the second insulating layer, a third insulating layer and the first insulating layer.
In an embodiment of the present invention, the step of forming the second insulating layer includes: a second insulating layer is formed, the second insulating layer being located on an upper surface of the first conductive via and over the first insulating layer.
As described above, according to the LDMOS device structure and the manufacturing method thereof provided by the invention, the first conductive channel is connected between the source region and the source metal layer, and the first conductive channel is in contact with the upper surface of the source region, so that the on-resistance of the source region can be reduced, the EAS capability is improved, and the overall performance of the device is enhanced.
Drawings
Fig. 1 shows a schematic cross-sectional view of a structure of an LDMOS device as described in the prior art;
fig. 2 is a schematic cross-sectional view of an LDMOS device structure according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of a gate structure according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of an LDMOS device structure according to another embodiment of the invention;
fig. 5 is a schematic cross-sectional view of an LDMOS device structure according to another embodiment of the invention;
fig. 6A to 6N are schematic cross-sectional views illustrating a device structure fabricated at various stages in an embodiment of the method for fabricating an LDMOS according to the present invention;
description of element reference numerals
201. Substrate of first conductivity type
202. Epitaxial layer of first conductivity type
203. Gate structure
203A gate dielectric layer
203B gate conductive layer
203C silicide layer
203D fourth insulating layer 203D
204. Well region of first conductivity type
205. Drift region of second conductivity type
206. Source region of second conductivity type
207. Drain region of second conductivity type
208. A first insulating layer
209. First conductive path
210. Second insulating layer
211. Second conductive path
212. Drain electrode
213. Source electrode
214. Shielded conductor layer
214A first horizontal portion of the shield conductor layer
214B shielding the first vertical portion of the conductor layer
Second horizontal portion of 214C shielding conductor layer
215. Third insulating layer
216. First groove
217. Body contact region of first conductivity type
218. Doped region of first conductivity type
220. Protruding eave
221. Second groove
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the spirit of the invention, and various modifications and adaptations of the invention may be made to the details of the present description based on various points of view and applications. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
The figures in which the relative doping concentrations are indicated next to the doping types "n" or "p" indicate "-" or "+" and the doped regions of the same relative doping concentration do not necessarily have the same absolute doping concentration; for example, two different "n" doped regions may have the same or different absolute doping concentrations.
It will be understood that when a layer, a region, or the like is referred to as being "on" or "over" another layer, another region, when describing the structure of the device, it can be directly on the other layer, another region, or additional layers or regions can be included between the device and the other layer, another region, or the like. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
In this application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" means extending in a direction substantially perpendicular to the depth direction of the trench; the term "vertical" refers to an orientation that is perpendicular to the first surface, arranged based on a normal direction parallel to the first surface of the semiconductor substrate or body.
In order to solve the technical problems in the prior art, the invention provides an LDMOS device structure. Referring to fig. 2, a schematic cross-sectional view of the LDMOS device structure is shown.
As shown in fig. 2, the LDMOS device structure includes: a substrate 201 of a first conductivity type; an epitaxial layer 202 of a first conductivity type on the upper surface of the substrate 201; a gate structure 203 located on the upper surface of the epitaxial layer 202; a well region 204 of the first conductivity type located in the epitaxial layer 202 and located at one side of the gate structure 203; a portion of the upper surface of the first conductivity-type well region 204 is in contact with the lower surface of the gate structure 203, and the width of the first conductivity-type well region 204 is greater than the width of the gate structure 203; a drift region 205 of the second conductivity type located within the epitaxial layer 202 and on the opposite side of the gate structure 203; the second conductivity-type drift region 205 and the first conductivity-type well region 204 may not be in contact; the second conductivity type is different from the first conductivity type; a source region 206 of a second conductivity type located within the well region 204 of the first conductivity type, and a portion of an upper surface of the source region 206 of the second conductivity type extending beyond a lower surface of the gate structure 203; the second conductivity type drain region 207 is located in the second conductivity type drift region 205; a first insulating layer 208 is located above the epitaxial layer 202 and the gate structure 203, covering the upper surface and both sidewalls of the gate structure 203, and the upper surface of the epitaxial layer 202; a first conductive via 209 extends down through the first insulating layer 208, the source region 206, and the epitaxial layer 202 in that order, and the first conductive via 209 extends to the substrate 201 layer; a lower surface of the first conductive via 209 is in contact with the substrate 201, and the first conductive via 209 is in contact with an upper surface of the source region 206 to connect the source region 206 with the substrate 201; a second insulating layer 210 is located on the upper surface of the first conductive via 209 and the upper surface of the first insulating layer 208; a second conductive via 211 extending through the second insulating layer 210 and the first insulating layer 208, and extending to the drain region 207; the lower surface of the second conductive channel 211 is connected with the drain region 207; a drain electrode 212 located on the upper surface of the second conductive path 211 and connected to the drain region 207 based on the second conductive path 211; a gate electrode (not shown) connected to the gate structure 203; and a source electrode 213 located on a surface of the substrate 201 remote from the epitaxial layer 202.
Specifically, as shown in fig. 2, the first conductive via 209 forms a protruding eave 220 with the upper surface contact region of the source region 206; based on the protruding eave 220, the first conductive channel 209 is divided into an upper portion and a lower portion, and then the width of the upper portion of the first conductive channel 209 is greater than the width of the lower portion of the first conductive channel 209, so that the contact area between the first conductive channel 209 and the upper surface of the source region 206 is increased, the contact resistance of the source region 206 can be further reduced while the crystal structure size of the device is not changed, and the performance of the product is improved.
It should be noted that, while the width of the upper portion of the first conductive channel 209 is greater than the width of the lower portion of the first conductive channel 209, the upper portion of the first conductive channel 209 is separated from the gate structure 203 by the first insulating layer 208, so as to avoid the connection between the source region 206 and the gate structure 203;
optionally, the width of the first insulating layer 208 between the upper sidewall of the first conductive channel 209 and the sidewall of the gate structure 203 is 0.1-0.3 um.
According to the LDMOS device structure provided by the invention, the first conductive channel 209 is connected between the source region 206 and the substrate 201, and the first conductive channel 209 is in contact with the upper surface of the source region 206, so that electron carriers can quickly and transversely migrate, the on-resistance of the source region 206 can be reduced, the EAS capability is improved, the overall performance of the LDMOS device is enhanced, and the stability of an LDMOS device system is improved.
The conductivity type in the present invention is determined by doping different types of impurity atoms in the neutral base, for example, doping a group five element (electron donating) such as nitrogen, phosphorus, arsenic into the silicon germanium semiconductor substrate 201 can form an N-type conductivity; p-type conductivity may be formed by incorporating a group iii element such as boron, aluminum, or the like (providing holes). As an example, in this embodiment, a P-type semiconductor substrate 201, such as a silicon substrate 201 doped with a group iii element such as boron, aluminum, or the like, may be used as the first conductivity type substrate 201, and at this time, the second conductivity type is N-type; of course, in another example, an N-type substrate 201 may be selected as the first conductive type substrate 201, and the second conductive type is P-type. The first conductivity type substrate 201 is a highly doped substrate 201 with a doping concentration of typically 10 19 cm -3 The above. The first conductivity type epitaxial layer 202 is a lightly doped epitaxial layer 202 having a doping concentration lower than that of the first conductivity type substrate 201, for example, 10 16 ～10 17 cm -3 。
In one or more embodiments, as shown in fig. 3, the gate structure 203 includes, from bottom to top, a gate dielectric layer 203A, a gate conductive layer 203B, a silicide layer 203C, and a fourth insulating layer 203D; wherein the gate dielectric layer 203A is located on the upper surface of the epitaxial layer 202 to isolate the epitaxial layer 202 from the gate conductor layer 203B; the gate conductive layer 203B is preferably a polysilicon layer because polysilicon is more resistant to high temperatures.
In one or more embodiments, as shown in fig. 4, a bottom portion of the first conductive via 209, i.e., a contact region between the substrate 201 and the first conductive via 209, is formed with a body contact region 217 of a first conductivity type; a body contact region 217 of the first conductivity type is located within the substrate 201 and is highly doped, illustratively at a doping concentration of 10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The first conductive via 209 is connected to theThe first conductivity type body contact region 217 and the source region 206 reduce the resistance of the epitaxial layer in the longitudinal direction compared to the conventional structure.
As shown in fig. 4, the device structure further includes vertically distributed first conductivity-type doped regions 218, wherein sidewalls of the first conductivity-type doped regions 218 are adjacent to sidewalls of the first conductive vias 209, an upper surface thereof contacts the source regions 206, extends through the first conductivity-type well regions 204 and the epitaxial layer 202, and the first conductivity-type doped regions 218 extend to the substrate 201; an upper surface of the first conductive type doped region 218 contacts the source region 206, and a lower surface of the first conductive type doped region 218 contacts the substrate 201 to connect the source region 206 and the substrate 201, thereby reducing a contact resistance of the source region 206.
As an example, the first conductive via 209 and the second conductive via 211 are filled with a multi-layer metal structure including Ti/TiN/W.
In one or more embodiments, as shown in fig. 5, the device structure further includes a shield conductor layer 214 and a third insulating layer 215; wherein the shielding conductor layer 214 includes a first horizontal portion 214A located above a portion of the gate structure 203, a vertical portion 214B located on a sidewall of the gate structure 203, and a second horizontal portion 214C located above the second conductivity type drift region 205; the third insulating layer 215 covering the upper surface and the sidewalls of the shielding conductor layer 214, and covering the upper surface of the first insulating layer 208 exposed by the shielding conductor layer 214; wherein the first insulating layer 208 exposed by the shielding conductor layer 214 includes: the first insulating layer 208 over the source region 206, a portion of the first insulating layer 208 over a portion of the gate structure 203 (a portion not covered by the shielding conductor layer 214), and a portion of the first insulating layer 208 over the second conductivity type drift region 205 (a portion not covered by the shielding conductor layer 214); in this embodiment, the first conductive via 209 extends through the third insulating layer 215, the first insulating layer 208, the source region 206, the first conductivity-type well region 204 and the epitaxial layer 202, and the first conductive via 209 extends to the substrate 201, i.e., the sidewall of the first conductive via 209 is in contact with the third insulating layer 215, the first insulating layer 208, the source region 206, the first conductivity-type well region 204 and the epitaxial layer 202; the second insulating layer 210 is located on the upper surface of the first conductive via 209 and the upper surface of the third insulating layer 215; and, the second conductive via 211 extends through the second insulating layer 210, the third insulating layer 215, and the first insulating layer 208, and the second conductive via 211 extends to the drain region 207; i.e., the sidewalls of the second conductive via 211 are in contact with the second insulating layer 210, the third insulating layer 215, and the first insulating layer 208. The surface electric field distribution is optimized by adding the shielding conductor layer 214, the breakdown voltage is improved, and the electric field near the grid electrode is reduced, so that the reliability of the LDMOS device can be improved; in addition, the first insulating layer 208 above the source region 206 is exposed in the shielding conductor layer 214, so that the sidewall of the first conductive channel 209 is easier to etch, and the etched sidewall has better effect.
The invention also provides a manufacturing method of the LDMOS device structure, which is used for manufacturing any one of the DMOS device structures in the above embodiments, so that the related description of the same structure in the above embodiments is also applicable to the present embodiment, and for the sake of brevity, the description of the same description is not repeated in the following embodiments.
Referring to fig. 6A to 6N, cross-sectional views of stages in a process of manufacturing an LDMOS device structure according to the present invention are shown.
As shown in fig. 6A, a substrate 201 of a first conductivity type is provided, and an epitaxial layer 202 of the same conductivity type is formed on the surface of the substrate 201; a gate dielectric layer 203A, a gate conductive layer 203B, a silicide layer 203C, and a fourth insulating layer 203D are sequentially formed on the surface of the epitaxial layer 202, so as to form a gate structure 203;
specifically, a first oxide layer is grown on the surface of the first conductivity type epitaxial layer 202 as a gate dielectric layer 203A, and a polysilicon layer, a metal silicide layer and a second oxide layer are sequentially deposited on the surface of the first oxide layer, which are respectively corresponding to the gate conductive layer 203B, the silicide layer 203C and the fourth insulating layer 203D; the gate structure 203 is formed by etching the layers.
As shown in fig. 6B, the epitaxial layer 202 on the opposite side of the gate structure 203 is subjected to ion implantation of a first conductivity type by a self-aligned process, and is subjected to high-temperature junction pushing to form a first conductivity type well region 204; performing ion implantation of a second conductivity type on the epitaxial layer 202 at one side of the gate structure 203, and performing high-temperature junction pushing to form a second conductivity type drift region 205; performing a heat treatment process such as annealing to diffuse the first conductivity type well region 204 in the epitaxial layer 202 so as to contact the second conductivity type drift region 205; and implanting ions of a second conductivity type into the surface of the first conductivity type well 204 to form a second conductivity type source region 206 in the first conductivity type well region 204, wherein the second conductivity type source region 206 is isolated from the second conductivity type drift region 205.
As shown in fig. 6C, the first insulating layer 208 is deposited on the upper surface of the epitaxial layer 202 and over the gate structure 203; optionally, the first insulating layer 208 is an oxide layer.
As shown in fig. 6D and 6E, a shielding conductor layer 214 is deposited on the upper surface of the first insulating layer 208, and an etching process is used to etch the shielding conductor layer 214, and expose the first insulating layer 208 above the source region 206, a portion of the first insulating layer 208 above the gate structure 203 (a portion not covered by the shielding conductor layer 214), and a portion of the first insulating layer 208 above the second conductivity type drift region 205 (a portion not covered by the shielding conductor layer 214); the etched shield conductor layer 214 serves as a field plate for the LDMOS device.
Optionally, the width of the first insulating layer 208 exposed above the source region 206 in the shielding conductor layer 214 may be determined according to the voltage withstanding requirement of the LDMOS device.
Optionally, the shielding conductor layer 214 is a doped polysilicon layer.
As shown in fig. 6F, a third insulating layer 215 is deposited over the shielding conductor layer 214 and the exposed upper surface of the first insulating layer 208, and then a chemical mechanical polishing process is performed on the surface of the third insulating layer 215;
optionally, the thickness of the third insulating layer 215 is 0.8-1.2 um;
optionally, the third insulating layer 215 is an oxide layer.
As shown in fig. 6G, the third insulating layer 215, the first insulating layer 208, the source region 206, the well region 204 of the first conductivity type and the epitaxial layer 202 are sequentially etched above the source region 206 until the etching reaches the upper surface of the substrate 201 to form a first trench 216; the width of the first trench 216 is not greater than the width of the source region 206; and the surface of the substrate 201 is exposed within the first trench 216.
Specifically, according to the width of the source region 206, the insulating layer is isotropically etched in a region of the first trench 216 located in the insulating layer (including the third insulating layer 215 and the first insulating layer 208) such that the source region 206 is exposed, and the exposed upper surface of the source region 206 has a width not greater than the width of the source region 206 such that the first trench 216 is isolated from the gate structure 203 by the insulating layer; after etching, the first trench 216 is still separated from the gate structure 203 based on the insulating layer.
As an example, when etching the insulating layer, the width of the lateral etching is controlled such that the thickness of the insulating layer between the upper portion of the first conductive via 209 and the gate structure 203 is 0.1 to 0.3um.
Optionally, as shown in fig. 6H, first conductivity type ions are implanted into the first trench 216 at a predetermined angle, so as to form a body contact region 217 of the first conductivity type in the substrate 201 exposed by the first trench 216, which is a high-concentration doped region; such that a connection between the body contact region 217 of the first conductivity type and the source region 206 is based on the first trench 216.
Optionally, a high-concentration doped region of the first conductivity type is formed in the epitaxial layer 202 (including the well region 204 of the first conductivity type) adjacent to the first trench 216; the first conductivity type doped region 218 connects the source region 206 with the substrate 201 with its sidewalls adjacent to the sidewalls of the first trench 216 to enhance the device EAS capability.
As an example, the implementation of implanting ions of the first conductivity type in the first trench 216 at a predetermined angle includes: the first conductivity type dopant is implanted into the sidewall of the epitaxial layer 202 (including the first conductivity type well region 204) adjacent to the first trench 216 at 0 to 7 ° compared to the vertical direction.
As shown in fig. 6I, the first trench 216 is filled with a first conductive material to form a first conductive channel 209, which extends downward through the insulating layer (including the third insulating layer 215 and the first insulating layer 208), the source region 206, the first conductivity-type well region 204, and the epitaxial layer 202 in this order, and the first trench 216 extends to the substrate 201; the lower surface of the first conductive via 209 contacts the substrate 201 to connect the source region 206 with the substrate 201; the first conductive via 209 forms a protruding eave 220 with the upper surface contact region of the source region 206; based on the protruding eave 220, the first conductive path 209 is divided into an upper portion and a lower portion, and the width of the upper portion of the first conductive path 209 is greater than the width of the lower portion of the first conductive path 209.
The first conductive material includes, but is not limited to, a metal compound such as tungsten silicide, titanium nitride, and the like.
As shown in fig. 6J, after the first conductive via 209 is formed, a second insulating layer 210 is formed on the upper surfaces of the first conductive via 209 and the third insulating layer 215, and a chemical mechanical polishing process is performed on the surface of the second insulating layer 210.
As shown in fig. 6K, the second insulating layer 210, the third insulating layer 215, and the first insulating layer 208 are sequentially etched above the second conductivity type drift region 205 using the second insulating layer 210 as a mask until the etching reaches the second conductivity type drift region 205, so as to form a second trench 221; in the second conductivity type drift region 205 exposed by the second trench 221, a second conductivity type drain region 207 is formed as a high concentration doped region.
The second trench 221 is filled with a second conductive material and etched back as shown in fig. 6L to form a second conductive channel 211, the second conductive channel 211 extending to the drain region 207 with a lower surface contacting the drain region 207 from extending down sequentially through the second insulating layer 210, the third insulating layer 215, and the first insulating layer 208.
Optionally, the second conductive material includes, but is not limited to, a metal compound, such as tungsten silicide, titanium nitride, and the like; and the second conductive material may be the same as or different from the first conductive material, which is not limited herein.
As shown in fig. 6M and 6N, a metal layer is deposited on the upper surface and the sidewall of the entire device, and the metal layer is etched to form a drain electrode 212 and a gate electrode (not shown) respectively, wherein the drain electrode 212 covers the upper surface including the second conductive path 211, so as to connect the drain region 207 and the drain electrode 212 through the second conductive path 211.
After the thinning process of the substrate 201, a source electrode 213 is deposited on the surface of the substrate 201 remote from the epitaxial layer 202.
It should be noted that when a chip product is formed based on the LDMOS device structure as described above, the source electrode 213 and the shielding conductive layer are connected at the edge of the chip so that the potentials of the source electrode 213 and the shielding conductive layer are the same, thereby enhancing the stability and reliability of the LDMOS device.
In one or more other embodiments, the shielding conductor layer 214 and the third insulating layer 215 may be omitted from the LDMOS device manufactured based on the manufacturing method of the LDMOS device structure. In this embodiment, the method may omit steps shown in fig. 6D to 6F, and directly perform steps shown in fig. 6G to 6N. Therefore, in this embodiment, the manufacturing method of fig. 6C to 6N may omit the shield conductor layer 214 and the third insulating layer 215 (not shown).
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations which can be accomplished by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.

Claims (20)

1. An LDMOS device structure comprising:
a substrate of a first conductivity type, an upper surface of which is formed an epitaxial layer of the first conductivity type;
the grid structure is positioned on the upper surface of the epitaxial layer;
the first conductive type well region and the second conductive type drift region are both positioned in the epitaxial layer, and the conductive types of the first conductive type well region and the second conductive type drift region are opposite;
the source region is of a second conductivity type and is positioned in the first conductivity type well region;
the drain region is of the first conductivity type and is positioned in the drift region of the second conductivity type;
the first insulating layer covers the upper surface and the two side walls of the grid structure and the upper surface of the epitaxial layer;
a first conductive via extending through the substrate including the first insulating layer, the source region, and the epitaxial layer, and extending into contact with the substrate; the first conductive channel is in contact with the upper surface of the source region to connect the source region and the substrate;
a second insulating layer over the first conductive via and the first insulating layer;
a second conductive path extending to contact the drain region;
a drain electrode connected to the drain region by connecting to the second conductive path;
a gate electrode connected to the gate structure; and
and a source electrode positioned on the surface of the substrate away from the epitaxial layer.
2. The LDMOS device structure of claim 1, wherein the first conductive via forms a protruding ledge with the upper surface contact region of the source region; based on the protruding eave, the first conductive channel is divided into an upper portion and a lower portion, and the width of the upper portion of the first conductive channel is larger than that of the lower portion of the first conductive channel.
3. The LDMOS device structure of claim 1 or 2, wherein an isolation between the upper portion of the first conductive channel and the gate structure is based on the first insulating layer, and an isolation width is 0.1-0.3 um.
4. The LDMOS device structure of claim 1, further comprising:
and a body contact region of a first conductivity type within the substrate, the first conductive via connecting the body contact region with the source region.
5. The LDMOS device structure of claim 4, further comprising: a first conductivity type doped region within the epitaxial layer; the first conductivity type doped region is adjacent to the first conductive via and connects the source region and the substrate, respectively.
6. The LDMOS device structure of claim 1, further comprising a shield conductor layer and a third insulating layer; the shielding conductor layer is positioned on the first insulating layer and is positioned above part of the grid structure and part of the second conductive type drift region; the third insulating layer covers an upper surface and a sidewall of the shield conductor layer, and covers an upper surface of the first insulating layer exposed by the shield conductor layer.
7. The LDMOS device structure of claim 6, wherein the second insulating layer is located over the first conductive channel and the first insulating layer, comprising: the second insulating layer is located on the upper surface of the first conductive channel and the upper surface of the third insulating layer above the first insulating layer.
8. The LDMOS device structure of claim 6, wherein the first conductive channel extends through the first insulating layer, the source region, and the epitaxial layer, comprising: the first conductive via extends sequentially through the third insulating layer, the first insulating layer, the source region, and the epitaxial layer.
9. The LDMOS device structure of claim 6, wherein the second conductive channel extends into contact with the drain region, comprising: the second conductive channel extends through the second insulating layer, the third insulating layer and the first insulating layer in sequence, and the second conductive channel extends to contact the drain region.
10. A method of fabricating an LDMOS device, comprising:
providing a substrate of a first conductivity type, and forming an epitaxial layer of the first conductivity type on the surface of the substrate of the first conductivity type;
forming a grid structure on the upper surface of the epitaxial layer;
forming a first conductive type well region and a second conductive type drift region in the epitaxial layer respectively;
forming a source region of a second conductivity type within the first conductivity type well region; wherein the first conductivity type is opposite to the second conductivity type;
forming an insulating layer over the upper surface of the epitaxial layer and the gate structure;
forming a first trench extending through the substrate layer including the first insulating layer, the source region, and the epitaxial layer, and extending into contact with the substrate to expose an upper surface of the substrate layer and an upper surface of the source region; filling a first conductive material in the first groove to form a first conductive channel; the first conductive channel is in contact with the upper surface of the source region, and the lower surface of the first conductive channel is in contact with the substrate to connect the source region and the substrate;
forming a second insulating layer, wherein the second insulating layer is positioned above the first conductive channel and the first insulating layer;
forming a second trench extending into the second conductivity type drift region; forming a second conductivity type drain region in the second conductivity type drift region exposed by the second trench; filling a second conductive material in the second groove to form a second conductive channel; the second conductive channel is connected with the drain region;
forming a drain electrode and a gate electrode, connecting the drain electrode to the drain region through the second conductive channel, and connecting the gate electrode to the gate structure; the method comprises the steps of,
and forming a source electrode, wherein the source electrode covers the surface of the substrate far away from the epitaxial layer.
11. The method of manufacturing an LDMOS device of claim 10, wherein the step of forming the first trench comprises:
forming the first trench with the first insulating layer as a mask, the first trench extending through the first insulating layer, the source region and the epitaxial layer, and the first conductive via extending into contact with the substrate to expose the substrate;
the first insulating layer is isotropically etched to expose an upper surface of the source region according to a thickness of the source region, and a width of the exposed upper surface of the source region is not greater than a width of the source region to isolate the first trench from the gate structure based on the first insulating layer.
12. The method of manufacturing an LDMOS device of claim 11, wherein a width of the first insulating layer is controlled to be 0.1-0.3 um between the upper portion of the first conductive via and the gate structure by controlling a width of the first insulating layer during the etching.
13. The method of manufacturing an LDMOS device of claim 10, further comprising:
after forming the first trench and before filling the first trench, a body contact region of a first conductivity type is formed in the substrate exposed by the first trench, such that after the first conductive channel is formed, a connection between the body contact region of the first conductivity type and the source region is based on the first conductive channel.
14. The method of manufacturing an LDMOS device of claim 13, further comprising:
forming a first conductive type doped region at a position adjacent to the first groove of the first insulating layer after the first groove is formed and before the first groove is filled; the first conductivity type doped region connects the source region and the substrate.
15. The method of manufacturing an LDMOS device of claim 14, wherein the step of forming a first conductivity type doped region comprises: and implanting ions of the first conductivity type into the side wall of the first insulator adjacent to the first groove at an angle of 0-7 degrees compared with the vertical direction.
16. The method of manufacturing an LDMOS device of claim 10, wherein the step of forming the second trench comprises: and forming the second groove by taking the second insulating layer as a mask, wherein the second groove extends to be contacted with the drain region so as to expose the drain region, and the second groove comprises the second insulating layer and the first insulating layer.
17. The method of manufacturing an LDMOS device according to claim 10, wherein after forming the first insulating layer, before forming the first trench, the method further comprises:
forming a shielding conductor layer, wherein the shielding conductor layer is positioned on the upper surface of the first insulating layer; and
etching the shield conductor layer to expose at least a portion of the second conductivity type drift region and a portion of the first insulating layer over the gate structure;
a third insulating layer is formed covering the upper surface and the side walls of the shield conductor layer and covering the upper surface of the first insulating layer exposed by the shield conductor layer.
18. The method of manufacturing an LDMOS device of claim 17, wherein the step of forming the first trench comprises:
the third insulating layer is used as a mask to form the first groove, the first groove extends through the third insulating layer, the first insulating layer, the source region and the epitaxial layer, and the first groove extends to be in contact with the substrate so as to expose the substrate.
19. The method of manufacturing an LDMOS device of claim 17, wherein the step of forming the second trench comprises: and forming a second groove by taking the second insulating layer as a mask, wherein the second groove extends to be contacted with the drain region so as to expose the drain region, and the second groove comprises the second insulating layer, a third insulating layer and the first insulating layer.
20. The method of manufacturing an LDMOS device of claim 17, wherein the step of forming the second insulating layer comprises: a second insulating layer is formed, the second insulating layer being located on an upper surface of the first conductive via and over the first insulating layer.
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