CN113809162B - Power element - Google Patents

Power element Download PDF

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Publication number
CN113809162B
CN113809162B CN202110480080.5A CN202110480080A CN113809162B CN 113809162 B CN113809162 B CN 113809162B CN 202110480080 A CN202110480080 A CN 202110480080A CN 113809162 B CN113809162 B CN 113809162B
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layer
dielectric layer
gate
field plate
conductor layer
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CN113809162A (en
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普佳·瑞凡卓·戴许曼
陈柏安
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a power element, comprising: an epitaxial layer having a trench extending from a first surface to a second surface of the epitaxial layer; the isolation field plate is positioned in the ditch; an insulating filling layer which is positioned in the ditch and surrounds the side wall and the bottom of the lower part of the isolation field plate; the first grid electrode and the second grid electrode are positioned in the ditch and positioned on the insulating filling layer; and a dielectric layer surrounding sidewalls of the first gate and the second gate, wherein a lower portion of the dielectric layer has a maximum width of the dielectric layer, and wherein the isolation field plate includes a first portion and a second portion, the first portion being adjacent to the lower portion of the dielectric layer and having a doping concentration greater than the second portion.

Description

Power element
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly to a power device.
Background
The power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a voltage-type control element, has a simple driving circuit, high driving power, high switching speed and high operating frequency, and is a switching element widely used for various electronic application elements.
A trench gate mosfet is a power mosfet in which the gate is buried in the substrate or epitaxial layer so that it has a vertical channel. The power metal oxide semiconductor field effect transistor has smaller cell size and small on-resistance, and is suitable for a power MOSFET with medium and low voltage.
Split gate trench gate (Split Gate Trench, SGT) MOSFET is a power MOSFET in which a single gate is split into two gates and the two gates are separated by a spacer. The isolation field plate deeper into the epitaxial layer increases the lateral depletion region (lateral depletion) and increases the N drift doping concentration (N-drift doping concentration). The spacer field plate may also reduce gate to drain overlap and thus gate to drain capacitance (gate-to-drain capacitance). Therefore, the structure has excellent performance in both static and dynamic characteristics.
However, since the SGT MOSFET is relatively complex in process, leakage current is easily generated between the gate and the isolation field plate, so that breakdown voltage of the device is insufficient. On the other hand, if the doping concentration of the epitaxial layer is reduced to reduce the leakage current between the gate and the isolation field plate, the on-resistance (Ron) increases, and the gate charge amount (QG) increases, thereby affecting the device performance.
Disclosure of Invention
The invention provides a power element which can reduce leakage current between a grid electrode and an isolation field plate, improve breakdown voltage of the element, reduce on-resistance, reduce grid electrode charge Quantity (QG), improve figure of merit (FOM) and improve efficiency of the element.
A power element of an embodiment of the present invention includes a power element including: an epitaxial layer having a trench extending from a first surface to a second surface of the epitaxial layer; a drain doped layer on the second surface of the epitaxial layer; the first substrate region and the second substrate region are positioned in the epitaxial layers at two sides of the ditch; the first source doped region and the second source doped region are respectively positioned in the first matrix region and the second matrix region; the isolation field plate is positioned in the ditch; an insulating filling layer which is positioned in the ditch and surrounds the side wall and the bottom of the lower part of the isolation field plate; a first gate and a second gate located in the trench and on the insulating fill layer, wherein the first gate is located between the isolation field plate and the first body region, and the second gate is located between the isolation field plate and the second body region; and a dielectric layer surrounding sidewalls of the first gate and the second gate, wherein a lower portion of the dielectric layer has a maximum width of the dielectric layer, and wherein the isolation field plate includes a first portion and a second portion, the first portion being adjacent to the lower portion of the dielectric layer and having a doping concentration greater than the second portion.
Based on the above, the bottom corner of the gate trench has a thick enough oxide layer, so that the leakage current between the gate and the isolation field plate can be reduced, and the breakdown voltage of the element can be improved. On the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge Quantity (QG), improve the quality Factor (FOM), and improve the performance of the device.
Drawings
Fig. 1A to 1J are schematic cross-sectional views of a method for manufacturing a power device according to a first embodiment of the present invention.
Fig. 2 is an enlarged schematic view of region R in fig. 1J.
Fig. 3A to 3E are schematic cross-sectional views illustrating a method for manufacturing a power device according to a second embodiment of the present invention.
Fig. 4A to 4E are schematic cross-sectional views illustrating a method for manufacturing a power device according to a third embodiment of the present invention.
Fig. 5A to 5D are schematic cross-sectional views illustrating a method for manufacturing a power device according to a fourth embodiment of the present invention.
Fig. 6 shows a schematic cross-sectional view of two cells of a power device.
Reference numerals:
10: substrate and method for manufacturing the same
12: drain doped layer
14: epitaxial layer
14a: a first surface
14b: a second surface
16: ditch groove
18. 18a: insulating filling layer
20. 20a, 20a', 20c, 31: conductor layer
20b: doped layer, doped region
20b', 20d: doped region
22: first gate trench
24: second gate trench
30. 46: dielectric layer
30a: first gate dielectric layer
30b: second gate dielectric layer
30c: a first insulating layer
30d: second insulating layer
30L: lower part
30U: upper part
32. 32': first grid electrode
34. 34': second grid electrode
36: first matrix region
38: second matrix region
42: first source doped region
44: second source doped region
52: first contact opening
54: second contact opening
62: first doped region
64. 64': second doped region
72: first contact window
74. 74': second contact window
C1, C1': unit cell
PL: isolation field plate
P1: first part
P2: second part
P3: third part
IMP 1, IMP 2, IMP3: ion implantation process
T min1 、T min2 : minimum thickness of
T max1 、T max2 : maximum thickness of
α1, α2, β1, β2: base angle
θ: included angle
Detailed Description
Fig. 1A to 1J are schematic cross-sectional views of a method for manufacturing a power device according to a first embodiment of the present invention. The power element is, for example, an SGT MOSFET.
Referring to fig. 1A, a method for fabricating a power device includes forming a drain doped layer 12 in a substrate 10. The substrate 10 may be a semiconductor substrate 10, such as a silicon substrate. The drain doped layer 12 may be formed in an in-situ (in-situ) dopant process at the time of wafer fabrication. The drain doped layer 12 has a dopant of the first conductivity type. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. Next, an epitaxial layer 14 is formed on the drain doped layer 12. The epitaxial layer 14 is formed by, for example, a selective epitaxial growth process. Epitaxial layer 14 has a dopant of the first conductivity type. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of epitaxial layer 14 is, for example, lower than the doping concentration of drain doped layer 12. The dopants of epitaxial layer 14 may be formed in situ (in-situ) during the selective epitaxial growth process or by an ion implantation process after the selective epitaxial growth process.
Thereafter, a trench 16 is formed in the epitaxial layer 14. Trenches 16 extend from first surface 14a to second surface 14b of epitaxial layer 14. Trenches 16 may be formed by photolithography and etching processes. The etching process may be an anisotropic etching process, an isotropic etching process, or a combination thereof. Thereafter, an insulating fill layer 18 and a conductor layer 20 are formed over the epitaxial layer 14 and within the trench 16. The material of the insulating filling layer 18 is, for example, silicon oxide, silicon nitride or a combination thereof formed by chemical vapor deposition. A conductor layer 20 is formed on the insulating fill layer 18 and fills the space remaining in the trench 16. The conductor layer 20 may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by chemical vapor deposition.
Referring to fig. 1B, an etching back process is performed on the conductor layer 20 to remove the conductor layer 20 outside the trench 16, so as to leave the conductor layer 20a in the trench 16. In some embodiments, the top surface of conductor layer 20a is lower than the top surface of epitaxial layer 14.
Referring to fig. 1C, a doped layer (or referred to as a doped region) 20b is formed on the conductive layer 20a or in the conductive layer 20a. The doped layer/doped region 20b has a dopant of the same conductivity type as the conductor layer 20a, for example a dopant of the first conductivity type. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the doped layer/doped region 20b is, for example, higher than the doping concentration of the conductor layer 20a. In some embodiments, the doping concentration of doped layer/doped region 20b is in the range of 5E18 1/cm 3 To 5E 20.sup.1/cm 3 . The thickness/depth of doped layer/region 20b greater than 1500 angstroms may facilitate control of a subsequent etch process to form the gate trench. The thickness/depth of doped layer/doped region 20b ranges, for example, from 1600 angstroms to 2500 angstroms.
In one embodiment, doped region 20b is located in conductor layer 20a. The doped region 20b is formed by, for example, performing an ion implantation process IMP 1 on the conductive layer 20a. The ion implantation process IMP 1 implants dopants into the conductor layer 20a in a manner that is perpendicular to the surface of the substrate 10. In another embodiment, doped layer 20b is located on conductor layer 20a. The doped layer 20b is formed, for example, by performing a chemical vapor deposition process in situ after the formation of the conductor layer 20a, so as to form the doped layer 20b having a concentration greater than that of the conductor layer 20a on the conductor layer 20a.
Then, referring to fig. 1D, a conductive layer 20c is formed on the doped layer/doped region 20b. The method for forming the conductor layer 20c is, for example, to form a conductor layer on the insulating filling layer 18 and the doped layer/doped region 20b, and then to perform an etching back process to remove the conductor layer outside the trench 16. The conductor layer 20c may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by chemical vapor deposition. The top surface of conductor layer 20c may be coplanar with first surface 14a of epitaxial layer 14 or lower than first surface 14a of epitaxial layer 14.
Thereafter, referring to fig. 1E, an etching back process is performed on the insulation filling layer 18, and the insulation filling layer 18 outside the trench 16 is removed to leave an insulation filling layer 18a in the trench 16. The insulating fill 18a surrounds the sidewalls and bottom surface of the conductor layer 20a and surrounds a portion of the sidewalls of the doped layer/region 20b, and the top surface of the insulating fill 18a is between the top and bottom surfaces of the doped region 20b. In other words, the insulating filling layer 18a has the first gate trench 22 and the second gate trench 24 thereon. The sidewalls of the first gate trench 22 and the second gate trench 24 expose the epitaxial layer 14, the conductor layer 20c, and a portion of the doped region 20b, and the bottom surfaces of the first gate trench 22 and the second gate trench 24 expose the top surface of the insulating fill layer 18a. The etch-back process is, for example, an anisotropic etch process, an isotropic etch process, or a combination thereof.
Referring to fig. 1F, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductor layer 20c and in the first gate trench 22 and the second gate trench 24. The dielectric layer 30 may be silicon oxide formed by thermal oxidation or chemical vapor deposition. In some embodiments in which dielectric layer 30 is a silicon oxide layer formed by thermal oxidation, doped region 20b has a doping concentration that is greater than the doping concentration of epitaxial layer 14, and doped region 20b is more susceptible to oxidation than epitaxial layer 14. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the doped region 20b is larger than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the epitaxial layer 14. In addition, since the doping concentration of the doped region 20b is greater than that of the conductor layer 20c, the doped region 20b is easier to oxidize than the conductor layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the doped region 20b is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20c, which will be described later with reference to fig. 2.
Referring to fig. 1G, a conductive layer 31 is formed on the dielectric layer 30. The conductor layer 31 fills the space left between the first gate trench 22 and the second gate trench 24. The conductor layer 31 may be a semiconductor material, such as doped polysilicon formed by chemical vapor deposition.
Referring to fig. 1H, the conductor layer 31 is etched back, and the conductor layer 31 outside the first gate trench 22 and the second gate trench 24 is removed to form a first gate 32 and a second gate 34 in the first gate trench 22 and the second gate trench 24. The top surfaces of the first gate 32 and the second gate 34 may be coplanar with the first surface 14a of the epitaxial layer 14 or lower than the first surface 14a of the epitaxial layer 14.
With continued reference to fig. 1H, a first body region 36 and a second body region 38 are formed in the epitaxial layer 14 on both sides of the trench 16. First body region 36 and second body region 38 extend from first surface 14a to second surface 14b of epitaxial layer 14. The first body region 36 and the second body region 38 have dopants of a second conductivity type, such as P-type dopants. The P-type dopant is, for example, boron or boron trifluoride. The first body region 36 and the second body region 38 are formed by ion implantation, for example. In another embodiment, first body region 36 and second body region 38 may be formed prior to forming trench 16. For example, the first body region 36 and the second body region 38 may be formed in-situ (in-situ) during the selective epitaxial growth process for forming the epitaxial layer 14, or may be formed by an ion implantation process after the selective epitaxial growth process.
Then, first source doped region 42 and second source doped region 44 are formed in first body region 36 and second body region 38, respectively. A first source doped region 42 and a second source doped region 44. Having a dopant of a first conductivity type, such as an N-type dopant. The N-type dopant is, for example, phosphorus or arsenic. The first source doped region 42 and the second source doped region 44 are formed by ion implantation, for example.
Referring to fig. 1I, a dielectric layer 46 is formed on the epitaxial layer 14 to cover the first source doped region 42, the second source doped region 44, the first gate 32, the second gate 34 and the dielectric layer 30. Dielectric layer 46 is, for example, borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, or a combination thereof, formed by chemical vapor deposition. Then, photolithography and etching processes are performed to form a first contact opening 52 and a second contact opening 54 in the dielectric layer 46, so as to expose the first source doped region 42 and the second source doped region 44, respectively. Thereafter, first doped region 62 and second doped region 64 are formed in first body region 36 and second body region 38, respectively. The first doped region 62 and the second doped region 64 have dopants of the second conductivity type. The dopant of the second conductivity type may be a P-type dopant, such as boron or boron trifluoride. The first doped region 62 and the second doped region 64 are formed by ion implantation, for example.
Referring to fig. 1J, after that, a first contact 72 contacting the first doped region 62 and a second contact 74 contacting the second doped region 64 are formed in the first contact opening 52 and the second contact opening 54, respectively, and the first contact 72 and the second contact 74 are electrically connected to each other. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include electrically connecting the first gate 32 with the second gate 34, and so on.
Referring to fig. 1J, in the present embodiment, the conductor layer 20a, the doped layer/doped region 20b and the conductor layer 20c may be collectively referred to as a source polysilicon layer or an isolation field plate PL. The isolation field plate PL can uniformly distribute the electric field of the epitaxial layer 14 under the first body region 36 and the second body region 38, so that the peak electric field intensity is reduced, and thus the breakdown voltage can be increased. On the other hand, at the same breakdown voltage, the doping concentration of epitaxial layer 14 may be increased to reduce the on-resistance (Ron).
Further, in the present embodiment, the isolation field plate PL includes a first portion P1 and a second portion P2. Doped layer/region 20b is a first portion P1 of isolation field plate PL; the conductor layer 20a and the conductor layer 20c may be collectively referred to as a second portion P2 of the isolation field plate PL. The first portion P1 is sandwiched between the second portion P2, and the doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2.
Since the first portion P1 of the isolation field plate PL having a higher concentration in the present embodiment is exposed by the first gate trench 22 and the second gate trench 24, the bottoms of the first gate trench 22 and the second gate trench 24 are higher than the bottom of the first portion P1 (as shown in fig. 1E). Therefore, the first portion P1 having a higher concentration facilitates the formation of a thicker silicon oxide layer during the subsequent thermal oxidation process for forming the dielectric layer 30, and thus, more of the first portion P1 is oxidized. Thus, after the dielectric layer 30 is formed, the first portion P1 is the narrowest in width in the isolation field plate PL between the top and bottom surfaces of the first gate trench 22 and the second gate trench 24, as shown in fig. 1F and 2.
Fig. 2 shows an enlarged schematic view of region R in fig. 1J. Referring to fig. 2, the dielectric layer 30 between the epitaxial layer 14 and the first gate 32 is referred to as a first gate dielectric layer 30a. The dielectric layer 30 between the epitaxial layer 14 and the second gate 34 is referred to as a second gate dielectric layer 30b. The dielectric layer 30 between the isolation field plate PL and the first gate electrode 32 is referred to as a first insulating layer 30c. The dielectric layer 30 between the isolation field plate PL and the second gate 34 is referred to as a second insulating layer 30d.
The first portion P1 (doped layer/doped region 20 b) of the isolation field plate PL is adjacent to and in contact with the first insulating layer 30c and the lower portion 30L of the second insulating layer 30d. In the isolation field plate PL, a second portion P2 (conductor layer 20 c) above the first portion P1 is adjacent to and in contact with the first insulating layer 30c and the upper portion 30U of the second insulating layer 30d.
Since the first portion P1 having a higher concentration contributes to the formation of a thicker silicon oxide layer, the lower portions 30L of the first and second insulating layers 30c and 30d are the maximum thickness T of the first and second insulating layers 30c and 30d max1 、T max2 Where it is. In addition, although the first insulating layer 30c and the second insulating layer 30d between the bottom surface of the first gate electrode 32 and the first portion P1 (doped layer/doped region 20 b) of the isolation field plate PL have the minimum thickness T min1 、T min2 However, this minimum thickness T min1 Ratio to the average thickness of the first insulating layer 30c, and minimum thickness T min2 The ratio to the average thickness of the second insulating layer 30d is still greater than 0.8. In one embodiment, the average thickness of the first insulating layer 30c and the second insulating layer 30d is about 900 angstroms, wherein the maximum thickness T of the lower portion 30L max1 、T max2 About 1600 angstroms, minimum thickness T of lower portion 30L min1 、T min2 About 800 angstroms.
Since the lower portion 30L of the dielectric layer 30 (the first insulating layer 30c and the second insulating layer 30 d) in contact with the first gate electrode 32 and the second gate electrode 34 has a thick and sufficiently thick thickness, leakage currents between the first gate electrode 32 and the isolation field plate PL and between the second gate electrode 34 and the isolation field plate PL can be reduced, and breakdown voltage of the element can be improved.
Fig. 3A to 3E are schematic cross-sectional views illustrating a method for manufacturing a power device according to a second embodiment of the present invention.
Referring to fig. 3A, after the conductive layer 20a is formed in the trench 16 according to the method described in the first embodiment, two doped regions 20b' are formed in the conductive layer 20a. The doped region 20b 'is formed in an edge region of the conductor layer 20a, and a central region of the conductor layer 20a is not formed with the doped region 20b'. The doped region 20b' has a dopant of the same conductivity type as the conductor layer 20a, for example, a dopant of the first conductivity type. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the doped region 20b' is higher than the doping concentration of the conductor layer 20a. In some embodiments, the doping concentration of doped region 20b' ranges from 5E18 1/cm 3 To 5E 20.sup.1/cm 3 . Method for forming doped region 20bSuch as by performing a tilted ion implantation process IMP 2 on the conductor layer 20a. The angle θ between the inclined ion implantation process IMP 2 and the normal direction of the surface of the substrate 10 is, for example, in the range of 30 degrees to 60 degrees.
Thereafter, referring to fig. 3B, a conductive layer 20c is formed on the conductive layer 20a and the doped region 20B' according to the method described in the first embodiment. In the present embodiment, the conductor layer 20a, the doped region 20b' and the conductor layer 20c may be collectively referred to as a source polysilicon layer or an isolation field plate PL. The isolation field plate PL may include a first portion P1 and a second portion P2. The first portion P1 comprises two separate unconnected doped regions 20b'. The second portion P2 includes a conductor layer 20a and a conductor layer 20c connected to each other, and separates two doped regions 20b' from each other. The doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2.
Referring to fig. 3C, an etching back process is performed on the insulation filling layer 18 according to the method described in the first embodiment, so as to leave an insulation filling layer 18a in the trench 16, and a first gate trench 22 and a second gate trench 24 are formed on the insulation filling layer 18a. The bottom surfaces of the first gate trench 22 and the second gate trench 24 have a height between the top surfaces and the bottom surfaces of the two doped regions 20b'.
Thereafter, referring to fig. 3D, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductor layer 20c and in the first gate trench 22 and the second gate trench 24 according to the method described in the first embodiment. Likewise, since the doping concentration of the doped region 20b 'is greater than the doping concentration of the conductor layer 20c and greater than the doping concentration of the epitaxial layer 14, the doped region 20b' is more susceptible to oxidation than the conductor layer 20c and the epitaxial layer 14. Therefore, the thickness of the dielectric layer 30 formed on the surface of the doped region 20b' is greater than the thickness of the dielectric layer 30 formed on the surface of the conductor layer 20c, and the thickness of the dielectric layer 30 formed on the surface of the conductor layer 20c is greater than the thickness of the dielectric layer 30 formed on the surface of the epitaxial layer 14.
Thereafter, referring to fig. 3E, a subsequent process is performed according to the method described in the first embodiment until the first contact hole 72 and the second contact hole 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include electrically connecting the first gate 32 with the second gate 34, and so on.
Fig. 4A to 4E are schematic cross-sectional views illustrating a method for manufacturing a power device according to a third embodiment of the present invention.
Referring to fig. 4A, a conductive layer 20a' is formed in the trench 16 according to the method of forming the conductive layer 20a according to the first embodiment. However, in the present embodiment, the conductor layer 20a' is doped polysilicon having a higher concentration. In one embodiment, the doping concentration of the conductor layer 20a' is in the range of 1E19 1/cm 3 To 5E 20.sup.1/cm 3 。
Thereafter, a mask layer 19 is formed on the surface of the edge region of the conductor layer 20a'. The mask layer 19 exposes the surface of the central region of the conductor layer 20a'. The mask layer 19 may be a patterned photoresist layer covering the surface and sidewalls of the insulating fill layer 19 and the surface of the edge region of the conductor layer 20a'. The mask layer 19 has an opening exposing the surface of the central region of the conductor layer 20a'. The mask layer 19 may be a spacer, which covers only the sidewall of the insulating filling layer 19 and the surface of the edge region of the conductor layer 20a'. The spacer material may be silicon oxide, silicon nitride, or a combination thereof. The spacer forming method may first form the spacer material layer and then perform the anisotropic etching process.
The ion implantation process IMP3 is performed on the conductor layer 20a ', and a doped region 20d is formed in the conductor layer 20a'. The doped region 20d and the conductive layer 20a' may have dopants of the same or different conductivity types.
In an embodiment in which the doped region 20d has a dopant of the same conductivity type as the conductor layer 20a ', the doping concentration of the doped region 20d is lower than the doping concentration of the conductor layer 20a'. The doped region 20d may be implanted with dopants in the conductor layer 20a' perpendicular to the surface of the substrate 10 by using an ion implantation process IMP 3. The ion implantation process IMP3 is, for example, to implant a second conductive type dopant different from the first conductive type dopant of the conductive layer 20a ' into the conductive layer 20a ', and to make the doping concentration of the formed doped region 20d lower than that of the conductive layer 20a ' by mutual compensation of the dopants. The dopant of the second conductivity type is a P-type dopant, such as boron or tri-type dopantBoron fluoride. The doping concentration of the doped region 20d is in the range of 5E18 1/cm 3 To 1E20 1/cm 3 。
In an embodiment in which the doped region 20d and the conductive layer 20a 'have different conductive types, the ion implantation process IMP3 may be used to implant the dopant into the conductive layer 20a' perpendicularly to the surface of the substrate 10 to form the doped region 20d. The ion implantation process IMP3 is, for example, to implant a second conductive type dopant different from the first conductive type dopant of the conductive layer 20a 'and having a higher doping concentration than the conductive layer 20a' into the conductive layer 20a ', so that the conductive type of the dopant of the formed doped region 20d is different from the conductive type of the dopant of the conductive layer 20a'. The dopant of the second conductivity type is a P-type dopant, such as boron or boron trifluoride. The doping concentration of the doped region 20d is in the range of 5E19 1/cm 3 To 8E20 1/cm 3 。
Referring to fig. 4B, the mask layer 19 is removed. The mask layer 19 may be removed by ashing or etching. Thereafter, a conductor layer 20c is formed on the doped region 20d and the conductor layer 20a' according to the method described in the first embodiment. In the present embodiment, the conductor layer 20a', the doped region 20d, and the conductor layer 20c may be collectively referred to as a source polysilicon layer or an isolation field plate PL.
The isolation field plate PL may include a first portion P1, a second portion P2, and a third portion P3. The doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2 and greater than the doping concentration of the third portion P3. The first portion P1 includes a conductor layer 20a'; the second portion P2 includes a doped region 20d; the third portion includes a conductor layer 20c. The side wall and the bottom of the second portion P2 are surrounded by the first portion P1, and the third portion P3 covers the top surfaces of the first portion P1 and the second portion P2.
Referring to fig. 4C, an etching back process is performed on the insulation filling layer 18 according to the method described in the first embodiment, so as to leave an insulation filling layer 18a in the trench 16, and a first gate trench 22 and a second gate trench 24 are formed on the insulation filling layer 18a. The bottom surfaces of the first gate trench 22 and the second gate trench 24 are lower than the top surface of the conductor layer 20a ', so that the sidewalls of the first gate trench 22 and the second gate trench 24 expose the conductor layer 20c and a portion of the conductor layer 20a'.
Thereafter, referring to fig. 4D, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductor layer 20c and in the first gate trench 22 and the second gate trench 24 according to the method described in the first embodiment. Since the doping concentration of the conductor layer 20a 'is greater than that of the conductor layer 20c, the conductor layer 20a' is more susceptible to oxidation than the conductor layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20a' is larger than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20c. The doped region 20d is less susceptible to oxidation than the conductor layer 20a ', so that the isolation field plate PL can maintain a sufficient width, and the characteristics of the power element are not affected because the conductor layer 20a' becomes too thin due to excessive oxidation. In addition, it is ensured that the dielectric layers on the left and right sides are not connected to each other by excessive oxidation of the conductor layer 20a', and if the dielectric layers (oxide layers) 30 on the left and right sides are connected, the isolation field plate PL is disconnected.
Thereafter, referring to fig. 4E, a subsequent process is performed according to the method described in the first embodiment until the first contact hole 72 and the second contact hole 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include electrically connecting the first gate 32 with the second gate 34, and so on.
Fig. 5A to 5D are schematic cross-sectional views illustrating a method for manufacturing a power device according to a fourth embodiment of the present invention.
Referring to fig. 5A, according to the method for forming the conductive layer 20a of the first embodiment, the conductive layer 20a 'is formed in the trench 16, but in this embodiment, the conductive layer 20a' is doped polysilicon with a higher concentration. In one embodiment, the doping concentration of the conductive layer 20a' is in the range of 5E19 1/cm 3 To 8E20 1/cm 3 。
Thereafter, the conductor layer 20c is formed on the conductor layer 20a' in accordance with the method described in the first embodiment. The conductive layer 20c and the conductive layer 20a' have the same conductive type dopant, for example, the first conductive type dopant. The doping concentration of the conductor layer 20c is lower than that of the conductor layer 20a'. The method for forming the conductor layer 20c is, for example, to perform a chemical vapor deposition process in situ after forming the conductor layer 20a ', but to reduce the concentration of the doped gas so as to form the conductor layer 20c having a concentration lower than that of the conductor layer 20a ' on the conductor layer 20a '. The doping concentration of the conductor layer 20c is, for example, 2/3 to 1/2 of the doping concentration of the conductor layer 20a'.
In this embodiment, the conductor layer 20a' and the conductor layer 20c may be collectively referred to as a source polysilicon layer or an isolation field plate PL. The conductor layer 20a' is a first portion P1 of the isolation field plate PL; the conductor layer 20c is the second portion P2 of the isolation field plate PL. The doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2. The second portion P2 covers the top surface of the first portion P1.
Referring to fig. 5B, an etching back process is performed on the insulation filling layer 18 according to the method described in the first embodiment, so as to leave an insulation filling layer 18a in the trench 16, and a first gate trench 22 and a second gate trench 24 are formed on the insulation filling layer 18a. The bottom surfaces of the first gate trench 22 and the second gate trench 24 are lower than the top surface of the conductor layer 20a ', so that the sidewalls of the first gate trench 22 and the second gate trench 24 expose the conductor layer 20c and a portion of the conductor layer 20a'.
Referring to fig. 5C, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductor layer 20C and in the first gate trench 22 and the second gate trench 24 according to the method described in the first embodiment. Since the doping concentration of the conductor layer 20a 'is greater than that of the conductor layer 20c, the conductor layer 20a' is more susceptible to oxidation than the conductor layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20a' is larger than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20c.
Thereafter, referring to fig. 5D, a subsequent process is performed according to the method described in the first embodiment until the first contact hole 72 and the second contact hole 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include electrically connecting the first gate 32 with the second gate 34, and so on.
Fig. 1J, 3E, 4E, and 5D above illustrate one cell of an SGT MOSFET, respectively. However, the invention is not limited thereto. In some embodiments, the SGT MOSFET may have two cells C1 and C1', as shown in FIG. 6. In fig. 6, the unit of fig. 1J is taken as an example, but the invention is not limited thereto. Reference numerals for similar or identical components in the units C1' and C1 are denoted by the same numerals, and the numerals are followed by the numerals "prime". For example, the second doped regions 64', similar to the second doped regions 64, are dopants of the second conductivity type.
The cells C1 and C1 'are adjacent to each other, and the first body region 36 and the first doped region 62 are shared by the cells C1 and C1'. In addition, the first doped region 62, the second doped region 64, and the second doped region 64 'are electrically connected to each other through the first contact window 72 and the second contact windows 74, 74'. The first and second gates 32 and 34 of the cell C1 and the first and second gates 32' and 34' of the cell C1' may be electrically connected to each other.
In other embodiments, the SGT MOSFETs may have more cells and the cells may be arranged in an array. In other words, the SGT MOSFET may have multiple gates, multiple source doped regions and multiple drain doped regions. The gates, sources and drains may be arranged in an array, and the gates, source doped regions and drain doped regions may be connected together by interconnects to form a gate terminal, a source terminal and a drain terminal
In summary, the isolation field plate with high doping concentration is exposed at the lower side wall of the gate trench, so that a thick oxide layer can be formed at the bottom corner of the gate trench, thereby reducing the leakage current between the gate and the source and improving the breakdown voltage of the device. On the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (QG), improve the figure of merit (FOM), and improve the device performance.

Claims (10)

1. A power element, comprising:
an epitaxial layer having a trench extending from a first surface to a second surface of the epitaxial layer;
a drain doped layer on the second surface of the epitaxial layer;
the first substrate region and the second substrate region are positioned in the epitaxial layers at two sides of the ditch;
the first source doped region and the second source doped region are respectively positioned in the first matrix region and the second matrix region;
the isolation field plate is positioned in the ditch;
an insulating filling layer which is positioned in the ditch and surrounds the side wall and the bottom of the lower part of the isolation field plate;
a first gate and a second gate located in the trench and on the insulating fill layer, wherein the first gate is located between the isolation field plate and the first body region, and the second gate is located between the isolation field plate and the second body region; and
a dielectric layer surrounding the sidewalls of the first and second gates, wherein the lower part of the dielectric layer has the maximum width of the dielectric layer, and
wherein the isolation field plate includes a first portion and a second portion, the first portion being adjacent to the lower portion of the dielectric layer and having a doping concentration greater than that of the second portion.
2. The power element of claim 1, wherein the first portion is a doped layer sandwiched between the second portion.
3. The power element of claim 1, wherein the first portion comprises two unconnected doped regions separated by the second portion.
4. The power device of claim 1, wherein the isolation field plate further comprises a third portion having a lower doping concentration than the first portion and covering top surfaces of the first portion and the second portion, and wherein sidewalls and bottom portions of the second portion are surrounded by the first portion.
5. The power element of claim 1, wherein the second portion is located on the first portion and covers a top surface of the first portion.
6. The power element of claim 1, wherein a bottom surface of the first portion is higher than a bottom surface of the dielectric layer.
7. The power element of claim 1, wherein a top surface of the first portion is higher than a bottom surface of the dielectric layer.
8. The power element of claim 1, wherein the maximum width of the dielectric layer is greater than an average width of the dielectric layer.
9. The power element of claim 1, wherein the isolation field plate has a minimum width of a dielectric layer corresponding to the lower portion of the dielectric layer.
10. The power element according to claim 9, wherein a ratio of the minimum width of the dielectric layer to an average width of the dielectric layer is 0.8 or more.
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