CN113809162A - Power element - Google Patents

Power element Download PDF

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Publication number
CN113809162A
CN113809162A CN202110480080.5A CN202110480080A CN113809162A CN 113809162 A CN113809162 A CN 113809162A CN 202110480080 A CN202110480080 A CN 202110480080A CN 113809162 A CN113809162 A CN 113809162A
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layer
dielectric layer
gate
field plate
trench
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CN202110480080.5A
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CN113809162B (en
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普佳·瑞凡卓·戴许曼
陈柏安
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention provides a power element including: an epitaxial layer having a trench extending from a first surface to a second surface of the epitaxial layer; an isolated field plate located in the trench; the insulating filling layer is positioned in the trench and surrounds the side wall and the bottom of the lower part of the isolation field plate; the first grid and the second grid are positioned in the trench and positioned on the insulating filling layer; and a dielectric layer surrounding sidewalls of the first and second gates, wherein a lower portion of the dielectric layer has a maximum width of the dielectric layer, and wherein the isolated field plate comprises a first portion and a second portion, the first portion being adjacent to the lower portion of the dielectric layer and having a doping concentration greater than the second portion.

Description

Power element
Technical Field
The present invention relates to the field of semiconductor device technology, and more particularly, to a power device.
Background
A power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a voltage-type control element, has a simple driving circuit, high driving power, high switching speed, and high operating frequency, and is a switching element widely used for various electronic application elements.
A trench gate mosfet is a power mosfet in which the gate is buried in a substrate or an epitaxial layer so that it has a vertical channel. The power metal oxide semiconductor field effect transistor has smaller unit size and small on-resistance, and is suitable for a power MOSFET of medium and low voltage.
Split Gate Trench (SGT) MOSFETs are power MOSFETs in which a single Gate is Split into two gates and the two gates are separated by an isolation field plate. The isolation field plate deep into the epitaxial layer can increase the lateral depletion region (lateral depletion) and increase the N-drift doping concentration (N-drift doping concentration). The isolated field plate may also reduce gate-to-drain capacitance (gate-to-drain capacitance) by reducing gate-to-drain overlap. Thus, the structure has excellent performance in both static and dynamic characteristics.
However, since the process of the SGT MOSFET is complicated, leakage current is easily generated between the gate and the isolated field plate, so that the breakdown voltage of the device is insufficient. On the other hand, if the doping concentration of the epitaxial layer is reduced to reduce the leakage current between the gate and the isolation field plate, the on-resistance (Ron) is increased, the gate charge (QG) is increased, and the performance of the device is affected.
Disclosure of Invention
The invention provides a power element which can reduce leakage current between a grid and an isolation field plate, improve breakdown voltage of the element, reduce on-resistance, reduce grid charge Quantity (QG), improve quality Factors (FOM) and improve efficiency of the element.
A power element of an embodiment of the present invention includes a power element including: an epitaxial layer having a trench extending from a first surface to a second surface of the epitaxial layer; a drain doping layer located on the second surface of the epitaxial layer; the first substrate area and the second substrate area are positioned in the epitaxial layers on two sides of the ditch; the first source electrode doping area and the second source electrode doping area are respectively positioned in the first base area and the second base area; an isolated field plate located in the trench; the insulating filling layer is positioned in the trench and surrounds the side wall and the bottom of the lower part of the isolation field plate; a first gate and a second gate in the trench and on the insulating fill layer, wherein the first gate is between the isolated field plate and the first substrate region and the second gate is between the isolated field plate and the second substrate region; and a dielectric layer surrounding sidewalls of the first and second gates, wherein a lower portion of the dielectric layer has a maximum width of the dielectric layer, and wherein the isolated field plate comprises a first portion and a second portion, the first portion being adjacent to the lower portion of the dielectric layer and having a doping concentration greater than the second portion.
Based on the above, the gate trench has the sufficiently thick oxide layer at the bottom corner, so that the leakage current between the gate and the isolation field plate can be reduced, and the breakdown voltage of the device can be improved. On the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (QG), improve the quality Factor (FOM), and improve the performance of the device.
Drawings
Fig. 1A to fig. 1J are schematic cross-sectional views illustrating a manufacturing method of a power device according to a first embodiment of the invention.
Fig. 2 is an enlarged schematic view of the region R in fig. 1J.
Fig. 3A to fig. 3E are schematic cross-sectional views illustrating a manufacturing method of a power device according to a second embodiment of the invention.
Fig. 4A to 4E are schematic cross-sectional views illustrating a manufacturing method of a power device according to a third embodiment of the invention.
Fig. 5A to 5D are schematic cross-sectional views illustrating a manufacturing method of a power device according to a fourth embodiment of the invention.
FIG. 6 is a cross-sectional view of two units of the power device.
Reference numerals:
10: substrate
12: drain doped layer
14: epitaxial layer
14 a: first surface
14 b: second surface
16: ditch (Trench)
18. 18 a: insulating filling layer
20. 20a, 20 a', 20c, 31: conductive layer
20 b: doped layer, doped region
20 b', 20 d: doped region
22: first gate trench
24: second gate trench
30. 46: dielectric layer
30 a: a first gate dielectric layer
30 b: a second gate dielectric layer
30 c: a first insulating layer
30 d: a second insulating layer
30L: lower part
30U: upper part
32. 32': a first grid electrode
34. 34': second grid
36: a first substrate region
38: a second substrate region
42: first source doped region
44: second source electrode doped region
52: first contact window opening
54: second contact window opening
62: first doped region
64. 64': second doped region
72: first contact window
74. 74': second contact window
C1, C1': unit cell
PL: isolated field plate
P1: the first part
P2: the second part
P3: third part
IMP 1, IMP 2, IMP 3: ion implantation process
Tmin1、Tmin2: minimum thickness
Tmax1、Tmax2: maximum thickness
α 1, α 2, β 1, β 2: bottom corner
θ: included angle
Detailed Description
Fig. 1A to fig. 1J are schematic cross-sectional views illustrating a manufacturing method of a power device according to a first embodiment of the invention. The power element is, for example, an SGT MOSFET.
Referring to fig. 1A, a method for manufacturing a power device includes forming a doped drain layer 12 in a substrate 10. The substrate 10 may be a semiconductor substrate 10, such as a silicon substrate. The drain doping layer 12 may be formed in an in-situ (in-situ) dopant process at wafer fabrication. The drain doping layer 12 has a first conductive type dopant. The first conductive type dopant is an N-type dopant, such as phosphorus or arsenic. Next, an epitaxial layer 14 is formed on the drain doped layer 12. The epitaxial layer 14 is formed, for example, by a selective epitaxial growth process. The epitaxial layer 14 has a dopant of the first conductivity type. The first conductive type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of epitaxial layer 14 is, for example, lower than the doping concentration of drain doped layer 12. The dopant of the epitaxial layer 14 may be formed in-situ during the selective epitaxial growth process or by an ion implantation process after the selective epitaxial growth process.
Thereafter, trenches 16 are formed in epitaxial layer 14. The trenches 16 extend from the first surface 14a to the second surface 14b of the epitaxial layer 14. The trenches 16 may be formed by photolithography and etching processes. The etching process may be an anisotropic etching process, an isotropic etching process, or a combination thereof. Thereafter, an insulating fill layer 18 and a conductive layer 20 are formed on the epitaxial layer 14 and in the trenches 16. The material of the insulating filling layer 18 is, for example, silicon oxide, silicon nitride or a combination thereof formed by chemical vapor deposition. The conductive layer 20 is formed on the insulation filling layer 18 and fills the remaining space of the trench 16. The conductive layer 20 may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by chemical vapor deposition.
Referring to fig. 1B, a back etching process is performed on the conductive layer 20 to remove the conductive layer 20 except the trench 16, so as to leave a conductive layer 20a in the trench 16. In some embodiments, the top surface of conductor layer 20a is lower than the top surface of epitaxial layer 14.
Referring to fig. 1C, a doped layer (or referred to as a doped region) 20b is formed on the conductive layer 20a or in the conductive layer 20 a. The doped layer/doped region 20b and the conductive layer 20a have the same conductivity type, such as the first conductivity type dopant. The first conductive type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the doping layer/doping region 20b is higher than that of the conductor layer 20a, for example. In some embodiments, the doping layer/doping region 20b has a doping concentration in the range of 5E 181/cm3To 5E 201/cm3. A thickness/depth of the doped layer/region 20b greater than 1500 angstroms may facilitate control of the subsequent etching process for forming the gate trench. The thickness/depth of doped layer/doped region 20b ranges, for example, from 1600 angstroms to 2500 angstroms.
In one embodiment, the doped region 20b is located in the conductive layer 20 a. The doped region 20b is formed by, for example, performing an ion implantation process IMP 1 on the conductive layer 20 a. The ion implantation process IMP 1 implants dopants into the conductive layer 20a in a manner perpendicular to the surface of the substrate 10. In another embodiment, the doped layer 20b is located on the conductive layer 20 a. The doped layer 20b is formed, for example, by performing a chemical vapor deposition process in situ after the conductive layer 20a is formed, so as to form the doped layer 20b on the conductive layer 20a in a concentration greater than that of the conductive layer 20 a.
Thereafter, referring to fig. 1D, a conductive layer 20c is formed on the doped layer/doped region 20 b. The conductive layer 20c is formed, for example, by forming a conductive layer on the insulation filling layer 18 and the doped layer/doped region 20b, and then performing a back etching process to remove the conductive layer outside the trench 16. The conductive layer 20c may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by chemical vapor deposition. The top surface of the conductor layer 20c may be coplanar with the first surface 14a of the epitaxial layer 14 or lower than the first surface 14a of the epitaxial layer 14.
Thereafter, referring to fig. 1E, an etch-back process is performed on the insulating filling layer 18 to remove the insulating filling layer 18 outside the trench 16, so as to leave an insulating filling layer 18a in the trench 16. The insulation filling layer 18a surrounds the sidewall and the bottom surface of the conductive layer 20a, and surrounds a portion of the sidewall of the doped layer/doped region 20b, and the top surface of the insulation filling layer 18a is between the top surface and the bottom surface of the doped region 20 b. In other words, the insulating filling layer 18a has a first gate trench 22 and a second gate trench 24. The sidewalls of the first gate trench 22 and the second gate trench 24 expose the epitaxial layer 14, the conductive layer 20c and a portion of the doped region 20b, and the bottom surfaces of the first gate trench 22 and the second gate trench 24 expose the top surface of the insulation filling layer 18 a. The etch-back process is, for example, an anisotropic etch process, an isotropic etch process, or a combination thereof.
Referring to fig. 1F, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductive layer 20c and in the first gate trench 22 and the second gate trench 24. The dielectric layer 30 may be silicon oxide formed by thermal oxidation or chemical vapor deposition. In some embodiments of the silicon oxide layer formed by thermal oxidation of the dielectric layer 30, the doping concentration of the doped region 20b is greater than the doping concentration of the epitaxial layer 14, and the doped region 20b is easier to oxidize than the epitaxial layer 14. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the doped region 20b is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the epitaxial layer 14. In addition, since the doping concentration of the doped region 20b is greater than that of the conductive layer 20c, the doped region 20b is easier to oxidize than the conductive layer 20 c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the doped region 20b is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductive layer 20c, which will be described in detail later with reference to fig. 2.
Referring to fig. 1G, a conductive layer 31 is formed on the dielectric layer 30. The conductor layer 31 fills the remaining space of the first gate trench 22 and the second gate trench 24. The conductive layer 31 may be a semiconductor material, such as doped polysilicon formed by chemical vapor deposition.
Referring to fig. 1H, the conductive layer 31 is etched back to remove the conductive layer 31 outside the first gate trench 22 and the second gate trench 24, so as to form a first gate 32 and a second gate 34 in the first gate trench 22 and the second gate trench 24. The top surfaces of the first gate 32 and the second gate 34 may be coplanar with the first surface 14a of the epitaxial layer 14 or lower than the first surface 14a of the epitaxial layer 14.
With continued reference to fig. 1H, a first body region 36 and a second body region 38 are formed in the epitaxial layer 14 on both sides of the trench 16. The first and second body regions 36 and 38 extend from the first surface 14a to the second surface 14b of the epitaxial layer 14. The first and second body regions 36, 38 have dopants of a second conductivity type, such as P-type dopants. The P-type dopant is, for example, boron or boron trifluoride. The first and second body regions 36, 38 are formed, for example, by ion implantation. In another embodiment, the first and second body regions 36 and 38 can be formed before forming the trench 16. For example, the first and second body regions 36, 38 may be formed in-situ during a selective epitaxial growth process for forming the epitaxial layer 14, or may be formed by an ion implantation process after the selective epitaxial growth process.
Next, a first doped source region 42 and a second doped source region 44 are formed in the first body region 36 and the second body region 38, respectively. A first source doped region 42 and a second source doped region 44. The dopant having the first conductivity type is, for example, an N-type dopant. The N-type dopant is, for example, phosphorus or arsenic. The first source doping region 42 and the second source doping region 44 are formed by ion implantation, for example.
Referring to fig. 1I, a dielectric layer 46 is formed on the epitaxial layer 14 to cover the first source doped region 42, the second source doped region 44, the first gate 32, the second gate 34 and the dielectric layer 30. The dielectric layer 46 is, for example, borophosphosilicate glass (BPSG), silicon oxide, silicon nitride or a combination thereof formed by chemical vapor deposition. Next, photolithography and etching processes are performed to form a first contact opening 52 and a second contact opening 54 in the dielectric layer 46, so as to expose the first source doped region 42 and the second source doped region 44, respectively. Thereafter, first and second doped regions 62 and 64 are formed in the first and second body regions 36 and 38, respectively. The first doped region 62 and the second doped region 64 have dopants of the second conductivity type. The dopant of the second conductivity type may be a P-type dopant, such as boron or boron trifluoride. The first doped region 62 and the second doped region 64 are formed by ion implantation, for example.
Referring to fig. 1J, a first contact 72 contacting the first doped region 62 and a second contact 74 contacting the second doped region 64 are formed in the first contact opening 52 and the second contact opening 54, respectively, and the first contact 72 and the second contact 74 are electrically connected to each other. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate 32 to the second gate 34.
Referring to fig. 1J, in the present embodiment, the conductive layer 20a, the doped layer/region 20b and the conductive layer 20c can be collectively referred to as a source polysilicon layer or an isolated field plate PL. The isolated field plate PL can uniform the electric field distribution of the epitaxial layer 14 under the first body region (p-body region)36 and the second body region 38, so that the peak electric field strength is reduced, and thus the breakdown voltage can be increased. On the other hand, the doping concentration of the epitaxial layer 14 can be increased to reduce the on-resistance (Ron) at the same breakdown voltage.
Further, in the present embodiment, the isolation field plate PL includes the first portion P1 and the second portion P2. Doped layer/doped region 20b is a first portion P1 of isolated field plate PL; the conductor layer 20a and the conductor layer 20c may together be referred to as the second portion P2 of the isolated field plate PL. The first portion P1 is sandwiched between the second portions P2, and the doping concentration of the first portion P1 is greater than that of the second portion P2.
Since the first portion P1 of the isolation field plate PL having a higher concentration in this embodiment is exposed by the first gate trench 22 and the second gate trench 24, the bottom of the first gate trench 22 and the second gate trench 24 is higher than the bottom of the first portion P1 (as shown in fig. 1E). Therefore, the first portion P1 with a higher concentration facilitates the formation of a thicker silicon oxide layer during the thermal oxidation process for forming the dielectric layer 30, and thus, more of the first portion P1 is oxidized. Therefore, after the dielectric layer 30 is formed, the first portion P1 is the narrowest width in the isolation field plate PL between the top and bottom surfaces of the first gate trench 22 and the second gate trench 24, as shown in fig. 1F and 2.
Fig. 2 shows an enlarged schematic view of region R in fig. 1J. Referring to fig. 2, the dielectric layer 30 between the epitaxial layer 14 and the first gate electrode 32 is referred to as a first gate dielectric layer 30 a. The dielectric layer 30 between the epitaxial layer 14 and the second gate 34 is referred to as a second gate dielectric layer 30 b. The dielectric layer 30 between the isolated field plate PL and the first gate 32 is referred to as a first insulating layer 30 c. The dielectric layer 30 between the isolated field plate PL and the second gate 34 is referred to as a second insulating layer 30 d.
The first portion P1 (doped layer/doped region 20b) of the isolation field plate PL is adjacent to and in contact with the first insulating layer 30c and the lower portion 30L of the second insulating layer 30 d. In the isolated field plate PL, the second portion P2 (conductor layer 20c) above the first portion P1 is adjacent to and in contact with the first insulating layer 30c and the upper portion 30U of the second insulating layer 30 d.
Since the first portion P1 with a higher concentration facilitates forming a thicker silicon oxide layer, the lower portion 30L of the first and second insulating layers 30c and 30d has the maximum thickness T in the first and second insulating layers 30c and 30dmax1、Tmax2Where. Furthermore, although the first insulating layer 30c and the second insulating layer 30d between the bottom surface of the first gate 32 and the first portion P1 (doped layer/doped region 20b) of the isolation field plate PL have a minimum thickness Tmin1、Tmin2However, this minimum thickness Tmin1A ratio to the average thickness of the first insulating layer 30c, and a minimum thickness Tmin2The ratio to the average thickness of the second insulating layer 30d is still greater than 0.8. In one embodiment, the average thickness of the first insulating layer 30c and the second insulating layer 30d is about 900 angstroms, wherein the maximum thickness T of the lower portion 30L ismax1、Tmax2About 1600 angstroms, and a minimum thickness T of the lower portion 30Lmin1、Tmin2About 800 angstroms.
Since the lower portion 30L of the dielectric layer 30 (the first insulating layer 30c and the second insulating layer 30d) in contact with the first gate 32 and the second gate 34 has a relatively thick and sufficiently thick thickness, leakage current between the first gate 32 and the isolation field plate PL and between the second gate 34 and the isolation field plate PL can be reduced, and the breakdown voltage of the device can be increased.
Fig. 3A to fig. 3E are schematic cross-sectional views illustrating a manufacturing method of a power device according to a second embodiment of the invention.
Referring to fig. 3A, after forming the conductive layer 20a in the trench 16, two doped regions 20 b' are formed in the conductive layer 20a according to the method of the first embodiment. The doped region 20b 'is formed in the edge region of the conductor layer 20a, and the doped region 20 b' is not formed in the central region of the conductor layer 20 a. The doped region 20 b' and the conductive layer 20a have the same conductivity type, such as the first conductivity type dopant. The first conductive type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the doped region 20 b' is higher than that of the conductor layer 20 a. In some embodiments, the doping concentration of the doped region 20 b' ranges from 5E 181/cm3To 5E 201/cm3. The doped region 20 b' is formed by, for example, performing an inclined ion implantation process IMP 2 on the conductive layer 20 a. The angle θ between IMP 2 and the normal of the surface of the substrate 10 is, for example, in the range of 30 degrees to 60 degrees.
Thereafter, referring to fig. 3B, a conductive layer 20c is formed on the conductive layer 20a and the doped region 20B' according to the method of the first embodiment. In the present embodiment, the conductive layer 20a, the doped region 20 b' and the conductive layer 20c can be collectively referred to as a source polysilicon layer or an isolated field plate PL. The isolated field plate PL may include a first portion P1 and a second portion P2. The first portion P1 includes two unconnected doped regions 20 b' that are separated. The second portion P2 includes a conductor layer 20a and a conductor layer 20c connected to each other and separating the two doped regions 20 b' from each other. The doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2.
Then, referring to fig. 3C, according to the method of the first embodiment, the insulation filling layer 18 is etched back to leave the insulation filling layer 18a in the trench 16, and the first gate trench 22 and the second gate trench 24 are formed on the insulation filling layer 18 a. The heights of the bottom surfaces of the first gate trench 22 and the second gate trench 24 are between the top surfaces and the bottom surfaces of the two doped regions 20 b'.
Thereafter, referring to fig. 3D, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductive layer 20c and in the first gate trench 22 and the second gate trench 24 according to the method of the first embodiment. Similarly, since the doping concentration of the doped region 20b 'is greater than the doping concentration of the conductive layer 20c and greater than the doping concentration of the epitaxial layer 14, the doped region 20 b' is easier to oxidize than the conductive layer 20c and the epitaxial layer 14. Therefore, the thickness of the dielectric layer 30 formed on the surface of the doped region 20 b' is greater than the thickness of the dielectric layer 30 formed on the surface of the conductive layer 20c, and the thickness of the dielectric layer 30 formed on the surface of the conductive layer 20c is greater than the thickness of the dielectric layer 30 formed on the surface of the epitaxial layer 14.
Thereafter, referring to fig. 3E, the following processes are performed according to the method described in the first embodiment until the first contact 72 and the second contact 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate 32 to the second gate 34.
Fig. 4A to 4E are schematic cross-sectional views illustrating a manufacturing method of a power device according to a third embodiment of the invention.
Referring to fig. 4A, according to the method for forming the conductive layer 20a described in the first embodiment, a conductive layer 20 a' is formed in the trench 16. However, in the present embodiment, the conductive layer 20 a' is doped polysilicon with a higher concentration. In one embodiment, the doping concentration of the conductive layer 20 a' is in the range of 1E 191/cm3To 5E 201/cm3。
Thereafter, a mask layer 19 is formed on the surface of the edge region of the conductor layer 20 a'. The mask layer 19 exposes the surface of the central region of the conductor layer 20 a'. The mask layer 19 may be a patterned photoresist layer covering the surface and sidewalls of the insulating filling layer 19 and the surface of the edge region of the conductor layer 20 a'. The mask layer 19 has an opening exposing the surface of the central region of the conductor layer 20 a'. The mask layer 19 may be a spacer covering only the sidewall of the insulating fill layer 19 and the surface of the edge region of the conductor layer 20 a'. The material of the spacer may be silicon oxide, silicon nitride or a combination thereof. The spacer forming method may form the spacer material layer first and then perform the anisotropic etching process.
The conductive layer 20a 'is subjected to an ion implantation process IMP3 to form a doped region 20d in the conductive layer 20 a'. The doped region 20d and the conductive layer 20 a' may have the same or different conductivity type dopants.
In the embodiment where the doped region 20d and the conductive layer 20a 'have the same conductivity type, the doping concentration of the doped region 20d is lower than that of the conductive layer 20 a'. The doped region 20d may be formed by implanting dopants into the conductive layer 20 a' in a manner perpendicular to the surface of the substrate 10 by using an ion implantation process IMP 3. The ion implantation process IMP3 is, for example, to implant a second conductive type dopant different from the first conductive type dopant of the conductive layer 20a ' into the conductive layer 20a ', and compensate each other by the dopants, so that the doping concentration of the formed doped region 20d is lower than that of the conductive layer 20a '. The second conductive type dopant is a P-type dopant, such as boron or boron trifluoride. The doping concentration range of the doped region 20d is 5E 181/cm3To 1E 201/cm3。
In an embodiment where the doped region 20d and the conductive layer 20a 'have different conductive type dopants, an ion implantation process IMP3 may be used to implant dopants into the conductive layer 20 a' in a manner perpendicular to the surface of the substrate 10 to form the doped region 20 d. The ion implantation process IMP3 is, for example, to implant a second conductive type dopant different from the first conductive type dopant of the conductive layer 20a 'and having a doping concentration higher than that of the conductive layer 20 a' into the conductive layer 20a ', and to compensate each other by the dopant, so that the conductivity type of the dopant of the formed doped region 20d is different from that of the dopant of the conductive layer 20 a'. The second conductive type dopant is a P-type dopant, such as boron or boron trifluoride. The doped region 20d has a doping concentration range of 5E 191/cm3To 8E 201/cm3。
Referring to fig. 4B, mask layer 19 is removed. The mask layer 19 may be removed by ashing or etching. Thereafter, a conductive layer 20c is formed on the doped region 20d and the conductive layer 20 a' according to the method described in the first embodiment. In the present embodiment, the conductive layer 20 a', the doped region 20d and the conductive layer 20c can be collectively referred to as a source polysilicon layer or an isolated field plate PL.
The isolation field plate PL may include a first portion P1, a second portion P2 and a third portion P3. The doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2 and greater than the doping concentration of the third portion P3. The first portion P1 includes the conductor layer 20 a'; the second portion P2 includes the doped region 20 d; the third portion includes a conductor layer 20 c. The side wall and the bottom of the second part P2 are surrounded and covered by the first part P1, and the third part P3 covers the top surfaces of the first part P1 and the second part P2.
Then, referring to fig. 4C, according to the method of the first embodiment, the insulation filling layer 18 is etched back to leave the insulation filling layer 18a in the trench 16, and the first gate trench 22 and the second gate trench 24 are formed on the insulation filling layer 18 a. The bottom surfaces of the first gate trench 22 and the second gate trench 24 are lower than the top surface of the conductive layer 20a ', so that the sidewalls of the first gate trench 22 and the second gate trench 24 expose the conductive layer 20c and a portion of the conductive layer 20 a'.
Next, referring to fig. 4D, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductive layer 20c and in the first gate trench 22 and the second gate trench 24 according to the method of the first embodiment. Since the doping concentration of the conductive layer 20a 'is greater than that of the conductive layer 20c, the conductive layer 20 a' is easier to oxidize than the conductive layer 20 c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20 a' is larger than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20 c. The doped region 20d is less prone to oxidation than the conductive layer 20a ', so that the isolation field plate PL can maintain a sufficient width to prevent the resistance value from being too high due to excessive oxidation of the conductive layer 20 a' and affecting the characteristics of the power device. In addition, it is also ensured that the dielectric layers on the left and right sides are not connected to each other due to excessive oxidation of the conductor layer 20 a', which would result in disconnection of the isolation field plate PL if the dielectric layers (oxide layers) 30 on the left and right sides are connected.
Thereafter, referring to fig. 4E, the following processes are performed according to the method described in the first embodiment until the first contact 72 and the second contact 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate 32 to the second gate 34.
Fig. 5A to 5D are schematic cross-sectional views illustrating a manufacturing method of a power device according to a fourth embodiment of the invention.
Referring to fig. 5A, according to the method for forming the conductive layer 20a described in the first embodiment, the conductive layer 20a 'is formed in the trench 16, but in the present embodiment, the conductive layer 20 a' is doped polysilicon with a higher concentration. In one embodiment, the doping concentration of the conductive layer 20 a' is in the range of 5E 191/cm3To 8E 201/cm3。
Thereafter, a conductor layer 20c is formed on the conductor layer 20 a' in accordance with the method described in the first embodiment above. The conductive layer 20c and the conductive layer 20 a' have the same conductive type, such as the first conductive type dopant. The doping concentration of the conductor layer 20c is lower than that of the conductor layer 20 a'. The conductive layer 20c is formed, for example, by performing a chemical vapor deposition process in situ after the conductive layer 20a ' is formed, but the concentration of the doping gas is reduced to form the conductive layer 20c on the conductive layer 20a ' at a lower concentration than the conductive layer 20a '. The doping concentration of the conductive layer 20c is, for example, 2/3-1/2 of the doping concentration of the conductive layer 20 a'.
In the present embodiment, the conductive layer 20 a' and the conductive layer 20c can be collectively referred to as a source polysilicon layer or an isolated field plate PL. Conductor layer 20 a' is a first portion P1 of isolated field plate PL; conductor layer 20c is the second portion P2 of isolated field plate PL. The doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2. The second portion P2 covers the top surface of the first portion P1.
Referring to fig. 5B, according to the method of the first embodiment, the insulation filling layer 18 is etched back to leave the insulation filling layer 18a in the trench 16, and the first gate trench 22 and the second gate trench 24 are formed on the insulation filling layer 18 a. The bottom surfaces of the first gate trench 22 and the second gate trench 24 are lower than the top surface of the conductive layer 20a ', so that the sidewalls of the first gate trench 22 and the second gate trench 24 expose the conductive layer 20c and a portion of the conductive layer 20 a'.
Referring to fig. 5C, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductive layer 20C and in the first gate trench 22 and the second gate trench 24 according to the method of the first embodiment. Since the doping concentration of the conductive layer 20a 'is greater than that of the conductive layer 20c, the conductive layer 20 a' is easier to oxidize than the conductive layer 20 c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20 a' is larger than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20 c.
Thereafter, referring to fig. 5D, the following processes are performed according to the method described in the first embodiment until the first contact 72 and the second contact 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate 32 to the second gate 34.
Fig. 1J, 3E, 4E, and 5D respectively illustrate a unit of the SGT MOSFET. However, the invention is not limited thereto. In some embodiments, the SGT MOSFET may have two cells C1 and C1', as shown in fig. 6. In fig. 6, the units of fig. 1J are illustrated as an example, but the invention is not limited thereto. The reference numerals of similar or identical components of units C1 'and C1 are indicated by the same numerals followed by "'". For example, the second doped region 64' is similar to the second doped region 64 and has a second conductive type dopant.
The cells C1 and C1 'are adjacent to each other, and the first body region 36 and the first doped region 62 are shared by the cells C1 and C1'. In addition, the first doped region 62, the second doped region 64 and the second doped region 64 'are electrically connected to each other through the first contact window 72 and the second contact windows 74 and 74'. The first and second gates 32 and 34 of the cell C1 and the first and second gates 32 ' and 34 ' of the cell C1 ' may be electrically connected to each other.
In other embodiments, the SGT MOSFET may have more cells, and the cells may be arranged in an array. In other words, the SGT MOSFET may have a plurality of gates, a plurality of source doped regions and a plurality of drain doped regions. The plurality of gates, the plurality of sources and the plurality of drains may be arranged in an array, and the plurality of gates, the plurality of source doped regions and the plurality of drain doped regions may be connected together by interconnects to form a gate terminal, a source terminal and a drain terminal, respectively
In summary, the isolation field plate with high doping concentration is exposed on the lower sidewall of the gate trench, so that a thick oxide layer can be formed at the bottom corner of the gate trench, thereby reducing the leakage current between the gate and the source and improving the breakdown voltage of the device. On the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (QG), improve the quality Factor (FOM), and improve the device performance.

Claims (10)

1. A power element, comprising:
an epitaxial layer having a trench extending from a first surface to a second surface of the epitaxial layer;
a drain doping layer located on the second surface of the epitaxial layer;
the first substrate area and the second substrate area are positioned in the epitaxial layers on two sides of the ditch;
the first source electrode doping area and the second source electrode doping area are respectively positioned in the first base area and the second base area;
an isolated field plate located in the trench;
the insulating filling layer is positioned in the trench and surrounds the side wall and the bottom of the lower part of the isolation field plate;
a first gate and a second gate in the trench and on the insulating fill layer, wherein the first gate is between the isolated field plate and the first substrate region and the second gate is between the isolated field plate and the second substrate region; and
a dielectric layer surrounding sidewalls of the first and second gates, wherein a lower portion of the dielectric layer has a maximum width of the dielectric layer, an
Wherein the isolated field plate includes a first portion and a second portion, the first portion being adjacent to the lower portion of the dielectric layer and having a doping concentration greater than the second portion.
2. The power device of claim 1 wherein said first portion is a doped layer sandwiched between said second portions.
3. The power element of claim 1, wherein the first portion comprises two unconnected doped regions separated by the second portion.
4. The power device of claim 1, wherein the isolation field plate further comprises a third portion having a lower doping concentration than the first portion and covering top surfaces of the first portion and the second portion, and wherein sidewalls and a bottom of the second portion are surrounded by the first portion.
5. The power element of claim 1, wherein the second portion is located on the first portion and covers a top surface of the first portion.
6. The power element of claim 1, wherein a bottom surface of the first portion is higher than a bottom surface of the dielectric layer.
7. The power element of claim 1, wherein a top surface of the first portion is higher than a bottom surface of the dielectric layer.
8. The power element of claim 1, wherein the maximum width of the dielectric layer is greater than an average width of the dielectric layer.
9. The power element of claim 1, wherein the isolated field plate has a minimum width of dielectric layer corresponding to the lower portion of the dielectric layer.
10. The power element according to claim 9, wherein a ratio of the minimum width of the dielectric layer to an average width of the dielectric layer is 0.8 or more.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116525663A (en) * 2023-07-05 2023-08-01 江苏应能微电子股份有限公司 Trench type power MOSFET device with gate source end clamping structure and preparation method thereof

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4895810A (en) * 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US4992390A (en) * 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide
TW456049B (en) * 2000-09-05 2001-09-21 Ind Tech Res Inst Trench-type metal oxide semiconductor stop structure
DE69806484D1 (en) * 1998-11-17 2002-08-14 St Microelectronics Srl Method of making a vertical channel MOSFET
US20050242392A1 (en) * 2004-04-30 2005-11-03 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
TW201023273A (en) * 2008-12-05 2010-06-16 Maxpower Semiconductor Inc Power metal oxide semiconductor field effect transistor structure and manufacturing method thereof
CN101840934A (en) * 2009-03-17 2010-09-22 万国半导体有限公司 The structure of bottom drain LDMOS power MOSFET and preparation method
US20110156139A1 (en) * 2009-12-28 2011-06-30 Force Mos Technology Co. Ltd. Super-Junction trench mosfet with resurf step oxide and the method to make the same
US20130320435A1 (en) * 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Trench Power MOSFET
CN108878527A (en) * 2017-05-12 2018-11-23 新唐科技股份有限公司 U-shaped metal oxide semiconductor component and its manufacturing method
TW201903956A (en) * 2017-06-06 2019-01-16 馬克斯半導體股份有限公司 Power element with polycrystalline silicon filled trenches with tapered oxide thickness doping nitrogen into the trench walls to form tapered oxide

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283201A (en) * 1988-05-17 1994-02-01 Advanced Power Technology, Inc. High density power device fabrication process
US8373225B2 (en) * 2009-12-28 2013-02-12 Force Mos Technology Co., Ltd. Super-junction trench MOSFET with Resurf stepped oxides and split gate electrodes
US8969955B2 (en) * 2012-06-01 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Power MOSFET and methods for forming the same

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4895810A (en) * 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US4992390A (en) * 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide
DE69806484D1 (en) * 1998-11-17 2002-08-14 St Microelectronics Srl Method of making a vertical channel MOSFET
TW456049B (en) * 2000-09-05 2001-09-21 Ind Tech Res Inst Trench-type metal oxide semiconductor stop structure
US20050242392A1 (en) * 2004-04-30 2005-11-03 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
TW201023273A (en) * 2008-12-05 2010-06-16 Maxpower Semiconductor Inc Power metal oxide semiconductor field effect transistor structure and manufacturing method thereof
CN101840934A (en) * 2009-03-17 2010-09-22 万国半导体有限公司 The structure of bottom drain LDMOS power MOSFET and preparation method
US20110156139A1 (en) * 2009-12-28 2011-06-30 Force Mos Technology Co. Ltd. Super-Junction trench mosfet with resurf step oxide and the method to make the same
US20130320435A1 (en) * 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Trench Power MOSFET
CN108878527A (en) * 2017-05-12 2018-11-23 新唐科技股份有限公司 U-shaped metal oxide semiconductor component and its manufacturing method
TW201903956A (en) * 2017-06-06 2019-01-16 馬克斯半導體股份有限公司 Power element with polycrystalline silicon filled trenches with tapered oxide thickness doping nitrogen into the trench walls to form tapered oxide

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116525663A (en) * 2023-07-05 2023-08-01 江苏应能微电子股份有限公司 Trench type power MOSFET device with gate source end clamping structure and preparation method thereof
CN116525663B (en) * 2023-07-05 2023-09-12 江苏应能微电子股份有限公司 Trench type power MOSFET device with gate source end clamping structure and preparation method thereof

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