TW456049B - Trench-type metal oxide semiconductor stop structure - Google Patents

Abstract

The present invention provides a trench stop structure which is used in connection with any kind of trench-type metal oxide semiconductor component to form different power transistor structure with high voltage durability, such as Schottky diode, double diffused MOS, or insulated gate bipolar transistor. The process includes the following steps: forming trenches in the silicon substrate; growing gate oxide; refilling polysilicon layer; forming the spacer by anisotropic etching; depositing the oxide; defining the contact area with photoresist and etching; and, forming the metal layer and photoresist and etching the defining electrode. Therefore, because the metal oxide semiconductor structure and the stop structure are formed in the same time, the process is simpler and the number of required photomask is three which is less than the stop structure of conventional local oxide layer with guard ring. The trench-type stop structure can make the depletion area of the device planarized during reverse bias operation. The breakdown voltage will not be reduced by the effect of the stop structure so as to increase the production yield.

Description

456049 ---------__________________ V. Description of the Invention (1) | Field of the Invention: The present invention relates to semiconductor processes, and in particular refers to the termination of a Scho11ky diode power line using a trench structure. Prevent leakage current. Background of the Invention: Double diffused metal-oxide-semiconductor (double diffused M0S; M 0 S), insulated gate bipolar transistor (insu 1 atedga ΐ ebi ρ 1 ar transistor; IGBT), and Schottky diodes are all A very important power transistor is widely used in power supply switches, motor control, telecommunication switches, factory automation, electronic automation, etc. and many high-speed power switching applications, which can carry great forward current. Reverse bias can block at least 30 volts of high voltage. In particular, trench M0S, trench IGBT, and trench Schottky diodes have been researched and shown to be superior to DM0S, IGBT, and Schottky diodes with planar architectures. For a power transistor, in addition to designing an active region that can conduct current ', it is necessary to design a termination structure to avoid the early occurrence of a collapse phenomenon during reverse bias operation. Traditional termination structures are as follows: local oxidation of silicon (LOCOS), field plate, guard ring, or ---, V. Description of the invention (2 ) Liang'e I species. The regional oxidation method has the characteristics of a birdbeak. The phenomenon, ~ 'is easy to cause electric field crowding (electric iield crOwding). It is caused by the impact ionization rate (impaci i〇nizati〇n) at 亥, so that As the leakage current rises, the performance of the active region is degraded. ^ Absolute-• Schematic diagram of the Schottky diode and the termination structure. The figure shows n + A n + A, which is heavily doped with n-type conductive impurities. Bu Gu n 逡 φ is formed by t ^^ a, ^ 20〇 ^ # several grooved metal oxide half 15; U = =; there are complex 20 / gate oxide layer 25 / polycrystalline silicon layer 3〇 The edge of the substrate is -thick, with an area of about 600 0 Angstroms to oxidize the edge to "⑷t" in order to reduce the bird's beak effect, which results in an electric field of 5 in the area of the oxide layer. The protective layer of the region 50 forms a p + dopant 5 in a manner to enhance the resistance of the termination structure. 5 The active region 5 extends to the region oxide layer and the anode (a metal layer) makes the element under reverse bias. The empty region: the miscellaneous region 5 Beyond 0, it is used for 5. The guard ring p + doped region 5 〇 Although it can ease the phenomenon of electric field congestion in the empty region away from the active region, but The degree of ionization of the ion A is to reduce the restriction below the abutment of the 50 and the grooved gold halves. At the p + doped region, it is not a smooth curve, so the leakage is as shown by the arrow 60 in the figure. It is shown that the leakage current cannot be greatly reduced and it cannot bear ^; brother is still quite serious. Although the use of a guard ring in combination with the electric field plate structure can also have a high reverse bias voltage. In addition, to reduce the phenomenon of electric field crowding, there are similar, weaving and empty areas The degree of bending uses a large number of photomasks, and the process complexity is a problem. Secondly, the above-mentioned method & 'production cost is also high, V. Description of the invention (3) is even more disadvantageous. In view of the above traditional termination structure, it cannot be The problem is indeed solved. The present invention will therefore provide a new termination structure, which can not only make the empty area begin to bend away from the active area, make the empty area boundary flat, but also because the method of the present invention can be formed with the power transistor described above, it has The number of photomasks is small (the number of photomasks related to the termination structure is three), the process complexity is reduced, and the cost is reduced. The purpose and summary of the invention: The purpose is to provide a new termination structure and a method for forming the same. Another object of the present invention is to solve the problem of electric field crowding in the conventional termination structure. Another object of the present invention is to provide a power transistor capable of withstanding high voltage. The termination structure formed together can reduce the number of photomasks (the number of photomasks related to the termination structure is three), a method of reducing the complexity of the process, and a method of reducing costs. The present invention provides a grooved metal-oxide half-structure and The method for forming a termination structure at the same time includes at least the following steps: First, according to the trench metal-oxide semi-structure system, a Schottky diode, a double-diffusion metal-oxide semi-electric transistor (DM0S), or an insulating gate is formed. Bipolar Transistor (I GBT)

456049 V. Description of the invention (4) Same as ′ but using different semiconductor substrates as the basis. For example, the gold-oxygen semi-electric crystal structure in the active region, if it is used to form a trench-type S ch 〇11 ky diode ', the semiconductor substrate contains at least one first conductive impurity (C η type) doped from top to bottom. The first and second substrates (π +) ′, which are doped with the first substrate and a first conductive impurity heavily doped, are the upper and lower surfaces of the semiconductor substrate, respectively, as described in the first embodiment. If the above-mentioned trench-type metal-oxide half-structure is used to form a trench-type DMOS in the active region, the semiconductor substrate includes at least the first layer of a p-type conductive impurity heavily doped (P +) from top to bottom. (Wafer front side) / ρ-type conductive impurity, second layer of impurity (P) / lightly doped (η_) third layer of η-type conductive impurity / north-type conductive impurity re-doped (η +) The substrate is the fourth layer (semiconductor substrate: surface). The first layer has a plurality of n-type conductive heavy impurity regions (η +) formed in the first layer, and extends from the upper surface of the semiconductor substrate to the p-type conductive impurity. The second layer is doped. As described in the second embodiment. If the trench two-metal-oxide half-structure is used for the active region: Ϊ: Polar bipolar Λ transistor (IGBT) ’, the semiconductor substrate contains at least one p-type conductive impurity heavily doped from top to bottom (/

-Type conductive impurity doped (P) second layer ^ Thai layer (Ha round front side) / P (η-) third layer / n-type conductive impurity heavy I ¥ Impurity lightly doped electrical impurity heavily doped The substrate of (P +) is the fourth layer of the fifth ^ η +) / first of the p-type conductive impurities that are heavily doped (P +); and 2 (crystal / back surface) 'and 娌 ^ ^ ,,, On the top # 分 a ^ 1, a plurality of n-type conductive heavy impurity regions U +) are formed therein, and extend from the upper surface of the semiconductor substrate 456049. 5. Description of the invention (5) Inside the second floor. As described in the third embodiment. J The implementation method of the present invention is as follows: first, a plurality of first trenches having a relatively narrow width are formed in an active region of a semiconductor substrate, and a second trench is formed. The second trench extends from the edge of the active region to the edge of the semiconductor substrate. The plurality of first trenches are separated from each other and the second trench is separated from the first trench adjacent to the edge of the active region by a platform. The first trench is used to form a metal-oxide half-structure, and the second trench is used to form a termination structure region and another sidewall metal-oxide half-structure. In the first embodiment, the trench is formed in the first substrate. In the second embodiment, the bottoms of the first trench and the termination structure are in the third layer described above. In the third embodiment, the plurality of first trenches are formed in a second layer doped with an n-type conductive heavy impurity region / a p-type conductive impurity, and a third layer lightly doped with an n-type conductive impurity. Layer. Then, a high-temperature thermal oxidation process is used to form a gate oxide layer on the upper surface of the platform, the sidewalls and bottoms of the first trench, the second trench, and the back surface of the semiconductor substrate. Then, a first conductive layer is formed on the gate oxide layer, and at least fills the first trench and is higher than the upper surface of the platform. If a Schottky diode is formed, the first conductor layer may be a polycrystalline silicon layer, a metal layer, or an amorphous layer. When forming DM0S or I G B T, a polycrystalline silicon layer or an amorphous silicon layer is suitable. 456049 5. Description of the invention (6) Then an anisotropic etching is performed on the front surface of the semiconductor substrate to remove the first conductive layer until the gate oxide layer on the upper surface of the platform is exposed, and a gap wall is formed on the second On the sidewall of the trench. Then the exposed gate oxide layer on the front surface of the semiconductor substrate is exposed to expose the upper surface of the platform.

I! I Subsequently, there are slight differences depending on the embodiment. For example, the methods of the second embodiment and the third embodiment are performed by a high-temperature thermal oxidation process to oxidize the first conductor layer and the first layer of the semiconductor substrate to form a conductor interlayer oxide layer, and then remove the surface of the platform. High temperature oxidation layer. At this time, the surface of the first conductor layer in the first trench and the gap wall surface of the second trench still has an interlayer conductor oxide layer to isolate the connection between the first conductor layer and the second conductor layer (described later). In the first embodiment, the above two steps will be skipped so as to form a Sh 0 11 k y contact. Finally, as in the first embodiment, a termination structure oxide layer is formed on all regions including the back surface of the semiconductor substrate. Then, a photoresist pattern is formed on the termination structure oxide layer to define a contact area to expose the plurality of first trenches. The first conductor layer of the trench, the flat surface, and a part of the upper surface of the second trench spacer; subsequently, the photoresist pattern is used as a mask to stop the oxidation of the structure

Page 10 4 5 6 0 4 9 [^, Description of the invention (7) An oxide layer is formed, and then lithography and etching are performed to form a termination structure oxide layer, which covers the bottom of the second trench and the sides of the spacer. Finally, a second conductive layer is formed in all areas to form an electrode on the front and back of the semiconductor substrate. The second conductive layer in the termination structure area is removed by lithography and etching technology as a source (for DM0S) or emitter (for I GBT). Detailed description of the invention: In view of the background of the invention, the conventional termination structure, whether it is any one of regional oxidation, electric field plate, guard ring, or a combination thereof, may still cause the problem of electric field congestion, only the position is changed. Therefore, the present invention will provide a method with a permanent cure, that is, a grooved metal oxide semi-terminated structure. The grooved metal oxide semi-terminated structure of the present invention has a feature of flattening the edge of the empty region and bending it away from the active region to prevent it. Electric field congestion / problems can therefore prevent premature collapse. The termination structure of the present invention can be applied to any type of high-voltage trench power transistor, such as a trench Schottky diode, a trench DM0S, and a trench insulated gate bipolar transistor (IGBT ), Etc., and can form the termination structure of the present invention while forming the above-mentioned trench power transistor. The following embodiments will be described separately. 4 5 6 Ο 4 9 V. Description of the invention (8) The first embodiment is a method for forming a trench termination junction L v # Shi Tu Zaixing Schot tky diode at the same time. Please refer to the schematic diagram of the cross-section of FIG. 2. First, a half-1000 ′ semiconductor substrate 100 includes a first conductive impurity dopant. A preferred embodiment is the first substrate 1⑽A and a first ^ The electrically heavily doped (n +) second substrate 100B is the upper and lower sides of the semiconductor substrate 100 respectively. Therefore, when the first substrate 100A and the selected metal layer contact & form a Schottky contact, the first When the two substrates 100B are in contact with the same metal layer, an ohmic contact can be formed. Generally speaking, the first substrate 100A is formed by epitaxial growth of the second substrate. Next, a chemical vapor deposition method is used to deposit an oxide layer 101 having a thickness of about 2000 angstroms to 100 angstroms on the first substrate 100 A. Subsequently, a photoresist pattern (not shown) is formed on the oxide layer 101 to define a plurality of first trenches 1 1 Q and a second trench 120. The first trench 110 is formed in the active region. Viewed from a cross-sectional view, the width is about 0.2-2.0 # in 'the second groove 120 is formed at the edge of the active area and is spaced from the first groove 11 by a platform 115 having a width of about 2-4. 4 " m 0, and extends to the edge of the semiconductor substrate as a termination structure region to prevent the occurrence of electric field crowding. After that, an anisotropic Θ is applied for a while to transfer the photoresist pattern to the oxide layer 1 ο 1; then, the photoresist pattern is removed again, and the oxide layer 010 is used as a hard mask, and then an Isotropic #etch 'to remove the first. Substrate 1 0 0 A bare

Page 12 V. Description of the Invention (9) The semiconductor substrate 100a to form a second trench 1220 and a first trench 110 ′ to—in a preferred embodiment, the first trench and the first trench The second trench is about 0.4 deep — iO.O # m. Since the second trench 120 is the edge of the semiconductor substrate or the die (d i e), the second trench! 2 Only one side adjacent to the first trench 1 1 0 has a side wall 120A. The width of the first trench is about 0.2-2. 0 μm (as shown in the cross section of the figure), and the width of the second trench 120 is about 2_0-30.0 # πm, which is much larger than the first trench U 0. Please refer to FIG. 3, after the oxide layer 101 is removed, a gate oxide layer 1 2 5 is formed in an all-round manner by a high-temperature thermal oxidation process. The gate oxide layer 1 2 5 is about 150 Angstroms to 3 0 0 0 A side wall 115A of the first trench 110 and the second trench 1220 are 〇 〇A, 12 0 A and the bottom 11 0 B, 12 0 B and the upper surface of the mesa between the two trenches 115A The gate oxide layer 125 may also be formed by high temperature oxidation (HTQ) deposition. Next, the first trenches 110 and the second trenches 12 are completely backfilled by a chemical vapor deposition method with a first conductive layer 1 40 on the gate oxide layer 12 5 and higher than the platform 115. At the same time, a first conductive layer 140 is also formed on the gate oxide layer 125 on the back of the semiconductor substrate (ie, the second substrate 100B); the first conductive layer 140 may be a metal layer, a polycrystalline silicon layer, or an amorphous silicon layer. In a preferred embodiment, the first conductive layer 140 is about 0.5 to 3.0 # m thick. In order that the inside of the first trench Π0 can be completely free of holes (v oid), the polycrystalline silicon layer deposited on the first conductive layer 14 by a low-pressure chemical vapor deposition method with better step coverage is:佳 'but when the aspect ratio of the first trench Π 〇 (aspect

Page 13 4 5 6 Ο 4 9 V. Description of the invention (10) rati 〇) Too large, for example, greater than 5, then plasma-assisted chemical vapor deposition is used to deposit an amorphous silicon with better interstitial properties. The layers are better (but need to be reannealed to recrystallize). Subsequently, please refer to FIG. 4 ′ to perform an anisotropic etching to remove the excess first conductive layer 140 on the first trench 110 to the gate oxide layer 1 2 5 on the platform 115 of the bare semiconductor substrate. 'At the same time as the etching, a partition wall 1 2 2 having a height and a width that is approximately the same can be formed on the side wall 1 2 0A of the second trench. Β is subsequently exposed to the exposed gate oxide layer on the platform 1 1 5 by wet etching. Remove. Next, a full dielectric layer is deposited (the termination structure is widely oxidized). In the preferred embodiment, the dielectric layer may be LPTEOS, PETEOS, or ozone. £ 03 It is also possible to use a layer, or a layer of 1 {1'0 or a dioxide layer. The dielectric layer 150 is about 0.2 to 1.0 # m thick. After that, a photoresist pattern 15 5 is formed on the dielectric layer 150 to define a Schottky contact area of the active region; and a dry etching is performed to etch the dielectric layer 50 using the photoresist pattern 155 as a mask to expose The upper surface 115A of the platform of the first substrate 100A and the first conductor layer 140 in the first trench I10. Finally, please refer to FIG. 5. In the photoresist pattern removal pattern, the semiconductor substrate surface (ie, the second substrate 屮 _) is removed: the first layer of the “electricity” = the -conductor layer HG, the gate oxide layer 125 is removed, Take out the first substrate

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4 5 6 0 4 S V. Description of the invention (11) The upper surface of 10 〇 B. Subsequently, a second conductor layer is deposited on the first substrate 100A by sputtering to form a Schottky contact region Π5A and an upper surface of the second substrate 100B to generate a cathode i 6 O B with an ohm 1 c contact. Subsequently, a photoresist pattern 165 is formed on the second conductor layer 14 of the first substrate 100A to define the anode location. Finally, an etching technique is applied to form the anode i 608. In a preferred embodiment, the anode 160a on the first trench 120 needs to extend away from the active area by at least 2, m, so that the 'empty' empty area is far from the active area. Figure 5B shows the structure of the first embodiment (the simulated electrical board simulated by the grooved Schottky diode plus termination structure of Figure 5). The conductor layer, that is, the cathode α i is applied with clear voltage. : The case of mϊ voltage '). The curve indicated by the symbol m in the figure: ΐ ΐ! The voltage shared by the potential line from the bottom to the top gradually decreases, and the curve perpendicular to: the bit line is a schematic diagram of the leakage current. It is shown that only the active region has leakage current, and the leakage current under the termination structure region is very small. Furthermore, the electrical diagram of the structure of the present invention makes the potential line ΐ80〇ι representing the boundary of the empty region slow, so it will not cause early collapse The formation current is extremely limited, please refer to Figure 5C, showing the unmatched termination: the metal-oxygen half-structure reverse bias current 1 95 # p with the termination structure > the comparison diagram of the standby bias current 190, at the reverse bias For 10: the current is only increased by about 8. 8%, compared with the traditional regional oxide layer. The 1.28% of the superstructured flat ring structure is significantly improved, but the latter mask, the present invention requires only three masks ( The formation of 4 times the light Dan said horse for the first time, the termination structure

Page 15 456〇49 ^^ -_____ 5. Description of the invention (12) ~ 1 ~. 'The porosity layer is formed for the first time, and the metal electrode is engraved for the third time). The above therefore 'according to the above-mentioned formation method' The structure of the Schottk y diode and the two termination structure region includes at least: a semiconductor substrate 100 including a first substrate 10Q A doped with a first conductive impurity and a first conductivity The second substrate 100B heavily doped with impurities is divided into two parts above and below the semiconductor substrate so that a narrow first trench 110 is formed in the active region 1 and a second trench 1 2 0 is formed by a platform u. The distance 5 is separated from the first trench 11 0 and formed on the edge of the first substrate 100 A active area and extends to the edge of the first substrate 110 A. Therefore, the cross-section of the second trench 120 is much larger than The first trench 110 is wide. A first trench metal-oxide half-structure is formed in the first trench 110 and includes a first conductive layer 14 0 / gate oxide layer 1 2 5 / first substrate 100. A second metal-oxygen half structure is formed in the second trench 1 2 0 sidewall 1 2 0 A, and includes a side barrier / gate oxide layer 1 2 5 formed by the first conductive layer 1 4 0 / first substrate 1 0 0 A. The first conductive layer 140 in the first metal-oxygen half structure fills the first trench 110. The second metal-oxide-semiconductor structure is separated from the first metal-oxide-semiconductor structure by a platform (mesa). In addition, a termination region oxide layer 150 is formed in the second trench 1 2 0 and the bottom 1 2 0 B and extends to cover the conductor layer. On the side of the side gap wall 140, a metal guide layer 160A is formed on the first metal-oxygen half structure, the upper surface of the platform 115A, and the second metal-oxygen half structure and extends to cover the bottom of the second trench 1 2 0 portion. And form a grooved Schottky.

Page 16 456049 V. Description of the invention (13)! The second preferred embodiment of the present invention uses the termination structure of the hairpin as the termination structure of the trench DMOS. Please refer to FIG. 6. In order to apply the trench metal-oxide half structure to DMOS, the semiconductor substrate required will be different from the case of forming a Schottky diode. Therefore, the structure and the method of forming DM0S are as follows. First, a semiconductor substrate 2000 ′ is provided. The semiconductor substrate 2000 includes an n-type heavily doped substrate (n + substfate) 2 [) from the bottom up. The impurity is lightly changed to the epitaxial layer or called the drift layer (heart ^ iayer)) 2 00B 'and a p-type conductive conductive body is replaced with the worm crystal layer (or called the p base layer (p_base iayer)). 200A. Therefore, the outer layer is formed of a heavily doped P + layer 203 on top of the p-base layer 200 A by ion implantation. The n + region 2 〇4 is in the heavily doped ρ + layer 2 0 3 in the ρ base layer 2 0 0A. Therefore, the ρ + layer 203 has been divided, and the η + region 2 0 4 is divided to form a cross-sectional view as shown in FIG. 6. The ρ + region 2 03 and ^ + region 20 4 are shown. Among them, the thickness of the ρ base layer 200 Α is about 0_5_5 porphyry_ ρ + region 2 03 and η + region 2 0 are about 0 ·, respectively. 2-1.0 mm and 0.2-1.0 μηη). ^ Subsequently, please refer to FIG. 7, as in the method of the first preferred embodiment, a plurality of first trenches 210 are formed in the n + region 204 of the active region, and the bottom of the first trench 210 is deep. And p drift layer 2000B under the base layer 2000A. The first trench 210 and a second trench 220 are separated by a platform 22 5 and are formed from the edge of the active region to the edge of the semiconductor substrate 2000 (or a die di e). Subsequently, as described in the first preferred embodiment, a gate oxide layer 22 5 having a thickness of about 150 to 300 angstroms is fully formed by a high-temperature thermal oxidation process. Fully backfill the polycrystalline silicon layer

Page 17 4 5 6 0 4 9 V. Description of the invention (14) 2 4 0 (or amorphous debris layer) fills the first trench 2 1 0 and is higher than the upper surface of the platform 2 2 5 A, and then etch back to The gate oxide layer 2 2 5 A on the upper surface of the platform 2 2 5 is exposed. Next, the gate oxide layer is first removed by wet etching to expose the p + region 2 0 3 and η + on the semiconductor substrate 2 0 A. Area 2 0 4 and then the conductor interlayer silicon oxide layer 2 4 5 is formed again by the high temperature thermal oxidation process. Please note that the polycrystalline silicon layer 2 4 0 can provide more grain boundaries to provide oxygen and silicon react with each other. Fast path. Therefore, the polycrystalline silicon layer 24 in the first trench 210 has a deeper degree of oxidation. In addition, the side wall of the second trench 2 20 also consumes part of the polycrystalline silicon layer due to oxidation, so the gap The wall 2 4 0 also has a thicker oxide layer than the platform 2 1 5. Please refer to FIG. 8 '. Next, the termination layer is engraved with the surface of the platform 2 1 5 A as a surname again, and a part of the conductive interlayer oxide layer 2 4 5 is removed. Please note that since the oxide layer on the polycrystalline silicon layer is thick, when the semiconductor substrate 200A is removed and exposed, the polycrystalline silicon layer 2 4 0 on the first trench 2 1 0 and the second trench 2 2 0 There is still a portion of the oxide layer 245. There is another option in the above steps. The gate oxide layer 2 2 5 is temporarily removed, and after the thermal oxidation again forms the conductor interlayer oxide layer 2 4 5, the platform 2 1 5 A is used as the etching stop layer. The high-temperature oxide layers 2 2 5 and 2 4 5 on the η + region 2 0 4 and the ρ + region 2 0 3 are removed together. However, care must be taken to keep the oxide layer 2 4 5 on the polycrystalline silicon layer 2 40 during the etching to prevent the short circuit caused by the connection with the metal conductor layer formed in the subsequent steps.

Page 18 4 5 6 0 4 9 V. Description of the invention (15) Still referring to FIG. 8 ', a TEO S dielectric layer 2 50 is further formed, a photoresist pattern is formed, and the oxide layer is etched by an etching technique. The platform 215A on the semiconductor substrate is an inscribed stop layer, which is used to expose the n + doping regions 204 and p + regions 203 (203 and 204 on the semiconductor substrate on the active region) as the source. ). Finally, please refer to FIG. 9 before removing the back surface of the semiconductor substrate before forming the source and non-contact metal layer by the Tibetan mineral method, that is, the TEOS dielectric layer 2 50 / conductor interlayer oxidation on the semiconductor substrate 200c. The layer 2 4 5 / polycrystalline silicon layer 2 40 and the anode oxide layer 2 2 5 are used to expose the n + doped region of the semiconductor substrate 2 0 0 C. Subsequently, a metal layer 2 60 is formed by a sputtering method to form a source contact 2 60 A on the first substrate 200 A, and at the same time, a drain is formed on the back surface of the wafer (the substrate 2 0 C). The contact 2 6 0 ′, and the polycrystalline silicon layer 2 40 of the first trench and the spacer 2 240 of the second trench are trench gates. Finally, the metal layer (source electrode 260 A) on the structure region 220 is terminated, and then the photoresist and etching techniques are used to cut off part of the metal layer away from the active region. The termination structure of the present invention can also be formed at the same time (IGBT), as in the first embodiment of the present invention, as in the first embodiment, the bit and the insulated gate bipolar transistor)) For the three embodiments, please refer to the tenth figure. Please refer to FIG. 10 ’for forming the termination structure and the semiconductor substrate and the shape of the I GBT.

Page 19 456049 V. Description of the invention (16) Trenched DM0S-like semiconductor substrate Semiconductor substrate 300 includes from top to bottom a first layer substrate 300A of a p-type doping, and a second layer 300B of a lightly doped n-type, The n-type heavily doped third layer (also known as the buffer layer) is 300 ° C, and the p-type heavily doped base layer is 300 D. The first to third layers are formed on the p-type heavily doped base layer 300 D by an epitaxial method. The upper part of the first substrate 2008 is additionally ion-implanted to form a doped P + layer 3. 0 3, and finally formed by the mask and ion implantation and the Ω + region 3 04 in the heavy P + layer 3 0 3. Therefore, the p + layer 3 0 3 has been divided by the n + region 3 0 4 and is shaped like, π, 戍 as shown in the cross-sectional view of Fig. 10, the P + region 3 0 3 and the η + region 3 0 4 °. Exciting 181 eleven, forming a plurality of first trenches 3 1 0 at the bottom of the Φ _ 'T' first trench 3 1 0 in the active region η + region 3 0 4 and deep below the p layer 3 0 2. In addition, the M Γ trench 3 2 0 and the first trench 3 1 0 and the plurality of first trenches 3 1 0 are all 彡 A η for a while. π 丄, see about 0_ 2-4 · 0 // m platform 315 apart, the second trench 3 2 0 is formed at the edge of the main semiconductor W + 4 and extends to the edge of the semiconductor substrate. The trench formation method is the same as that described in the first embodiment. Subsequently, the same; 1¾ ^ ^ ,,, ^ According to the first preferred embodiment, the high temperature thermal oxidation system is used to produce 裎 + r α, η Λ and the thickness is about 1 5 0-3 0 0 〇Angle gate oxide layer 3 2 5 Zaiquan ™ Λ ^ ^ 32 ^ 7 ^ ^ 3 ^ ° ^-until the first trench 3 1 0 on the flat surface is exposed and higher than the platform 3 1 5 ′ The nickname engraved the gate oxide layer 3 2 5 with a surface of 3 1 5 A and formed a partition wall 3 4 0 on the side wall of the first trench.

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45604S V. Description of the invention (17) ^ f Immediately, after removing the gate oxide layer 3 on the platform surface 315 A, the high-temperature thermal oxidation and etching techniques are used to form the conductive layer 345, as in the second. The preferred embodiment is shown. Of course, the first conductor layer is also thermally oxidized at high temperature to form a conductive interlayer oxide layer 3 = the gate oxide layers 325 and 345 on the platform are then removed, but the first "340," and the spacer 34 0 are prepared. An oxide layer is formed thereon to prevent the first conductor layer and the V-body layer from being short-circuited. Difficult to conduct a conductor Finally, a TE0S dielectric layer 35 is formed comprehensively, and then a photoresist pattern is formed. The oxide layer is etched by an etching technique, and the first substrate is used as an etching middle layer. It is used to expose the n + doped region 304 and the p + dopant region 303 (the gap wall 34 of the emitter stop groove 320 part to connect with the wire layer. Secondly, please refer to FIG. Before forming the emitter contact layer by plating, remove the back surface of the semiconductor substrate, that is, the p + base layer (3001) without the gold TEOS dielectric layer 3 50 / oxide layer 345 / polycrystalline silicon layer 34 and the gate hafnium oxide. 3 2 5 ′ to expose the back surface of the semiconductor substrate (ρ + base layer 300). = = 成 -Metal layer, used to form the emitter moxibustion on the first substrate view :, At the same time, the collector contact is also formed on the back surface of the semiconductor substrate (P + layer 3 0 0 D). 〇 / z m。 Finally, lithography and etching technology is used to cut off the second metal layer on the termination structure ‘break off’ is also at least 2. 0 / z m away from the active area. The present invention has the following advantages: (1) Since the empty area_curve has extended away from the active area, and the empty product boundary is flat, it can greatly reduce the early occurrence of the breakdown voltage 4 5 6 Ο 4 i .; 5. Invention Note (18), and the leakage current (about 8.8%) caused by the termination structure of the present invention is significantly smaller than the termination structure (about 12.8%) of the traditional regional oxide layer and guard ring. (2) The manufacturing process is simpler than the traditional method. The termination structure can be formed together with the active area structure * and the number of photomasks is reduced. The above is only a preferred embodiment of the present invention. It is not intended to limit the scope of patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application.

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45 60 4 S Schematic illustration of the preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: Figure 1 shows the traditional grooved Schottky diode and regional oxidation The layer plus guard ring is used as a schematic diagram of the termination structure. FIG. 2 shows a schematic diagram of forming a first trench and a second trench in a semiconductor substrate according to the method of the present invention. FIG. 3 is a schematic diagram of backfilling the first trench and the second trench to form a first conductor layer according to the method of the present invention. FIG. 4 is a schematic diagram of defining a termination structure oxide layer and exposing a platform surface of an active region and a trench-type metal-oxide semi-structure according to the method of the present invention. FIG. 5A shows a cross-section of forming a S c h 〇 11 k y diode and a termination structure according to the method of the present invention. FIG. 5B shows a simulation diagram of a potential field and a power line of the S c h 〇 11 k y diode and the termination structure formed according to the method of the present invention. Figure 5C shows a comparison of the leakage current between the metal-oxygen half-structure without termination structure and the gold-milk half-structure with termination structure. Figure 6 shows the cross-section of the semiconductor substrate required to form the DMOS and termination structures of the present invention. FIG. 7 is a schematic cross-sectional view of the method according to the present invention after applying a high-temperature thermal oxidation process after the polycrystalline silicon layer is etched back. FIG. 8 is a schematic diagram of defining the termination structure oxide layer and exposing the surface of the platform and the trench-type metal-oxide half-structure according to the method of the present invention. Figure 9 shows a schematic cross-sectional view of a trenched DMOS and termination structure formed according to the method of the present invention.

Page 23 Brief Description of Drawings Figure 10 shows the cross-section of the semiconductor substrate required to form an insulated gate bipolar transistor and a termination structure according to the present invention. FIG. 11 is a schematic diagram of defining a termination structure oxide layer and exposing a platform surface of an active region and a trench-type metal-oxide half-structure according to the method of the present invention. FIG. 12 is a schematic cross-sectional view showing the formation of an insulated gate bipolar transistor and a termination structure according to the method of the present invention.

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Claims (1)

4 5 6 0 4 The formation of the French side-the end of the Xingsi Temple isomorphism and the formation of the semi-oxygen gold enclosure * & ditch ditch ^: tt Please rate one, six I · The lower degree is wide and contains less than the number of degrees. The width is reduced to a normal shape and square. The moving half of the area should extend to the plate extension base and the leading edge of the edge is in the groove. The distance from the platform is equal to one of the grooves on the other side of the groove. The first major number of the area on the edge of the groove is the same as that of the adjacent groove. This is due to the formation of the structure, the structure of the layered structure, the structure of the oxygen and oxygen, and the metal gate of the oxygen barrier. The gold side of the structure is formed into a shape for the other side and the whole system. The final temperature should be formed, the temperature should be high, and it should be used to phase the bottom of the trench and the trench on the wall side. The second and the slot. Fill in the half panel of the lead-back. The full base 'body is filled to the bottom and the oxygenated gate is stratified. • The surface characteristics of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface of the upper surface. The trough platform is flat, the first exposed, the bare exposed to the wall space, the exposed flat exposed, and the exposed front layer substrate of the exposed gas layer gate is semi-conductive; the faceted section is a conductive substrate on the upper layer. Half of the groove on the integral surface, the groove and the upper platform, the end of the layered oxygen structure, the gap between the grooves, the groove, the groove, the groove, the groove, the groove, the groove, the groove, and the groove. When touched and connected to the platform, the upper and lower layers of the body should conduct oxygen conduction. The structure of the surface stops the groove on the surface of the groove. The point in the first part of the figure is the wall resistance compound gap and the light is exposed. Grooved bare groove Page 25 6. The scope of the patent application is to etch the termination structure oxide layer with the photoresist pattern as a mask; remove the photoresist pattern; remove the gate oxide layer, the first conductor layer, and the termination structure oxidation on the back of the semiconductor substrate Layer to expose the semiconductor substrate; forming a second conductive layer in all regions in an entirety; and patterning the second conductive layer to form an anode. 2. For the method of claim 1 in the scope of patent application, wherein the above-mentioned metal-oxygen half structure is used to form a trench S ch 〇11 ky diode in the active region, so the semiconductor substrate includes at least a first conductive type A first substrate doped with a conductive impurity and a second substrate heavily doped with a first conductive impurity occupy the upper and lower sides of the semiconductor substrate, and the first trench, the platform, and the termination region structure are located at In the first substrate. 3. If the method of applying for the scope of the first item of the patent, the width of the above platform is about 0.2-4.0; «mo 4. If the method of applying for the scope of the first item of the patent, wherein the first groove and the second groove The forming step includes at least: forming an oxide layer on a semiconductor substrate; forming a photoresist pattern on the oxide layer to define a plurality of first trenches and a second trench, wherein a width of the second trench is much larger An anisotropic etching is performed on the first trench to transfer a photoresist pattern to the oxide layer Page 26 6. Applying for a patent; removing the photoresist pattern; applying an anisotropic etching to remove the exposed portion of the semiconductor substrate to form the second trench and the first trench described above, and using the oxidation The layer is a hard mask and the oxide layer is removed. 5. The method according to item 1 of the patent application range, wherein the first groove and the second groove have a depth of about 0. 4-1 0 // m. 6. The method according to item 1 of the patent application range, wherein the gate oxide layer is about 150 angstroms to 300 angstroms thick. 7. The method according to item 1 of the scope of patent application, wherein the first conductor layer is selected from one of metal, polycrystallite and amorphous sand. 8. The method according to item 1 of the patent application range, wherein the second trench is from the edge of the active region to the terminal of the semiconductor substrate. 9. The method according to item 1 of the scope of patent application, wherein the above-mentioned termination structure oxidation layer is one selected from the group consisting of HTO, LPTEOS, PETEOS, and ozone TEOS, silicon dioxide. 1 〇. The method of claim 1 in which the above-mentioned termination structure Page 27 456049 6. Scope of patent application The thickness of the oxide layer is about 2 to 10 # m. 1 1. As described in the method of item 1 of the patent, wherein the step of patterning the second conductive layer to form an anode is to make the second conductor layer extending from the active region to the second trench at least 2.0 from the edge of the active region # m. 12. The method according to item 1 of the scope of patent application, wherein the step of patterning the conductive layer is to form the formed conductive layer in the active area and extend to a part of the second trench to a preset area. Value width to connect the metal-oxide half-structure in the first trench and the metal-oxide half-structure in the second trench, wherein the preset value width is at least about 2.0 mm so that the empty region bends Stay away from the active area. 1 3. A method for simultaneously forming a trench-type metal-oxide-half structure and a termination structure, the method includes at least the following steps: forming a plurality of narrow first trenches in an active region of a semiconductor substrate, and one in the active region Edge and extend to the edge of the semiconductor substrate, the plurality of first trenches are separated from each other and the second trench is separated from the first trench adjacent to the edge of the active area by a platform, the first trench is used for A metal oxide half structure is formed, and the second trench is used to form a termination structure region and another side wall metal oxide half structure; a gate oxide layer is formed on the upper surface of the platform, the first surface by a high temperature thermal oxidation process. The sidewall and bottom of the trench and the second trench, and the back surface of the semiconductor substrate; Page 28 4 5 6 0 4 9 6. The scope of the patent application is to form a conductor layer on the gate oxide layer and fill at least the first trench and be higher than the upper surface of the platform; An anisotropic etching to remove the conductor layer until the gate oxide layer on the upper surface of the platform is exposed, and a conductor layer gap is formed on the side wall of the second trench; the gate on the platform is silver-etched An oxide layer; applying a high-temperature thermal oxidation process to partially oxidize the upper surface of the platform and the conductor layer to form a conductive interlayer oxide layer, and cause the surface of the conductor layer in the first trench to form the conductive interlayer oxide layer The semiconductor substrate lower than the upper surface of the platform; etching the conductive interlayer oxide layer on the upper surface of the semiconductor substrate platform to expose the semiconductor substrate on the upper surface of the platform; forming a termination structure oxide layer on the upper surface of the platform; A first conductive layer of the first trench, the second trench spacer, a bottom of the second trench, and a back surface of the semiconductor substrate; forming a photoresist pattern on the termination structure for oxidation A contact area is defined on the layer to expose the first conductor layer of the plurality of first trenches, the upper surface of the platform, and a portion of the upper surface of the second trench spacer; and etching the termination structure oxide layer to The photoresist pattern is a mask; removing the photoresist pattern; removing the gate oxide layer, the first conductor layer, and the termination structure oxide layer on the back surface of the semiconductor substrate to expose the semiconductor substrate to form a conductive layer in all areas; and the pattern; and The conductive layer is formed to form an electrode. Page 29 4 b 6 Ο 4 9 6. Application for Patent Scope 1 4. The method of item 13 in the scope of patent application, wherein the above-mentioned trench metal-oxide semi-structure is used to form a trench DMOS in the active region, Therefore, the semiconductor substrate includes at least one p-type doped first layer / n-type lightly doped second layer / n-doped base plate from top to bottom, and the first and second layers are epitaxial. The method is formed on the base board, and the upper part of the first layer is staggered with a plurality of P + regions and η + regions in a spaced manner. The above-mentioned first trench and termination region structure is formed in the above-mentioned first section. In one layer, the first trench is formed in a first layer doped with a region / p-type conductive impurity, and a second layer lightly doped with an n-type conductive impurity. 15. The method according to item 13 of the scope of patent application, wherein the above-mentioned trench-type metal-oxide semi-structure is used to form a trench-type I GBT in the active region, so the semiconductor substrate includes at least one p-type from top to bottom. First layer heavily doped with conductive impurities / Second layer doped with ρ-type conductive impurities / Third layer lightly doped with n-type conductive impurities / Fourth layer heavily doped with n-type conductive impurities / ρ A fifth layer heavily doped with conductive conductivity impurities, and a first layer heavily doped with p-type conductive impurities, and a plurality of n-type conductive heavy impurity regions are formed therein and extend from the upper surface of the semiconductor substrate to ρ The first layer is divided by the n-type conductive heavy impurity region, and the plurality of first trenches are formed in the n-type conductive heavy impurity. Region / p-type conductive impurity-doped second layer, to n-type conductive impurity-doped third layer. 16 6. The method according to item 13 of the scope of patent application, wherein the above-mentioned platform width Page 30 4 5.6 Ο 4 U Six, the scope of patent application is about 0.2-4. Oy m. 17. The method according to item 13 of the scope of patent application, wherein the steps of forming the first groove and the first groove at least include: a shaped groove and a groove; applying; applying to form a curtain; and removing Forming an oxide layer on a semiconductor substrate; forming a photoresist pattern on the oxide layer to define a plurality of first trenches and second trenches, wherein the width of the second trenches is much larger than that of the first trenches with an anisotropy Etching, to transfer the photoresist pattern to the oxide layer to remove the photoresist pattern; to perform an anisotropic etching to remove the above-mentioned second trench and the first trench of the exposed portion of the semiconductor substrate, and to use the halogenation The layer is a hard mask to remove the oxide layer. 1 8. The method according to item 13 of the scope of patent application, wherein the depth of the first groove and the second groove is about 0.4 to 4 m. 19. The method according to item 13 of the scope of patent application, wherein the thickness of the gate oxide layer is about 150 angstroms to 300 angstroms. 20. The method according to item 13 of the scope of patent application, wherein the aforementioned conductor layer is selected from one of a polycrystalline silicon layer or an amorphous silicon layer. Page 31 45604S VI. Application scope of patent 2 1. The method according to item 13 of the scope of patent application, wherein the above-mentioned second trench is from the edge of the active region to the above-mentioned semiconductor substrate terminal. 2 2. The method according to item 13 of the scope of patent application, wherein the above-mentioned termination structure oxide layer is one selected from the group consisting of HT0, LPTEOS, PETEOS, and ozone TEOS, dioxin, and the like. 2 3. The method according to item 13 of the scope of patent application, wherein the above-mentioned termination structure has an oxide layer thickness of about 0.2 to 1.0 μm. 2 4 · The method according to item 13 of the scope of patent application, wherein the above-mentioned step of patterning the conductive layer is to form the formed conductive layer in the active region and extend to a part of the second trench to a predetermined region. The width of the value is set to connect the metal-oxide half-structure in the first trench and the metal-oxide half-structure in the second trench, wherein the preset width is at least about 2. Oy m to make the empty region bend. Stay away from the active area. 2 5. A trench metal-oxide half-element and termination structure, the trench metal-oxide half-element and termination structure at least include: a narrow first trench formed in an active region of a semiconductor substrate, and a second trench The trenches are separated from the first trench by a platform, and are formed on the edge of the active region and extend to the edge of the semiconductor substrate. A gate oxide layer is formed on the sidewall, the bottom, and the first trench. Page 32 4 5 6 0 4 9 VI. Patent application scope 2 Side wall and part of the bottom of the trench; A first conductor layer is formed in the first trench and on the side wall of the second trench, so the first trench The first conductor layer, the gate oxide layer, and the semiconductor substrate inside constitute a first metal-oxide half structure, and the gate oxide layer on the side wall of the second trench, the first conductor layer, and the semiconductor substrate A second metal-oxygen half structure is also formed at the same time; a termination region oxide layer is formed at the bottom of the second trench and extends to cover a portion of the first conductor layer of the side wall of the second trench, so that the oxide region is not oxidized by the termination region. The covered portion is exposed; and a second conductor layer is formed in the active region to connect the first metal-oxide-semiconductor structure, the upper surface of the platform, and extend to connect the second metal-oxide-semiconductor structure not covered by the oxide layer of the termination region. On a conductor layer, a part of the oxide layer of the termination region is further extended to reduce electric field congestion. 26. For example, the trench metal-oxide half-element and termination structure according to item 25 of the patent application scope, wherein the metal-oxide half-element is used to form a trench Schottky diode in the active region, so the semiconductor substrate is at least A first substrate doped with a first conductive impurity and a second substrate heavily doped with a first conductive impurity occupy the upper and lower sides of the semiconductor substrate, and the first trench, the platform, The structure of the termination region is located in the above-mentioned first substrate. For example, the grooved metal-oxide half-element and the termination structure of item 25 of the patent application range, wherein the grooved metal-oxide half-element is used for active Groove Page 33 4 5 6 0 4 VI. Patent application slot DM 0S, so the semiconductor substrate contains at least one p-doped first layer / n-type lightly doped second layer / n-doped from top to bottom A heterogeneous base plate, the first layer and the second layer are formed on the base plate by a stupid crystal method, and the upper part of the '~~ layer has a plurality of P + regions and η + regions in a spaced manner. Staggered arrangement, in which the first trench and the termination region structure are formed in the first layer, and the first trench is formed in a first layer doped with n + region / p-type conductive impurities, to n-type conductive impurities are lightly doped in the second layer. 28. For example, the trench metal-oxide half-element and termination structure according to item 25 of the patent application scope, wherein the above-mentioned trench metal-oxide half-element is used to form a trench I GBT in the active region, so the semiconductor The substrate includes at least one p-type conductive impurity heavily doped first layer / p-type conductive impurity doped second layer / n-type conductive impurity lightly doped third layer / n-type conductivity from top to bottom The fourth layer heavily doped with impurities / the fifth layer heavily doped with ρ-type conductive impurities, and the first layer heavily doped with ρ-type conductive impurities and having a plurality of n-type conductive heavy impurity regions formed therein, And extends from the upper surface of the semiconductor substrate into the second layer doped with p-type conductive impurities. In addition, the plurality of first trenches are formed in the n-type conductive heavy impurity region / p-type conductive impurities. A second layer doped to a third layer lightly doped with n-type conductive impurities. 29. For example, the groove metal-oxide half-element and the termination structure in the scope of the patent application No. 25 include that every two adjacent first grooves are separated by a platform of the same width, and the width of each platform is about 0.2 -4. Ομ m " Page 34 4 5 6 0 4b: VI. Patent application scope 3 〇 If the patent application scope item 25 of the groove metal oxide half element and termination structure, the first groove and the second groove above the depth About 0.4-10 / z 3 1. The trench metal-oxide half-element and termination structure according to item 25 of the patent application scope, wherein the gate oxide layer is about 150 angstroms to 300 angstroms thick. 32. The trench metal-oxide half-element and termination structure according to item 25 of the patent application, wherein the first conductor layer is selected from one of a metal, a polycrystalline silicon layer, or an amorphous silicon layer. 3 3. The grooved metal-oxide half-element and termination structure according to item 25 of the patent application, wherein the thickness of the first conductor layer is about 0.5 to 3.0 μm. 34. The termination structure according to item 25 of the scope of patent application, wherein the above-mentioned termination structure oxide layer is one selected from the group consisting of HTO, LPTEOS, PETEOS, and ozone TE0S, stone dioxide. 35. The termination structure according to item 25 of the scope of patent application, wherein the oxide thickness of the termination structure is about 0.2 to 1.0 # m. Page 35