CN111092113B - Terminal area structure of metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Terminal area structure of metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN111092113B CN111092113B CN201811245314.2A CN201811245314A CN111092113B CN 111092113 B CN111092113 B CN 111092113B CN 201811245314 A CN201811245314 A CN 201811245314A CN 111092113 B CN111092113 B CN 111092113B
- Authority
- CN
- China
- Prior art keywords
- layer
- forming
- doped region
- trench
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 8
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 8
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 52
- 229920005591 polysilicon Polymers 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 238000010276 construction Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 147
- 238000000034 method Methods 0.000 claims description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 210000000746 body region Anatomy 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 18
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
Abstract
The invention provides a terminal area structure of a metal oxide semiconductor field effect transistor and a manufacturing method thereof, wherein the manufacturing method sequentially comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and an epitaxial layer, and the epitaxial layer is formed above the substrate; forming a doped region on the epitaxial layer; forming a plurality of trench rings in the doped region, wherein the trench rings penetrate through the doped region and enter the epitaxial layer; forming a gate oxide layer in each trench ring; depositing polysilicon over the gate oxide layer; performing polysilicon back etching to form two self-aligned island-shaped polysilicon regions on the two side walls of each ditch ring, wherein the two island-shaped polysilicon regions are not contacted with each other; forming an insulating oxide layer in each trench ring, wherein the insulating oxide layer covers the upper parts of the two island-shaped polysilicon areas; and covering the metal layer on the doped region, and performing pattern construction on the metal layer to form a discontinuous metal layer. The terminal region structure of the metal oxide semiconductor field effect transistor has medium and high breakdown voltage and is not influenced by the depth of the trench ring.
Description
Technical Field
The present invention relates to a termination region structure of a mosfet and a method for fabricating the same, and more particularly, to a termination region structure of a mosfet with a medium-high voltage guard ring and a method for fabricating the same.
Background
Mosfet is widely used in switching devices of electrical devices, such as power supplies, rectifiers, or low voltage motor controllers. Conventional mosfet devices are usually designed in a vertical structure, such as trench (mosfet) devices, to increase device density. In general, a mosfet has a body region with a transistor device and a termination region located at an edge of the body region to improve a voltage-withstanding capability of the device edge. The most common design method of the termination region is to form a plurality of guard rings (guard rings) by using the well region, so as to reduce the electric field of the termination region to force the breakdown point of the device to occur in the body region. In order not to reduce the overall breakdown voltage capability of the body region, it is desirable to ensure that the breakdown voltage (which is the lateral breakdown voltage) in the termination region is greater than the breakdown voltage (which is the vertical breakdown voltage) of the body region.
In the conventional termination region structure of the guard ring formed by the well region, the guard ring depth (i.e. the well region depth) is proportional to the breakdown voltage, and the breakdown voltage can be increased by increasing the guard ring depth, however, in the semiconductor process, the deeper the well region depth, the higher the thermal budget is required to diffuse the impurity, so the withstand voltage is proportional to the thickness of the epitaxial layer. Such a process may make it practically necessary to use a thicker epitaxial layer for the product, and such a selection may increase the on-resistance of the product, which is disadvantageous in production.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present invention is to provide a termination region structure of a mosfet having a medium-high breakdown voltage and not affected by the depth of the guard ring and a method for fabricating the same.
In order to achieve the above object, the present invention provides a method for manufacturing a termination region structure of a mosfet, comprising the following steps in order: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate (substrate) and an epitaxial layer (epitaxial layer) formed above the substrate; forming a doped region on the epitaxial layer; forming a plurality of trench rings in the doped region, wherein the trench rings penetrate through the doped region and enter the epitaxial layer; forming a gate oxide layer in each trench ring; depositing polysilicon over the gate oxide layer; performing polysilicon back etching to form two self-aligned island-shaped polysilicon regions on the two side walls of each ditch ring, wherein the two island-shaped polysilicon regions are not contacted with each other; forming an insulating oxide layer in each trench ring, wherein the insulating oxide layer covers the upper parts of the two island-shaped polysilicon areas; and covering the metal layer on the doped region, and performing pattern construction on the metal layer to form a discontinuous metal layer.
In one embodiment, forming a trench ring in the doped region sequentially comprises the steps of: depositing a hard mask (hard mask) over the doped region; forming a patterned photoresist (patterned photoresist) over the hard mask; performing trench ring pattern construction by using the patterned photoresist on the hard mask; and performing dry etching to form a trench ring in the doped region.
In one embodiment, after forming the trench rings in the doped regions and before forming the gate oxide layer in each of the trench rings, the method further comprises the steps of: forming a sacrificial oxide layer in each trench ring, and removing the sacrificial oxide layer.
In one embodiment, after forming the insulating oxide layer in each trench ring and before covering the metal layer in the doped region, the method further comprises the following steps: forming a patterned photoresist on the insulating oxide layer; etching the exposed insulating oxide layer by using the patterned photoresist in the main body region of the metal oxide semiconductor field effect transistor to form a contact window, and removing the patterned photoresist; and forming a source polycrystalline silicon region and a heavily doped region in the doped region of the main body region through the contact window.
In one embodiment, forming the insulating oxide layer in each trench ring sequentially comprises the steps of: forming an Inter-Layer Dielectric (ILD) Layer in each trench ring; a borophosphosilicate Glass (BPSG) layer is formed on the interlayer dielectric layer.
In one embodiment, patterning the metal layer to form a discontinuous metal layer comprises the following steps in order: depositing a metal layer over the doped region; forming a patterned photoresist over the metal layer; etching the metal layer by using the patterned photoresist and removing the patterned photoresist; and forming a discontinuous metal layer.
The invention also provides a terminal area structure of the metal oxide semiconductor field effect transistor, which comprises a semiconductor substrate, a doped area, a grid oxide layer, two island-shaped polysilicon areas, an insulating oxide layer and a discontinuous metal layer. The semiconductor substrate includes a substrate and an epitaxial layer formed over the substrate. The doped region is formed on the epitaxial layer, and the doped region is provided with a plurality of ditch rings, and the ditch rings penetrate through the doped region and enter the epitaxial layer. The gate oxide layer is formed in each trench ring. Two island-shaped polysilicon regions are formed on the gate oxide layers on the two side walls of each trench ring, and the two island-shaped polysilicon regions are not contacted with each other. An insulating oxide layer covers the two island-shaped polysilicon regions. The discontinuous metal layer is formed on the doped region, the gate oxide layer in the trench ring and the insulating oxide layer.
In one embodiment, the materials used for the two island-shaped polysilicon regions include: polysilicon, metal, amorphous silicon, or combinations thereof, and wherein the material used for the gate oxide layer is silicon oxide.
In one embodiment, the insulating oxide layer comprises an inter-layer dielectric layer and a borophosphosilicate glass layer. A boron phosphorus silicon glass layer is formed over the inter-layer dielectric layer.
Drawings
FIGS. 1A-1D are simplified cross-sectional views sequentially illustrating stages in a process of forming a trench ring in accordance with one embodiment of the present invention.
Fig. 2A-2B are simplified cross-sectional views sequentially illustrating stages in the process of forming and removing a sacrificial oxide layer in accordance with one embodiment of the present invention.
Fig. 3A-3C are simplified cross-sectional views sequentially illustrating stages in a process of forming an island-shaped polysilicon region in accordance with one embodiment of the present invention.
Fig. 4A-4C are simplified cross-sectional views illustrating various stages in the formation of an insulating oxide layer, a source polysilicon region, and a heavily doped region in accordance with one embodiment of the present invention.
Fig. 5A-5C are simplified cross-sectional views sequentially illustrating stages in a process of forming a discontinuous metal layer according to one embodiment of the present invention.
Description of the reference numerals
100: substrate and method for manufacturing the same
102: epitaxial layer
104: doped region
106: hard mask
108: patterned photoresist
110: trench ring
112: sacrificial oxide layer
114: gate oxide layer
116: polycrystalline silicon
118: island-shaped polysilicon region
120: an inter-layer dielectric layer
122: boron phosphorus silicon glass layer
123: patterned photoresist
124: source polysilicon region
126: heavily doped region
128: metal layer
130: patterned photoresist
132: discontinuous metal layer.
Detailed Description
In the drawings, the relative thicknesses and locations of film layers, regions and/or structural components may be reduced or exaggerated for clarity and some well-known components are omitted.
Fig. 1A-1D are simplified cross-sectional views sequentially illustrating stages in a process of forming a trench ring 110, wherein the leftmost edge of the body region of a mosfet, in accordance with an embodiment of the present invention. As shown in fig. 1A, a semiconductor substrate is provided in this embodiment. The semiconductor substrate may include a substrate 100 and an epitaxial layer 102. The substrate 100 is formed by ion implanting a heavy dopant of a first conductivity type into a silicon substrate. An epitaxial layer 102 is epitaxially grown over the substrate 100 and is formed by ion implantation of a light dopant of a first conductivity type. For example, in one embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In another embodiment, the first conductivity type is P-type and the second conductivity type is N-type. Next, as shown in fig. 1B, a blanket body implant and drive-in process is performed to form a second conductivity type doped region 104 along the epitaxial layer 102, such as a P-well region, over the epitaxial layer 102, and then a hard mask 106 is deposited over the doped region 104. Next, as shown in fig. 1C, a photoresist is coated over the hard mask 106 and exposed and developed using a photomask to form a patterned photoresist 108. Next, as shown in fig. 1D, the exposed hard mask 106 is etched using the patterned photoresist 108 as a mask, and then the patterned photoresist 108 is removed, so as to implement trench ring pattern formation on the hard mask 106 to define the position and the range of the trench ring, and then the exposed doped region 104 and the epitaxial layer 102 below the doped region 104 are etched (e.g. dry etched) using the remaining hard mask 106 as a mask, thereby forming a plurality of trench rings 110 in the doped region 104. The trench rings 110 are located in the termination region, independent of each other, and all around the body region edge.
Fig. 2A-2B are simplified cross-sectional views illustrating stages in the process of forming and removing sacrificial oxide 112, in accordance with one embodiment of the present invention. As shown in fig. 2A, a sacrificial oxide layer 112 is formed in each trench ring 110 by oxidation. At this time, the doped region 104 diffuses due to the thermal effect, and the thickness of the doped region 104 increases. Next, as shown in fig. 2B, the sacrificial oxide layer 112 and the hard mask 106 are removed.
Fig. 3A-3C are simplified cross-sectional views sequentially illustrating various stages in the process of forming island-shaped polysilicon region 118 in accordance with one embodiment of the present invention. As shown in fig. 3A, a gate oxide 114 is formed over the doped region 104 and covers the trench rings 110. Next, as shown in fig. 3B, polysilicon 116 is deposited on gate oxide 114 within trench ring 110 and fills each trench ring 110 using conventional polysilicon deposition techniques, such as chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), or other suitable film forming process. It should be noted that the trench ring 110 of the termination region is wider, about 10 times as wide as the trench of the body region, and each trench ring 110 is not filled with polysilicon 116. Next, as shown in fig. 3C, the polysilicon 116 is etched by using a conventional etching process, such as anisotropic etching, back etching, dry etching, etc., and two self-aligned island-shaped polysilicon regions 118 are formed on two sidewalls of each trench ring 110 when the polysilicon back etching is performed due to the wider width of the trench ring 110 of the termination region, and the two island-shaped polysilicon regions 118 are not in contact with each other.
Fig. 4A-4C are simplified cross-sectional views illustrating various stages in the process of forming the insulating oxide layer, the source polysilicon region 124, and the heavily doped region 126 in accordance with one embodiment of the present invention. As shown in fig. 4A, an insulating oxide layer is formed in each trench ring 110 by oxidation. In the termination region structure, the insulating oxide layer is used to cover the two island-shaped polysilicon regions 118, preventing the subsequent deposition of a metal layer (see discontinuous metal layer 132 shown in fig. 5C, below) from causing the two island-shaped polysilicon regions 118 to electrically connect to form an equipotential. In this embodiment, forming the insulating oxide layer in each trench ring 110 sequentially includes the following steps: an inter-layer dielectric layer 120 is formed within each trench ring 110, and a borophosphosilicate glass layer 122 is formed on the inter-layer dielectric layer 120. Next, as shown in fig. 4A, a photoresist is coated on the insulating oxide layer (the inter-layer dielectric layer 120 and the borophosphosilicate glass layer 122) and exposed and developed using a photomask to form a patterned photoresist 123. Next, as shown in fig. 4B, the exposed insulating oxide layer (the inter-layer dielectric layer 120 and the borophosphosilicate glass layer 122) is etched to form a contact window by using the patterned photoresist 123 as a mask in the body region of the mosfet (the leftmost edge of the body region of the mosfet in the figure), and then the patterned photoresist 123 is removed, and then a first conductive source polysilicon region 124, such as an N-type source region, is formed in the doped region 104 of the body region through the contact window by ion implantation. Next, as shown in fig. 4C, a blanket body implant and drive-in process is finally performed to form a heavily doped region 126 of the second conductivity type, such as a P-type heavily doped region.
Fig. 5A-5C are simplified cross-sectional views sequentially illustrating stages in the process of forming a discontinuous metal layer 132 in accordance with one embodiment of the present invention. As shown in fig. 5A, a metal layer 128 is deposited over the doped region 104. Next, as shown in fig. 5B, a photoresist is coated over the metal layer 128 and exposed and developed using a photomask to form a patterned photoresist 130. Next, as shown in fig. 5C, the patterned photoresist 130 is used as a mask to etch the metal layer 128 and remove the patterned photoresist 130, so as to form a discontinuous metal layer 132. The discontinuous metal layer 132 is used to sense the lateral potential of the termination structure of the mosfet, and to increase the lateral breakdown voltage of the termination structure of the mosfet.
As shown in fig. 5C, the termination region structure of the mosfet of the present embodiment includes a semiconductor substrate, a doped region 104, a gate oxide 114, two island-shaped polysilicon regions 118, an insulating oxide, and a discontinuous metal layer 132. The semiconductor substrate includes a substrate 100 and an epitaxial layer 102, the epitaxial layer 102 being formed over the substrate 100. Doped region 104 is formed on a semiconductor substrate, more specifically doped region 104 is formed on epitaxial layer 102. The doped region 104 has a plurality of trench rings 110. A gate oxide 114 is formed in each trench ring 110. Two island-shaped polysilicon regions 118 are formed on the gate oxide layer 114 on both sidewalls of each trench ring 110, the two island-shaped polysilicon regions 118 being not in contact with each other. An insulating oxide layer is formed over the two island-shaped polysilicon regions 118, more specifically, the insulating oxide layer includes an inter-layer dielectric layer 120 and a borophosphosilicate glass layer 122, and the borophosphosilicate glass layer 122 is formed over the inter-layer dielectric layer 120. A discontinuous metal layer 132 is formed over the doped region and the gate oxide 114 and insulating oxide within the trench ring 110.
In one embodiment, the material used for the two island-shaped polysilicon regions comprises polysilicon, metal, amorphous silicon, or a combination thereof, and the material used for the gate oxide layer is silicon oxide.
Tables 1 and 2 below show the simulation results of the guard ring depth and breakdown voltage under the same epitaxial layer conditions for the present invention and the conventional termination region structure, respectively. As shown in Table 1, the breakdown voltage of the termination region structure of the present invention is independent of the depth of the guard ring, so that the device design is more flexible, and the lateral breakdown voltage is induced by the two island-shaped polysilicon regions and the discontinuous metal layer which are not in contact with each other in each trench, and the total lateral breakdown voltage is increased in a voltage division manner, so that the device breakdown point occurs in the body region. As shown in table 2, the breakdown voltage of the conventional termination region structure is proportional to the guard ring depth, and a higher thermal budget is required to diffuse the impurities deeper the guard ring depth, and a thicker epitaxial layer is required to accommodate the guard ring, resulting in an increase in on-resistance.
TABLE 1
TABLE 2
The termination region structure of the present invention is particularly suitable for the termination region structure of a trench MOSFET, which can simultaneously form a trench ring of the termination region when the body region forms a trench, so that the integration can be easily performed to use the same three-layer photomask process (including forming patterned photoresist 108, 123 and 130) in the body region and the termination region, thereby shortening the process time and reducing the cost of the product. In addition, compared with the traditional well region type protection ring, the terminal region structure of the invention uses the trench type protection ring (so called as a trench ring), so that the length of the protection ring can be shortened, the area of a chip can be further reduced, the sensitivity of breakdown voltage and the depth of the protection ring can be reduced for the component in characteristics, and the yield and the stability can be further improved.
The foregoing description is for the purpose of explanation and specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are not shown in block diagram form. Intermediate structures may be included between the components of the figures. The components may include additional inputs and outputs, which are not depicted in detail in the figures.
If component a is connected (or coupled) to component B, component a may be directly connected (or coupled) to component B or indirectly connected (or coupled) to component B via component C. If the specification states a component, feature, structure, procedure, or characteristic A results in a component, feature, structure, procedure, or characteristic B, that represents at least a portion of the cause of B, or that other components, features, structures, procedures, or characteristics assist in causing B. The terms "may" and "may" used in the specification, the components, features, procedures or characteristics thereof are not limited in the specification; the numbers mentioned in the specification are not limited to words such as "a" or "an".
The invention is a breakthrough in that it shows features different from the prior art in all aspects, means and effects. It should be noted, however, that the above-described embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the scope of the invention. Although specific embodiments and applications have been illustrated and described herein, it is not intended that the embodiments be limited to the precise arrangements and modifications, and variations may be effected by one skilled in the art without departing from the spirit and principles of the invention. It will also be appreciated that various modifications, alterations, extensions of arrangement, operation, details of the method, and the apparatus and methods disclosed herein, which are obvious to those skilled in the art, may be made without departing from the spirit and scope of the present disclosure, and are not limited to the scope defined in the appended claims.
Claims (9)
1. A method for manufacturing a terminal region structure of a metal oxide semiconductor field effect transistor is characterized by comprising the following steps in sequence:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and an epitaxial layer, and the epitaxial layer is formed above the substrate;
forming a doped region on the epitaxial layer;
forming a plurality of trench rings in the doped region, wherein the plurality of trench rings penetrate through the doped region and enter the epitaxial layer;
forming a gate oxide layer in each trench ring;
depositing polysilicon over the gate oxide layer;
performing polysilicon back etching to form two self-aligned island-shaped polysilicon regions on two side walls of each ditch ring, wherein the two island-shaped polysilicon regions are not contacted with each other;
forming an insulating oxide layer in each trench ring, wherein the insulating oxide layer covers the upper parts of the two island-shaped polysilicon areas; and
and covering the metal layer on the doped region, and performing graph construction on the metal layer to form a discontinuous metal layer.
2. The method of claim 1, wherein forming the plurality of trench loops in the doped region comprises:
depositing a hard mask over the doped region;
forming a patterned photoresist on the hard mask;
performing trench ring pattern construction on the hard mask by using the patterned photoresist; and
and performing dry etching to form a plurality of ditch rings in the doped region.
3. The method of claim 1, wherein after forming the plurality of trench rings in the doped region and before forming the gate oxide layer in each of the trench rings, further comprising:
forming a sacrificial oxide layer in each trench ring, and removing the sacrificial oxide layer.
4. The method of claim 1, wherein after forming the insulating oxide layer in each of the trench rings and before covering the metal layer in the doped region, further comprising:
forming a patterned photoresist on the insulating oxide layer;
etching the exposed insulating oxide layer by using the patterned photoresist in the main body region of the metal oxide semiconductor field effect transistor to form a contact window, and removing the patterned photoresist; and
and forming a source polycrystalline silicon region and a heavily doped region in the doped region of the main body region through the contact window.
5. The method of manufacturing a termination region structure of a mosfet as recited in claim 1, wherein forming the insulating oxide layer in each of the trench rings comprises the steps of:
forming an inter-layer dielectric layer in each trench ring; and
and forming a boron phosphorus silicon glass layer on the inner dielectric layer.
6. The method of manufacturing a termination region structure of a mosfet of claim 1, wherein patterning the metal layer to form the discontinuous metal layer comprises, in order, the steps of:
depositing the metal layer over the doped region;
forming a patterned photoresist over the metal layer;
etching the metal layer by using the patterned photoresist and removing the patterned photoresist; and
the discontinuous metal layer is formed.
7. A termination region structure for a mosfet, comprising:
a semiconductor substrate comprising a substrate and an epitaxial layer, the epitaxial layer being formed over the substrate;
the doped region is formed on the epitaxial layer and is provided with a plurality of ditch rings, and the ditch rings penetrate through the doped region and enter the epitaxial layer;
a gate oxide layer formed in each of the trench rings;
two island-shaped polysilicon regions formed on the gate oxide layer on the two side walls of each trench ring, the two island-shaped polysilicon regions not contacting each other;
an insulating oxide layer covering the two island-shaped polysilicon regions; and
and the discontinuous metal layer is formed above the doped region, the gate oxide layer in the trench ring and the insulating oxide layer.
8. The mosfet termination structure of claim 7, wherein said two island-shaped polysilicon regions comprise a material comprising: polysilicon, metal, amorphous silicon, or a combination thereof, and wherein the material used for the gate oxide layer is silicon oxide.
9. The termination region structure of claim 7, wherein the insulating oxide layer comprises:
an inner dielectric layer; and
and the borophosphosilicate glass layer is formed above the inner dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811245314.2A CN111092113B (en) | 2018-10-24 | 2018-10-24 | Terminal area structure of metal oxide semiconductor field effect transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811245314.2A CN111092113B (en) | 2018-10-24 | 2018-10-24 | Terminal area structure of metal oxide semiconductor field effect transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111092113A CN111092113A (en) | 2020-05-01 |
| CN111092113B true CN111092113B (en) | 2023-06-02 |
Family
ID=70392244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811245314.2A Active CN111092113B (en) | 2018-10-24 | 2018-10-24 | Terminal area structure of metal oxide semiconductor field effect transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111092113B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304006A (en) * | 2007-05-09 | 2008-11-12 | 半导体元件工业有限责任公司 | Semiconductor component and method of manufacture |
| CN103180958A (en) * | 2010-10-21 | 2013-06-26 | 威世通用半导体公司 | Trench dmos device with improved termination structure for high voltage applications |
| CN105226020A (en) * | 2014-06-26 | 2016-01-06 | 英飞凌科技股份有限公司 | Containing semiconductor device and the manufacture method of power transistor cell and lateral transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI497602B (en) * | 2011-02-15 | 2015-08-21 | Tzu Hsiung Chen | Trench schottky diode and manufacturing mehtod thereof |
| TWI422043B (en) * | 2011-04-15 | 2014-01-01 | Pfc Device Corp | Rectifier with vertical mos structure and method manufacturing the same |
| TWI576920B (en) * | 2015-11-20 | 2017-04-01 | 敦南科技股份有限公司 | Diode device and manufacturing method thereof |
-
2018
- 2018-10-24 CN CN201811245314.2A patent/CN111092113B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304006A (en) * | 2007-05-09 | 2008-11-12 | 半导体元件工业有限责任公司 | Semiconductor component and method of manufacture |
| CN103180958A (en) * | 2010-10-21 | 2013-06-26 | 威世通用半导体公司 | Trench dmos device with improved termination structure for high voltage applications |
| CN105226020A (en) * | 2014-06-26 | 2016-01-06 | 英飞凌科技股份有限公司 | Containing semiconductor device and the manufacture method of power transistor cell and lateral transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111092113A (en) | 2020-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101729935B1 (en) | Method of forming an insulated gate field effect transistor device having a shield electrode structure | |
| US7417266B1 (en) | MOSFET having a JFET embedded as a body diode | |
| US10263070B2 (en) | Method of manufacturing LV/MV super junction trench power MOSFETs | |
| US8921173B2 (en) | Deep silicon via as a drain sinker in integrated vertical DMOS transistor | |
| US7964933B2 (en) | Integrated circuit including power diode | |
| JP5298565B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI407564B (en) | Power semiconductor with trench bottom poly and fabrication method thereof | |
| JP2014135494A (en) | Semiconductor element having dual parallel channel structure and method of manufacturing the same | |
| US8017494B2 (en) | Termination trench structure for mosgated device and process for its manufacture | |
| KR20190087786A (en) | Semiconductor device and method of manufacturing the same | |
| TWI566410B (en) | Semiconductor device, termination structure and method of forming the same | |
| TWI681458B (en) | Termination structure of mosfet and fabricating method thereof | |
| KR101469343B1 (en) | Vertical power mosfet and methods of forming the same | |
| CN108400166A (en) | The power transistor with terminal groove in terminal reduces surface field region | |
| CN112635540A (en) | LDMOS device and preparation method thereof | |
| US8039897B2 (en) | Lateral MOSFET with substrate drain connection | |
| US7948031B2 (en) | Semiconductor device and method of fabricating semiconductor device | |
| CN111092113B (en) | Terminal area structure of metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN109148557B (en) | Super junction device and manufacturing method thereof | |
| KR20090070783A (en) | Semiconductor device and method for manufacturing the same | |
| US20140120670A1 (en) | Trenched power mosfet with enhanced breakdown voltage and fabrication method thereof | |
| TWI571939B (en) | Lateral diffused metal oxide semiconductor device and method for fabricating the same | |
| CN113437148B (en) | Semiconductor structure and forming method thereof | |
| CN113437149B (en) | Semiconductor structure and forming method thereof | |
| JP4425295B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20221207 Address after: No. 555, Siyuan Road, Xinzhuang District, Xinbei City, Taiwan, China, China (24th floor) Applicant after: Force Mos Technology Co.,Ltd. Address before: China Taiwan New Taipei City three District Road No. 13 Building 111-5 Xing Applicant before: Heding Technology Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |